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1597 commits 2 branches 75 tags 7 MiB
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421 commits

Author SHA1 Message Date
CTCaer
fdf0dcc636 bdk: joycon: add info about sio imu report 2023-08-22 14:36:23 +03:00
CTCaer
f2bdc3f47c bdk: i2c: fix stack buffer overflow 2023-08-07 21:02:20 +03:00
CTCaer
1cc97ebc51 bdk: update various comments 2023-07-31 17:03:15 +03:00
CTCaer
1e28320e5a bdk: t210: add more mmio addresses 
And simplify relevant drivers that hardcoded them.
 2023-07-31 16:59:15 +03:00
CTCaer
f291a5cfa7 bdk: max17050: add reg dumping 2023-07-28 03:34:11 +03:00
CTCaer
9187fa7a8c bdk: fuse: add all t210b01 fuses 
And use B01 to distinguish the ones only on that SoC.
 2023-07-22 07:10:12 +03:00
CTCaer
b9bc35a22e bdk: dram: correct old comments 2023-07-21 18:39:46 +03:00
CTCaer
d7ad9b874b bdk: use the typedefs on jc calib 2023-06-11 13:27:48 +03:00
CTCaer
820e6d5a6e bdk: update cal0 struct 2023-06-10 23:48:45 +03:00
CTCaer
93ed4d0899 bdk: emc: add temp and feature reporting defines 2023-06-09 10:38:24 +03:00
CTCaer
01afd2de56 bdk: sdmmc: properly report comp pad status 
The reporting of the resistor being shorted or open was swapped. Fix that so it's immediately known what's the issue.
 2023-06-09 10:37:47 +03:00
CTCaer
d621d96af1 bdk: sdmmc: refactor comments 2023-06-09 10:36:29 +03:00
CTCaer
b674624ad0 bdk: timer: add instruction sleep 
usage:
`isleep(ILOOP(instructions))`

Each loop is 3 cycles, or approximately 7.35ns on 408MHz CPU clock.
 2023-06-09 10:33:11 +03:00
CTCaer
191a0533d9 bdk: clock: add more known pto ids 2023-06-09 10:29:47 +03:00
CTCaer
8502731fbd bdk: tsec: refactor some register names 2023-06-09 10:28:28 +03:00
CTCaer
18f3a1b70c bdk: max77620: reduce max DRAM VDDIO/Q 
Reduce allowed VDDIO/VDDQfor T210B01 and VDDIO for T210B01.
 2023-06-09 10:24:55 +03:00
CTCaer
c2ee6be2f5 bdk: sdram: add Samsung 8GB RAM support for T210 
And remove Copper support completely.
 2023-06-08 04:16:51 +03:00
CTCaer
73a133556d bdk: sdram: correct sku related info 
Validated so rename accordingly.
 2023-06-08 02:57:30 +03:00
CTCaer
7d3663616e bdk: sdram: name 2 of the new ram chips 
Not actually validated, but educated guess, since all previous one were correct in the end.
New Micron still unknown, can be guessed but model doesn't exist in any public list.
 2023-06-08 02:52:03 +03:00
CTCaer
e76aebabba bdk: mem: minerva: check table size in clock check 
Don't hardcode table size to 10.
 2023-06-08 02:45:34 +03:00
CTCaer
bc0eea11f3 bdk: joycon: add calibration struct 2023-06-08 02:44:35 +03:00
CTCaer
795b4ad26e bdk: sdmmc: increase bw priority to SDMMC1 for L4T 2023-04-06 17:30:01 +03:00
CTCaer
bb10b8aea3 bdk: sdmmc: small refactor 2023-04-06 10:19:53 +03:00
CTCaer
811fa4c88b bdk: sdmmc: add SD registers debug printing 
Can be enabled with `SDMMC_DEBUG_PRINT_SD_REGS`
 2023-04-06 10:13:35 +03:00
CTCaer
8528e6a08a bdk: util: do not edit rtc alarm in power function 2023-03-31 09:12:58 +03:00
CTCaer
27ae312227 bdk: minor naming edits 2023-03-31 09:11:55 +03:00
CTCaer
50811aacfa bdk: touch: reorder power on 
So touch IC reset can be properly done on a fast power cycle.
 2023-03-31 09:08:20 +03:00
CTCaer
f4bf48e76a bdk: sdmmc: add driver type set support 2023-03-31 09:04:10 +03:00
CTCaer
d258c82d52 bdk: sdmmc: add UHS DDR200 support 
The bdk flag BDK_SDMMC_UHS_DDR200_SUPPORT can be used to enable it.

SD Card DDR200 (DDR208) support

Proper procedure:
1. Check that Vendor Specific Command System is supported.
   Used as Enable DDR200 Bus.
2. Enable DDR200 bus mode via setting 14 to Group 2 via CMD6.
   Access Mode group is left to default 0 (SDR12).
3. Setup clock to 200 or 208 MHz.
4. Set host to DDR bus mode that supports such high clocks.
   Some hosts have special mode, others use DDR50 and others HS400.
5. Execute Tuning.

The true validation that this value in Group 2 activates it, is that DDR50 bus
and clocks/timings work fully after that point.

On Tegra X1, that can be done with DDR50 host mode.
Tuning though can't be done automatically on any DDR mode.
So it needs to be done manually and selected tap will be applied from the
biggest sampling window.

Finally, all that simply works, because the marketing materials for DDR200 are
basically overstatements to sell the feature. DDR200 is simply SDR104 in DDR mode,
so sampling on rising and falling edge and with variable output data window.
It can be supported by any host that is fast enough to support DDR at 200/208MHz
and can do hw/sw tuning for finding the proper sampling window in that mode.

Using a SDMMC controller on DDR200 mode at 400MHz, has latency allowance implications. The MC/EMC must be clocked enough to be able to serve the requests in time (512B in 1.28 ns).
 2023-03-31 08:54:13 +03:00
CTCaer
7f32c6d211 bdk: sd: better removal detection handling 2023-03-31 08:31:20 +03:00
CTCaer
2f7e841b50 bdk: sdmmc: move sdr12 setup for better readability 2023-03-31 08:29:20 +03:00
CTCaer
29e32f09fb bdk: sdmmc: properly identify sdmmc1 clk config 
Remove schmitt trigger config from clock pin on sdmmc1 for identifying previous pinmuxing state.
 2023-03-31 08:27:48 +03:00
CTCaer
b123571c56 bdk: sdmmc: only allow power raise if SDR50 and up 
As per spec.
 2023-03-31 08:26:19 +03:00
CTCaer
b7164a629f bdk: sdmmc: allow max power limit to be set 
Even if it defaults to 1.44W.
Some cards' firmware maybe be bugged.

The 3.3V regulator on all SKUs allow more than 800mA current anyway.
 2023-03-31 08:24:52 +03:00
CTCaer
25be98b7e3 bdk: sdmmc: add UHS DDR50 support 
But disable it by default in the auto selection.
 2023-03-31 08:23:10 +03:00
CTCaer
76a5facbc3 bdk: clock: rename clock_t to clk_rst_t 
To avoid redefines when standard math header is used.
 2023-03-31 08:18:45 +03:00
CTCaer
502fc1ed50 bdk: sdmmc: rename ddr100 to the actual HS100 name 2023-03-31 08:15:40 +03:00
CTCaer
5e134ed54b bdk: sdmmc: refactor defines 2023-03-31 08:00:14 +03:00
CTCaer
4cfe5f241e bdk: sdmmc: remove eMMC OC 
Additionally, the flag BDK_SDMMC_OC_AND_EXTRA_PRINT is now just BDK_SDMMC_EXTRA_PRINT
 2023-03-31 07:55:17 +03:00
CTCaer
9a222e0e49 bdk: sdmmc: rename divisor param to card clock 2023-03-31 07:53:46 +03:00
CTCaer
298893f404 bdk: sdmmc: remove powersave arg from sdmmc init 2023-03-31 07:51:43 +03:00
CTCaer
1ce5bb10f8 bdk: sdmmc: refactor debug prints 2023-03-31 07:49:26 +03:00
CTCaer
107fbd1d24 bdk: gpio: add debounce set function 
The debounce time is not per pin but per bank. So software should manage proper time for sibling pins
 2023-03-31 07:43:16 +03:00
CTCaer
1edb6583ac bdk: gpio: reorder gpio config 
Since there are some bootloaders that mess with the states of some power gpios, reorder gpio configuration for input/output in order to prevent power pin glitches.
 2023-03-31 07:41:50 +03:00
CTCaer
d286ee4e9d bdk: sd: only clear inserted when requested 
Also rename var to further explain its usage
 2023-02-23 01:25:05 +02:00
CTCaer
17cdd5af0d bdk: hwdeinit: restore order of bpmp clock set 
Restore order of bpmp clock scale down in deinit, in order to decrease pressure on clock deinits.
 2023-02-22 14:48:43 +02:00
CTCaer
55e01ca735 bdk: sd: improve init error handling 
- Management of sd init done is now on sd init retry function
 Also manages inserted, since it can set the sd init done to false if failed
- Init will now always check if SD is also initialized, since it doesn't manage it anymore. Because of that, mounting is no longer forced, but checked first.
- Unmount/End will now always set the sd as unmounted, since no data residue is expected after the fact

The above will improve handling of faulty SD cards or faulty SD readers.
 2023-02-22 13:19:12 +02:00
CTCaer
c279fa2521 bdk: max77621: ckkadv is basically an enum 2023-02-22 13:00:36 +02:00
CTCaer
9a98c1afb9 bdk: stylistic corrections 
And update copyrights
 2023-02-11 23:46:38 +02:00
CTCaer
72abe60a3b bdk: hw init: remove support for broken hwinits 
It's 2023 already.
 2023-02-11 23:19:56 +02:00
CTCaer
ee682fdf24 bdk: l4t: minerva: don't rely on UB 2023-02-11 23:17:27 +02:00
CTCaer
42859a2373 bdk: usb: ums: print errors when sdmmc init fails 2023-02-11 23:16:37 +02:00
CTCaer
22bdd0e0ff bdk: sdmmc: remove unused power limits 
Also name some magic numbers
 2023-02-11 23:15:28 +02:00
CTCaer
114abba815 bdk: hw init: do not touch audio clocks on t210b01 2023-02-11 23:13:41 +02:00
CTCaer
ec8c04db8a bdk: bpmp: add 563MHz clock for worst binnings 2023-02-11 23:12:14 +02:00
CTCaer
4d7eb6a647 bdk: clock: improve pllc deinit 2023-02-11 23:11:24 +02:00
CTCaer
fd3cf1b7f8 bdk: reg-5v: remove X3 pin 
X3 is vbus enable on mariko.
 2023-02-11 23:10:43 +02:00
CTCaer
47f0734ba0 bdk: display: add more oled color mode info 2023-02-11 23:09:38 +02:00
CTCaer
5bb9a244ea bdk: utilize new gpio functions 2023-02-11 23:08:32 +02:00
CTCaer
05b5e4f297 bdk: gpio: add simple gpio direction functions 2023-02-11 22:55:22 +02:00
CTCaer
4e15e034b8 bdk: sdram: remove (lp)ddr2/3 support 2023-02-11 22:44:31 +02:00
CTCaer
ee3fc499cd bdk: bm92t36: add sanity checks 
If bm92t i2c comms are broken, it can hang hekate. So sanitize buffer and max profile print supported.
 2023-02-11 22:40:47 +02:00
CTCaer
cfbfe403c6 bdk: di: wait 8ms before setting window for vic 2022-12-22 12:32:05 +02:00
CTCaer
50dd458cfd bdk: ums: use emmc_end instead of sdmmc_storage_end 2022-12-20 16:55:16 +02:00
CTCaer
0b1bb521d8 bdk: ini: add l4t key parsing 2022-12-19 05:38:03 +02:00
CTCaer
0e1eece04f bdk: hw-init: remove charger forced enable 
Anything that doesn't manage it properly should fix itself.
(Like for example disabling charging on sleep or something. They should use the gpio equivalent.)
 2022-12-19 05:35:04 +02:00
CTCaer
c9ab6352f6 bdk: rtc: add T210B01 R2P 2022-12-19 05:30:23 +02:00
CTCaer
09ca75dd8c bdk: max77812: exit if RAM reg and not 211 phase 2022-12-19 05:28:35 +02:00
CTCaer
560f077196 bdk: sdram: rename new dram chips 2022-12-19 05:25:26 +02:00
CTCaer
4d823d5909 bdk: slight refactor 2022-12-19 05:22:55 +02:00
CTCaer
a1fde0d9b6 bdk: display: disable LCD DVDD on display deinit 2022-12-19 05:16:35 +02:00
CTCaer
d0b22bf374 bdk: manage host1x only in hw init 2022-12-19 05:14:39 +02:00
CTCaer
6257d20db9 bdk: emmc: add emmc_set_partition 
Additionally, add SDMMC index info to errors.
 2022-12-19 04:53:50 +02:00
CTCaer
c0cc9c9f4f bdk: vic: ease stress to APB when enabling VIC clk 2022-10-13 00:16:08 +03:00
CTCaer
fe0bd89c4c bdk: pmc: extend pmc scratch locker 2022-10-11 14:41:42 +03:00
CTCaer
f534d5e316 bdk: i2c: fix send packet mode 2022-10-11 14:40:58 +03:00
CTCaer
2ea595e98d bdk: sdram: add new dram ids/configs 
On T210B01 dram ids 7 and 16 got removed.
29 to 34 were added.

Additionally, remove all deprecated and unused dram id enums.
 2022-10-11 10:38:43 +03:00
CTCaer
1a8075669d bdk: lvgl: allow theme to take a bg color value 2022-10-11 08:22:48 +03:00
CTCaer
9d889e2c3e bdk: Add driver for VIC 
VIC is a HW engine that allows for frame/texture buffer manipulation.
 2022-10-11 06:41:38 +03:00
CTCaer
bfad719fcd bdk: small refactor 2022-10-11 06:16:38 +03:00
CTCaer
07695196cb bdk: emmc: utilize emmc_end 2022-10-11 04:12:04 +03:00
CTCaer
8bbe403e41 bdk: util: replace strtol/atoi w/ custom versions 
To get rid of reentrancy baggage (which is not needed) and save binary space
 2022-10-11 04:11:21 +03:00
CTCaer
d08fac5a08 bdk: xusb: improve clock deinit 
Allows L4T to use XUSB on T210B01 after a UMS usage.
T210 somehow was fine.
 2022-10-11 04:07:24 +03:00
CTCaer
197ce4c76f bdk: sdmmc: timing changes 
- Correct HS102 naming to DDR100
- Fix clock for DDR50 (even if it's unused)
 2022-10-11 04:05:12 +03:00
CTCaer
eaa25114ad bdk: lvgl: do not do unneeded invalidations 
A bug was fixed that was causing full parent object invalidations when tapping into a window.

Now if the object is already on top the invalidation is skipped and the whole rerender/draw is skipped, saving valuable cpu time.
 2022-10-11 04:00:41 +03:00
CTCaer
0b2c2aa564 bdk: regulator 5V: improve management per SKU 2022-10-11 03:57:17 +03:00
CTCaer
2aa251c44f bdk: max77812: uncomment RAM regulator 2022-10-11 03:53:17 +03:00
CTCaer
c52c11e7bc bdk: mem: improve emc MRR reading 2022-10-11 03:51:12 +03:00
CTCaer
ff5ee9758d bdk: joycon: refactor some structs and comments 2022-10-11 03:49:18 +03:00
CTCaer
44b429d5cd bdk: display: Name panel 1040 to Sharp LQ055T1SW10 2022-10-11 03:45:49 +03:00
CTCaer
b891657fb6 bdk: tsec: fix regression on HOS 6.2.0 not booting 
With the latest BDK changes on enabling always on AHB redirect with a compile time flag, TSEC fw boot was regressed because it needs it off.

Always disable redirect and if the flag is enabled, enable it on exit.
 2022-07-11 22:28:09 +03:00
CTCaer
801ebd3543 bdk: xusb: fully clear device mode ctrl register on deinit 2022-07-11 22:13:13 +03:00
CTCaer
d259d6f6d6 bdk: watchdog: clear timer interrupt also in handling 2022-07-11 22:10:41 +03:00
CTCaer
70523e404f bdk: whitespace refactor 2022-07-11 22:10:11 +03:00
CTCaer
b787053c2d bdk: joycon: fixup hori pads 
For Hori game pads:
- Restore the no power down fix
- Revert RTS signal back to active high
 2022-07-01 13:47:41 +03:00
CTCaer
e921d8f51c bdk: update memory map with more used addresses 2022-06-29 12:13:04 +03:00
CTCaer
57c8fd1f8c bdk: fiq: watchdog handling 
`BDK_WATCHDOG_FIQ_ENABLE` enables watchdog handling.
`BDK_RESTART_BL_ON_WDT` causes a reload of bootloader on FIQ

These 2 are useful when wanting to detect and handle hangs.
 2022-06-29 12:12:03 +03:00
CTCaer
d38ddad873 bdk: display: correct night mode value 2022-06-27 10:27:18 +03:00
CTCaer
b0c0a86108 bdk: migrate timers/sleeps to timer driver 2022-06-27 10:22:19 +03:00
CTCaer
061e10152f bdk: timer: add timer/watchdog driver 2022-06-27 10:20:25 +03:00