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https://github.com/CTCaer/hekate
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bdk: sdmmc: refactor debug prints
This commit is contained in:
CTCaer
parent
107fbd1d24
commit
1ce5bb10f8
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@ -35,8 +35,9 @@ u32 sd_power_cycle_time_start;
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static inline u32 unstuff_bits(u32 *resp, u32 start, u32 size)
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{
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const u32 mask = (size < 32 ? 1 << size : 0) - 1;
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const u32 off = 3 - ((start) / 32);
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const u32 off = 3 - ((start) / 32);
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const u32 shft = (start) & 31;
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u32 res = resp[off] >> shft;
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if (size + shft > 32)
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res |= resp[off - 1] << ((32 - shft) % 32);
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@ -577,7 +578,7 @@ static int _mmc_storage_enable_HS(sdmmc_storage_t *storage, bool check_sts_befor
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if (!sdmmc_setup_clock(storage->sdmmc, SDHCI_TIMING_MMC_HS52))
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return 0;
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DPRINTF("[MMC] switched to HS52\n");
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DPRINTF("[MMC] switched to HS52\n");
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storage->csd.busspeed = 52;
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if (check_sts_before_clk_setup || _sdmmc_storage_check_status(storage))
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@ -597,7 +598,7 @@ static int _mmc_storage_enable_HS200(sdmmc_storage_t *storage)
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if (!sdmmc_tuning_execute(storage->sdmmc, SDHCI_TIMING_MMC_HS200, MMC_SEND_TUNING_BLOCK_HS200))
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return 0;
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DPRINTF("[MMC] switched to HS200\n");
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DPRINTF("[MMC] switched to HS200\n");
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storage->csd.busspeed = 200;
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return _sdmmc_storage_check_status(storage);
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@ -622,7 +623,7 @@ static int _mmc_storage_enable_HS400(sdmmc_storage_t *storage)
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if (!sdmmc_setup_clock(storage->sdmmc, SDHCI_TIMING_MMC_HS400))
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return 0;
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DPRINTF("[MMC] switched to HS400\n");
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DPRINTF("[MMC] switched to HS400\n");
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storage->csd.busspeed = 400;
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return _sdmmc_storage_check_status(storage);
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@ -668,44 +669,46 @@ int sdmmc_storage_init_mmc(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 bus_wid
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storage->sdmmc = sdmmc;
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storage->rca = 2; // Set default device address. This could be a config item.
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DPRINTF("[MMC]-[init: bus: %d, type: %d]\n", bus_width, type);
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if (!sdmmc_init(sdmmc, SDMMC_4, SDMMC_POWER_1_8, SDMMC_BUS_WIDTH_1, SDHCI_TIMING_MMC_ID, SDMMC_POWER_SAVE_DISABLE))
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return 0;
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DPRINTF("[MMC] after init\n");
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DPRINTF("[MMC] after init\n");
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usleep(1000 + (74000 + sdmmc->divisor - 1) / sdmmc->divisor);
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if (!_sdmmc_storage_go_idle_state(storage))
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return 0;
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DPRINTF("[MMC] went to idle state\n");
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DPRINTF("[MMC] went to idle state\n");
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if (!_mmc_storage_get_op_cond(storage, SDMMC_POWER_1_8))
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return 0;
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DPRINTF("[MMC] got op cond\n");
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DPRINTF("[MMC] got op cond\n");
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if (!_sdmmc_storage_get_cid(storage))
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return 0;
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DPRINTF("[MMC] got cid\n");
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DPRINTF("[MMC] got cid\n");
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if (!_mmc_storage_set_relative_addr(storage))
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return 0;
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DPRINTF("[MMC] set relative addr\n");
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DPRINTF("[MMC] set relative addr\n");
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if (!_sdmmc_storage_get_csd(storage))
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return 0;
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DPRINTF("[MMC] got csd\n");
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DPRINTF("[MMC] got csd\n");
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_mmc_storage_parse_csd(storage);
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if (!sdmmc_setup_clock(storage->sdmmc, SDHCI_TIMING_MMC_LS26))
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return 0;
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DPRINTF("[MMC] after setup clock\n");
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DPRINTF("[MMC] after setup clock\n");
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if (!_sdmmc_storage_select_card(storage))
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return 0;
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DPRINTF("[MMC] card selected\n");
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DPRINTF("[MMC] card selected\n");
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if (!_sdmmc_storage_set_blocklen(storage, 512))
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return 0;
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DPRINTF("[MMC] set blocklen to 512\n");
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DPRINTF("[MMC] set blocklen to 512\n");
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// Check system specification version, only version 4.0 and later support below features.
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if (storage->csd.mmca_vsn < CSD_SPEC_VER_4)
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@ -713,11 +716,11 @@ DPRINTF("[MMC] set blocklen to 512\n");
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if (!_mmc_storage_switch_buswidth(storage, bus_width))
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return 0;
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DPRINTF("[MMC] switched buswidth\n");
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DPRINTF("[MMC] switched buswidth\n");
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if (!mmc_storage_get_ext_csd(storage, (u8 *)SDMMC_UPPER_BUFFER))
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return 0;
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DPRINTF("[MMC] got ext_csd\n");
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DPRINTF("[MMC] got ext_csd\n");
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_mmc_storage_parse_cid(storage); // This needs to be after csd and ext_csd.
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@ -725,13 +728,13 @@ DPRINTF("[MMC] got ext_csd\n");
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if (storage->ext_csd.bkops & 0x1 && !(storage->ext_csd.bkops_en & EXT_CSD_AUTO_BKOPS_MASK))
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{
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_mmc_storage_enable_auto_bkops(storage);
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DPRINTF("[MMC] BKOPS enabled\n");
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DPRINTF("[MMC] BKOPS enabled\n");
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}
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*/
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if (!_mmc_storage_enable_highspeed(storage, storage->ext_csd.card_type, type))
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return 0;
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DPRINTF("[MMC] successfully switched to HS mode\n");
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DPRINTF("[MMC] successfully switched to HS mode\n");
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sdmmc_card_clock_powersave(storage->sdmmc, SDMMC_POWER_SAVE_ENABLE);
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@ -800,15 +803,17 @@ static int _sd_storage_send_if_cond(sdmmc_storage_t *storage, bool *is_sdsc)
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static int _sd_storage_get_op_cond_once(sdmmc_storage_t *storage, u32 *cond, bool is_sdsc, int bus_uhs_support)
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{
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sdmmc_cmd_t cmdbuf;
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// Support for Current > 150mA
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// Support for Current > 150mA.
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u32 arg = !is_sdsc ? SD_OCR_XPC : 0;
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// Support for handling block-addressed SDHC cards
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// Support for handling block-addressed SDHC cards.
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arg |= !is_sdsc ? SD_OCR_CCS : 0;
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// Support for 1.8V
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// Support for 1.8V signaling.
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arg |= (bus_uhs_support && !is_sdsc) ? SD_OCR_S18R : 0;
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// This is needed for most cards. Do not set bit7 even if 1.8V is supported.
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// Support for 3.3V power supply (VDD1).
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arg |= SD_OCR_VDD_32_33;
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sdmmc_init_cmd(&cmdbuf, SD_APP_OP_COND, arg, SDMMC_RSP_TYPE_3, 0);
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if (!_sd_storage_execute_app_cmd(storage, R1_SKIP_STATE_CHECK, is_sdsc ? R1_ILLEGAL_COMMAND : 0, &cmdbuf, NULL, NULL))
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return 0;
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@ -828,7 +833,7 @@ static int _sd_storage_get_op_cond(sdmmc_storage_t *storage, bool is_sdsc, int b
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// Check if power up is done.
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if (cond & SD_OCR_BUSY)
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{
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DPRINTF("[SD] op cond: %08X, lv: %d\n", cond, bus_uhs_support);
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DPRINTF("[SD] op cond: %08X, lv: %d\n", cond, bus_uhs_support);
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// Check if card is high capacity.
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if (cond & SD_OCR_CCS)
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@ -842,14 +847,15 @@ DPRINTF("[SD] op cond: %08X, lv: %d\n", cond, bus_uhs_support);
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{
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if (!sdmmc_enable_low_voltage(storage->sdmmc))
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return 0;
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storage->is_low_voltage = 1;
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DPRINTF("-> switched to low voltage\n");
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DPRINTF("-> switched to low voltage\n");
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}
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}
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else
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{
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DPRINTF("[SD] no low voltage support\n");
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DPRINTF("[SD] no low voltage support\n");
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}
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return 1;
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@ -897,8 +903,9 @@ static void _sd_storage_parse_scr(sdmmc_storage_t *storage)
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// unstuff_bits can parse only 4 u32
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u32 resp[4];
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resp[3] = *(u32 *)&storage->raw_scr[4];
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resp[2] = *(u32 *)&storage->raw_scr[0];
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memcpy(&resp[2], storage->raw_scr, 8);
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_debug_scr(storage->raw_scr);
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storage->scr.sda_vsn = unstuff_bits(resp, 56, 4);
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storage->scr.bus_widths = unstuff_bits(resp, 48, 4);
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@ -957,8 +964,6 @@ static int _sd_storage_switch_get(sdmmc_storage_t *storage, void *buf)
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if (!sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, &reqbuf, NULL))
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return 0;
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//gfx_hexdump(0, (u8 *)buf, 64);
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u32 tmp = 0;
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sdmmc_get_rsp(storage->sdmmc, &tmp, 4, SDMMC_RSP_TYPE_1);
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return _sdmmc_storage_check_card_status(tmp);
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@ -1036,15 +1041,14 @@ static int _sd_storage_enable_highspeed(sdmmc_storage_t *storage, u32 hs_type, u
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{
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if (!_sd_storage_switch(storage, buf, SD_SWITCH_CHECK, SD_SWITCH_GRP_ACCESS, hs_type))
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return 0;
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DPRINTF("[SD] supports (U)HS mode: %d\n", buf[16] & 0xF);
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u32 type_out = buf[16] & 0xF;
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if (type_out != hs_type)
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return 0;
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DPRINTF("[SD] supports selected (U)HS mode\n");
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DPRINTF("[SD] supports selected (U)HS mode %d\n", buf[16] & 0xF);
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u16 total_pwr_consumption = ((u16)buf[0] << 8) | buf[1];
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DPRINTF("[SD] max power: %d mW\n", total_pwr_consumption * 3600 / 1000);
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DPRINTF("[SD] max power: %d mW\n", total_pwr_consumption * 3600 / 1000);
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storage->card_power_limit = total_pwr_consumption;
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if (total_pwr_consumption <= 800)
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@ -1058,7 +1062,7 @@ DPRINTF("[SD] max power: %d mW\n", total_pwr_consumption * 3600 / 1000);
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return 1;
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}
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DPRINTF("[SD] card max power over limit\n");
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DPRINTF("[SD] card max power over limit\n");
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return 0;
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}
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@ -1072,7 +1076,7 @@ static int _sd_storage_enable_uhs_low_volt(sdmmc_storage_t *storage, u32 type, u
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u8 access_mode = buf[13];
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u16 power_limit = buf[7] | buf[6] << 8;
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DPRINTF("[SD] access: %02X, power: %02X\n", access_mode, power_limit);
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DPRINTF("[SD] access: %02X, power: %02X\n", access_mode, power_limit);
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// Try to raise the power limit to let the card perform better.
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_sd_storage_set_power_limit(storage, power_limit, buf);
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@ -1085,8 +1089,9 @@ DPRINTF("[SD] access: %02X, power: %02X\n", access_mode, power_limit);
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// Fall through if not supported.
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if (access_mode & SD_MODE_UHS_SDR104)
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{
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type = SDHCI_TIMING_UHS_SDR104;
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hs_type = UHS_SDR104_BUS_SPEED;
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DPRINTF("[SD] bus speed set to SDR104\n");
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DPRINTF("[SD] setting bus speed to SDR104\n");
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switch (type)
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{
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case SDHCI_TIMING_UHS_SDR104:
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@ -1098,12 +1103,13 @@ DPRINTF("[SD] bus speed set to SDR104\n");
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}
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break;
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}
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case SDHCI_TIMING_UHS_SDR50:
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if (access_mode & SD_MODE_UHS_SDR50)
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{
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type = SDHCI_TIMING_UHS_SDR50;
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type = SDHCI_TIMING_UHS_SDR50;
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hs_type = UHS_SDR50_BUS_SPEED;
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DPRINTF("[SD] bus speed set to SDR50\n");
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DPRINTF("[SD] setting bus speed to SDR50\n");
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storage->csd.busspeed = 50;
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break;
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}
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@ -1123,7 +1129,7 @@ DPRINTF("[SD] bus speed set to SDR25\n");
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return 0;
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type = SDHCI_TIMING_UHS_SDR12;
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hs_type = UHS_SDR12_BUS_SPEED;
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DPRINTF("[SD] bus speed set to SDR12\n");
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DPRINTF("[SD] bus speed set to SDR12\n");
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storage->csd.busspeed = 12;
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break;
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@ -1134,13 +1140,16 @@ DPRINTF("[SD] bus speed set to SDR12\n");
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if (!_sd_storage_enable_highspeed(storage, hs_type, buf))
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return 0;
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DPRINTF("[SD] card accepted UHS\n");
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DPRINTF("[SD] card accepted UHS\n");
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if (!sdmmc_setup_clock(storage->sdmmc, type))
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return 0;
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DPRINTF("[SD] after setup clock\n");
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DPRINTF("[SD] after setup clock\n");
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if (!sdmmc_tuning_execute(storage->sdmmc, type, MMC_SEND_TUNING_BLOCK))
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return 0;
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DPRINTF("[SD] after tuning\n");
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DPRINTF("[SD] after tuning\n");
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return _sdmmc_storage_check_status(storage);
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}
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@ -1151,7 +1160,7 @@ static int _sd_storage_enable_hs_high_volt(sdmmc_storage_t *storage, u8 *buf)
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u8 access_mode = buf[13];
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u16 power_limit = buf[7] | buf[6] << 8;
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DPRINTF("[SD] access: %02X, power: %02X\n", access_mode, power_limit);
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DPRINTF("[SD] access: %02X, power: %02X\n", access_mode, power_limit);
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// Try to raise the power limit to let the card perform better.
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_sd_storage_set_power_limit(storage, power_limit, buf);
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@ -1259,7 +1268,7 @@ int sd_storage_get_ssr(sdmmc_storage_t *storage, u8 *buf)
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if (!(storage->csd.cmdclass & CCC_APP_SPEC))
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{
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DPRINTF("[SD] ssr: Not supported\n");
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DPRINTF("[SD] ssr: Not supported\n");
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return 0;
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}
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@ -1323,7 +1332,7 @@ static void _sd_storage_parse_csd(sdmmc_storage_t *storage)
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break;
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default:
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DPRINTF("[SD] unknown CSD structure %d\n", storage->csd.structure);
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DPRINTF("[SD] unknown CSD structure %d\n", storage->csd.structure);
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break;
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}
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@ -1362,7 +1371,7 @@ int sdmmc_storage_init_sd(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 bus_widt
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u8 *buf = (u8 *)SDMMC_UPPER_BUFFER;
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bool bus_uhs_support = _sdmmc_storage_get_bus_uhs_support(bus_width, type);
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DPRINTF("[SD] init: bus: %d, type: %d\n", bus_width, type);
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DPRINTF("[SD]-[init: bus: %d, type: %d]\n", bus_width, type);
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// Some cards (SanDisk U1), do not like a fast power cycle. Wait min 100ms.
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sdmmc_storage_init_wait_sd();
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@ -1372,59 +1381,59 @@ DPRINTF("[SD] init: bus: %d, type: %d\n", bus_width, type);
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if (!sdmmc_init(sdmmc, SDMMC_1, SDMMC_POWER_3_3, SDMMC_BUS_WIDTH_1, SDHCI_TIMING_SD_ID, SDMMC_POWER_SAVE_DISABLE))
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return 0;
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DPRINTF("[SD] after init\n");
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DPRINTF("[SD] after init\n");
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usleep(1000 + (74000 + sdmmc->divisor - 1) / sdmmc->divisor);
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if (!_sdmmc_storage_go_idle_state(storage))
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return 0;
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DPRINTF("[SD] went to idle state\n");
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DPRINTF("[SD] went to idle state\n");
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if (!_sd_storage_send_if_cond(storage, &is_sdsc))
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return 0;
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DPRINTF("[SD] after send if cond\n");
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DPRINTF("[SD] after send if cond\n");
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if (!_sd_storage_get_op_cond(storage, is_sdsc, bus_uhs_support))
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return 0;
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DPRINTF("[SD] got op cond\n");
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DPRINTF("[SD] got op cond\n");
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if (!_sdmmc_storage_get_cid(storage))
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return 0;
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DPRINTF("[SD] got cid\n");
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DPRINTF("[SD] got cid\n");
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_sd_storage_parse_cid(storage);
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if (!_sd_storage_get_rca(storage))
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return 0;
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DPRINTF("[SD] got rca (= %04X)\n", storage->rca);
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DPRINTF("[SD] got rca (= %04X)\n", storage->rca);
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if (!_sdmmc_storage_get_csd(storage))
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return 0;
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DPRINTF("[SD] got csd\n");
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DPRINTF("[SD] got csd\n");
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_sd_storage_parse_csd(storage);
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if (!storage->is_low_voltage)
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{
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if (!sdmmc_setup_clock(storage->sdmmc, SDHCI_TIMING_SD_DS12))
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return 0;
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DPRINTF("[SD] after setup default clock\n");
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DPRINTF("[SD] after setup default clock\n");
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}
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if (!_sdmmc_storage_select_card(storage))
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return 0;
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DPRINTF("[SD] card selected\n");
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DPRINTF("[SD] card selected\n");
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||||
|
||||
if (!_sdmmc_storage_set_blocklen(storage, 512))
|
||||
return 0;
|
||||
DPRINTF("[SD] set blocklen to 512\n");
|
||||
DPRINTF("[SD] set blocklen to 512\n");
|
||||
|
||||
// Disconnect Card Detect resistor from DAT3.
|
||||
if (!_sd_storage_execute_app_cmd_type1(storage, &tmp, SD_APP_SET_CLR_CARD_DETECT, 0, 0, R1_STATE_TRAN))
|
||||
return 0;
|
||||
DPRINTF("[SD] cleared card detect\n");
|
||||
DPRINTF("[SD] cleared card detect\n");
|
||||
|
||||
if (!sd_storage_get_scr(storage, buf))
|
||||
return 0;
|
||||
DPRINTF("[SD] got scr\n");
|
||||
DPRINTF("[SD] got scr\n");
|
||||
|
||||
// If card supports a wider bus and if it's not SD Version 1.0 switch bus width.
|
||||
if (bus_width == SDMMC_BUS_WIDTH_4 && (storage->scr.bus_widths & BIT(SD_BUS_WIDTH_4)) && storage->scr.sda_vsn)
|
||||
|
|
@ -1433,26 +1442,26 @@ DPRINTF("[SD] got scr\n");
|
|||
return 0;
|
||||
|
||||
sdmmc_set_bus_width(storage->sdmmc, SDMMC_BUS_WIDTH_4);
|
||||
DPRINTF("[SD] switched to wide bus width\n");
|
||||
DPRINTF("[SD] switched to wide bus width\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
bus_width = SDMMC_BUS_WIDTH_1;
|
||||
DPRINTF("[SD] SD does not support wide bus width\n");
|
||||
DPRINTF("[SD] SD does not support wide bus width\n");
|
||||
}
|
||||
|
||||
if (storage->is_low_voltage)
|
||||
{
|
||||
if (!_sd_storage_enable_uhs_low_volt(storage, type, buf))
|
||||
return 0;
|
||||
DPRINTF("[SD] enabled UHS\n");
|
||||
DPRINTF("[SD] enabled UHS\n");
|
||||
}
|
||||
else if (type != SDHCI_TIMING_SD_DS12 && storage->scr.sda_vsn) // Not default speed and not SD Version 1.0.
|
||||
{
|
||||
if (!_sd_storage_enable_hs_high_volt(storage, buf))
|
||||
return 0;
|
||||
|
||||
DPRINTF("[SD] enabled HS\n");
|
||||
DPRINTF("[SD] enabled HS\n");
|
||||
switch (bus_width)
|
||||
{
|
||||
case SDMMC_BUS_WIDTH_4:
|
||||
|
|
@ -1468,7 +1477,7 @@ DPRINTF("[SD] enabled HS\n");
|
|||
// Parse additional card info from sd status.
|
||||
if (sd_storage_get_ssr(storage, buf))
|
||||
{
|
||||
DPRINTF("[SD] got sd status\n");
|
||||
DPRINTF("[SD] got sd status\n");
|
||||
}
|
||||
|
||||
sdmmc_card_clock_powersave(sdmmc, SDMMC_POWER_SAVE_ENABLE);
|
||||
|
|
@ -1516,13 +1525,13 @@ int sdmmc_storage_init_gc(sdmmc_storage_t *storage, sdmmc_t *sdmmc)
|
|||
|
||||
if (!sdmmc_init(sdmmc, SDMMC_2, SDMMC_POWER_1_8, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_DDR100, SDMMC_POWER_SAVE_DISABLE))
|
||||
return 0;
|
||||
DPRINTF("[gc] after init\n");
|
||||
DPRINTF("[GC] after init\n");
|
||||
|
||||
usleep(1000 + (10000 + sdmmc->divisor - 1) / sdmmc->divisor);
|
||||
|
||||
if (!sdmmc_tuning_execute(storage->sdmmc, SDHCI_TIMING_MMC_DDR100, MMC_SEND_TUNING_BLOCK_HS200))
|
||||
return 0;
|
||||
DPRINTF("[gc] after tuning\n");
|
||||
DPRINTF("[GC] after tuning\n");
|
||||
|
||||
sdmmc_card_clock_powersave(sdmmc, SDMMC_POWER_SAVE_ENABLE);
|
||||
|
||||
|
|
|
|||
|
|
@ -812,7 +812,7 @@ static u32 _sdmmc_check_mask_interrupt(sdmmc_t *sdmmc, u16 *pout, u16 mask)
|
|||
u16 norintsts = sdmmc->regs->norintsts;
|
||||
u16 errintsts = sdmmc->regs->errintsts;
|
||||
|
||||
DPRINTF("norintsts %08X, errintsts %08X\n", norintsts, errintsts);
|
||||
DPRINTF("norintsts %08X, errintsts %08X\n", norintsts, errintsts);
|
||||
|
||||
if (pout)
|
||||
*pout = norintsts;
|
||||
|
|
@ -1039,7 +1039,7 @@ static int _sdmmc_execute_cmd_inner(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_
|
|||
if (!result)
|
||||
EPRINTFARGS("SDMMC%d: Transfer timeout!", sdmmc->id + 1);
|
||||
#endif
|
||||
DPRINTF("rsp(%d): %08X, %08X, %08X, %08X\n", result,
|
||||
DPRINTF("rsp(%d): %08X, %08X, %08X, %08X\n", result,
|
||||
sdmmc->regs->rspreg0, sdmmc->regs->rspreg1, sdmmc->regs->rspreg2, sdmmc->regs->rspreg3);
|
||||
if (result)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in a new issue