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https://github.com/CTCaer/hekate
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bdk: joycon: refactor some structs and comments
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CTCaer
parent
a33663f759
commit
ff5ee9758d
1 changed files with 60 additions and 54 deletions
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@ -43,9 +43,11 @@
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#define JC_HORI_INPUT_RPT 0x00
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#define JC_WIRED_CMD_GET_INFO 0x01
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#define JC_WIRED_CMD_INIT_DONE 0x10
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#define JC_WIRED_CMD_BRATE_DONE 0x11
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#define JC_WIRED_CMD_SET_RATE 0x12 // Output report rate.
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#define JC_WIRED_CMD_CHRG_CFG 0x02
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#define JC_WIRED_CMD_WAKE_REASON 0x07
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#define JC_WIRED_CMD_HID_CONN 0x10
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#define JC_WIRED_CMD_HID_DISC 0x11
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#define JC_WIRED_CMD_SET_HIDRATE 0x12 // Output report rate.
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#define JC_WIRED_CMD_SET_BRATE 0x20
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#define JC_HID_OUTPUT_RPT 0x01
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@ -148,16 +150,16 @@ static const u8 init_switch_brate[] = {
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0xC0, 0xC6, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00
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};
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static const u8 init_switched_brate[] = {
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0x19, 0x01, 0x03, 0x07, 0x00, // Uart header.
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JC_WIRED_CMD, JC_WIRED_CMD_BRATE_DONE, // Wired cmd and subcmd.
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0x00, 0x00, 0x00, 0x00, 0x0E // Wired subcmd data and crc.
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static const u8 init_hid_disconnect[] = {
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0x19, 0x01, 0x03, 0x07, 0x00, // Uart header.
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JC_WIRED_CMD, JC_WIRED_CMD_HID_DISC, // Wired cmd and subcmd.
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0x00, 0x00, 0x00, 0x00, 0x0E // Wired subcmd data and crc.
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};
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static const u8 init_set_rpt_rate[] = {
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0x19, 0x01, 0x03, 0x0B, 0x00, // Uart header.
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JC_WIRED_CMD, JC_WIRED_CMD_SET_RATE, // Wired cmd and subcmd.
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0x04, 0x00, 0x00, 0x12, 0xA6, // Wired subcmd data, data crc and crc.
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static const u8 init_set_hid_rate[] = {
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0x19, 0x01, 0x03, 0x0B, 0x00, // Uart header.
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JC_WIRED_CMD, JC_WIRED_CMD_SET_HIDRATE, // Wired cmd and subcmd.
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0x04, 0x00, 0x00, 0x12, 0xA6, // Wired subcmd data, data crc and crc.
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// Output report rate 15 ms.
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0x0F, 0x00, 0x00, 0x00
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@ -166,10 +168,10 @@ static const u8 init_set_rpt_rate[] = {
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// 0x05, 0x00, 0x00, 0x00
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};
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static const u8 init_finalize[] = {
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0x19, 0x01, 0x03, 0x07, 0x00, // Uart header.
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JC_WIRED_CMD, JC_WIRED_CMD_INIT_DONE, // Wired cmd and subcmd.
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0x00, 0x00, 0x00, 0x00, 0x3D // Wired subcmd data and crc.
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static const u8 init_hid_connect[] = {
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0x19, 0x01, 0x03, 0x07, 0x00, // Uart header.
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JC_WIRED_CMD, JC_WIRED_CMD_HID_CONN, // Wired cmd and subcmd.
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0x00, 0x00, 0x00, 0x00, 0x3D // Wired subcmd data and crc.
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};
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static const u8 nx_pad_status[] = {
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@ -230,7 +232,7 @@ typedef struct _jc_hid_in_rpt_t
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u8 stick_h_right;
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u8 stick_m_right;
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u8 stick_v_right;
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u8 vib_decider;
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u8 vib_decider; // right:8, left:8. (bit3 en, bit2-0 buffer avail).
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u8 submcd_ack;
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u8 subcmd;
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u8 subcmd_data[];
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@ -255,27 +257,12 @@ typedef struct _jc_hid_in_pair_data_t
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u8 pad1;
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} jc_hid_in_pair_data_t;
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typedef struct _joycon_ctxt_t
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{
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u8 buf[0x100]; //FIXME: If heap is used, dumping breaks.
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u8 uart;
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u8 type;
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u8 state;
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u8 mac[6];
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u32 last_received_time;
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u32 last_status_req_time;
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u8 rumble_sent;
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u8 connected;
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u8 detected;
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u8 sio_mode;
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} joycon_ctxt_t;
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typedef struct _jc_sio_out_rpt_t
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{
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u8 cmd;
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u8 subcmd;
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u16 len;
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u8 unk[2];
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u16 payload_size;
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u8 data[2];
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u8 crc_payload;
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u8 crc_hdr;
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u8 payload[];
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@ -288,8 +275,8 @@ typedef struct _jc_sio_in_rpt_t
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u16 payload_size;
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u8 status;
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u8 unk;
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u8 payload_crc;
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u8 hdr_crc;
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u8 crc_payload;
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u8 crc_hdr;
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u8 payload[];
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} jc_sio_in_rpt_t;
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@ -305,7 +292,7 @@ typedef struct _jc_hid_in_sixaxis_rpt_t
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typedef struct _jc_sio_hid_in_rpt_t
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{
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u8 cmd;
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u8 type;
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u8 pkt_id;
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u8 unk;
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u8 btn_right;
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@ -322,6 +309,21 @@ typedef struct _jc_sio_hid_in_rpt_t
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jc_hid_in_sixaxis_rpt_t sixaxis[15];
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} jc_sio_hid_in_rpt_t;
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typedef struct _joycon_ctxt_t
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{
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u8 buf[0x100]; //FIXME: If heap is used, dumping breaks.
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u8 uart;
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u8 type;
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u8 state;
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u8 mac[6];
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u32 last_received_time;
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u32 last_status_req_time;
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u8 rumble_sent;
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u8 connected;
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u8 detected;
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u8 sio_mode;
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} joycon_ctxt_t;
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static joycon_ctxt_t jc_l = {0};
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static joycon_ctxt_t jc_r = {0};
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@ -679,11 +681,11 @@ static void _jc_parse_wired_init(joycon_ctxt_t *jc, const u8* data, u32 size)
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case JC_WIRED_CMD_SET_BRATE:
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jc->state = JC_STATE_BRATE_CHANGED;
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break;
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case JC_WIRED_CMD_BRATE_DONE:
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case JC_WIRED_CMD_HID_DISC:
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jc->state = JC_STATE_BRATE_OK;
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break;
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case JC_WIRED_CMD_INIT_DONE:
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case JC_WIRED_CMD_SET_RATE:
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case JC_WIRED_CMD_HID_CONN:
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case JC_WIRED_CMD_SET_HIDRATE:
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// done.
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default:
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break;
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@ -738,7 +740,7 @@ static void _jc_sio_parse_payload(joycon_ctxt_t *jc, u8 cmd, const u8* payload,
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static void _jc_sio_uart_pkt_parse(joycon_ctxt_t *jc, const jc_sio_in_rpt_t *pkt, u32 size)
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{
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if (pkt->hdr_crc != _jc_crc((u8 *)pkt, sizeof(jc_sio_in_rpt_t) - 1, 0))
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if (pkt->crc_hdr != _jc_crc((u8 *)pkt, sizeof(jc_sio_in_rpt_t) - 1, 0))
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return;
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u8 cmd = pkt->ack & (~JC_SIO_CMD_ACK);
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@ -787,7 +789,7 @@ static void _jc_rcv_pkt(joycon_ctxt_t *jc)
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// For Sio, check uart output report and command ack.
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jc_sio_in_rpt_t *sio_pkt = (jc_sio_in_rpt_t *)(jc->buf);
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if (jc->sio_mode && sio_pkt->cmd == 0x92 && (sio_pkt->ack & JC_SIO_CMD_ACK) == JC_SIO_CMD_ACK)
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if (jc->sio_mode && sio_pkt->cmd == JC_SIO_INPUT_RPT && (sio_pkt->ack & JC_SIO_CMD_ACK) == JC_SIO_CMD_ACK)
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{
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_jc_sio_uart_pkt_parse(jc, sio_pkt, sio_pkt->payload_size + sizeof(jc_sio_in_rpt_t));
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@ -1066,11 +1068,11 @@ static void _jc_init_conn(joycon_ctxt_t *jc)
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uart_init(jc->uart, 3000000, UART_AO_TX_MN_RX);
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uart_invert(jc->uart, true, UART_INVERT_TXD | UART_INVERT_RTS);
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// Handshake with the new speed.
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// Disconnect HID.
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retries = 10;
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while (retries && jc->state != JC_STATE_BRATE_OK)
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{
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_joycon_send_raw(jc->uart, init_switched_brate, sizeof(init_switched_brate));
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_joycon_send_raw(jc->uart, init_hid_disconnect, sizeof(init_hid_disconnect));
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msleep(5);
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_jc_rcv_pkt(jc);
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retries--;
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@ -1080,13 +1082,13 @@ static void _jc_init_conn(joycon_ctxt_t *jc)
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goto out;
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}
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// Finalize initialization.
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_joycon_send_raw(jc->uart, init_finalize, sizeof(init_finalize));
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// Create HID connection with the new rate.
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_joycon_send_raw(jc->uart, init_hid_connect, sizeof(init_hid_connect));
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msleep(2);
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_jc_rcv_pkt(jc);
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// Set packet rate.
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_joycon_send_raw(jc->uart, init_set_rpt_rate, sizeof(init_set_rpt_rate));
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// Set hid packet rate.
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_joycon_send_raw(jc->uart, init_set_hid_rate, sizeof(init_set_hid_rate));
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msleep(2);
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_jc_rcv_pkt(jc);
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}
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@ -1095,11 +1097,10 @@ static void _jc_init_conn(joycon_ctxt_t *jc)
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}
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else
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{
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// Set Sio POR low to configure BOOT0 mode.
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// Set Sio NPOR low to configure BOOT0 mode.
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gpio_write(GPIO_PORT_CC, GPIO_PIN_5, GPIO_LOW);
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usleep(300);
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gpio_write(GPIO_PORT_T, GPIO_PIN_0, GPIO_LOW);
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gpio_output_enable(GPIO_PORT_T, GPIO_PIN_1, GPIO_OUTPUT_DISABLE);
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gpio_write(GPIO_PORT_CC, GPIO_PIN_5, GPIO_HIGH);
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msleep(100);
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@ -1163,14 +1164,19 @@ void jc_init_hw()
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PINMUX_AUX(PINMUX_AUX_GPIO_PE7) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE | PINMUX_PULL_UP;
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gpio_config(GPIO_PORT_E, GPIO_PIN_7, GPIO_MODE_GPIO);
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// Configure Sio RST and BOOT0.
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// Configure Sio NRST and BOOT0.
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PINMUX_AUX(PINMUX_AUX_CAM1_STROBE) = PINMUX_PULL_DOWN | 1;
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PINMUX_AUX(PINMUX_AUX_CAM2_PWDN) = PINMUX_PULL_DOWN | 1;
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gpio_config(GPIO_PORT_T, GPIO_PIN_1 | GPIO_PIN_0, GPIO_MODE_GPIO);
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gpio_output_enable(GPIO_PORT_T, GPIO_PIN_1 | GPIO_PIN_0, GPIO_OUTPUT_ENABLE);
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gpio_write(GPIO_PORT_T, GPIO_PIN_1 | GPIO_PIN_0, GPIO_LOW);
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// Configure Sio POR.
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// Set BOOT0 to flash mode. (output high is sram mode).
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gpio_output_enable(GPIO_PORT_T, GPIO_PIN_0, GPIO_OUTPUT_ENABLE);
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gpio_write(GPIO_PORT_T, GPIO_PIN_0, GPIO_LOW);
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// NRST to pull down.
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gpio_output_enable(GPIO_PORT_T, GPIO_PIN_1, GPIO_OUTPUT_DISABLE);
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// Configure Sio NPOR.
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PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN1) = PINMUX_IO_HV | PINMUX_LPDR | 1;
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gpio_config(GPIO_PORT_CC, GPIO_PIN_5, GPIO_MODE_GPIO);
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gpio_output_enable(GPIO_PORT_CC, GPIO_PIN_5, GPIO_OUTPUT_ENABLE);
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@ -1233,7 +1239,7 @@ void jc_deinit()
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}
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else
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{
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// Disable Sio POR.
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// Disable Sio NPOR.
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gpio_write(GPIO_PORT_CC, GPIO_PIN_5, GPIO_LOW);
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// Disable 4 MHz clock to Sio.
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