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1525 commits 2 branches 73 tags 6.3 MiB
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121 commits

Author SHA1 Message Date
CTCaer b584a3f53a bdk: add several defines 2023-12-25 04:08:34 +02:00
CTCaer 7f98fb736a bdk: hwinit: reorder sdmmc1 reg disable 2023-12-25 04:07:26 +02:00
CTCaer 87c50732c0 bdk: fuse: simplify idle wait 2023-12-25 03:47:26 +02:00
CTCaer 504659a39b bdk: actmon: switch to averaged sampling 2023-12-25 03:46:05 +02:00
CTCaer ce137852b7 bdk: change some defines and comments 2023-10-12 06:59:15 +03:00
CTCaer f2bdc3f47c bdk: i2c: fix stack buffer overflow 2023-08-07 21:02:20 +03:00
CTCaer 1e28320e5a bdk: t210: add more mmio addresses 
And simplify relevant drivers that hardcoded them.
 2023-07-31 16:59:15 +03:00
CTCaer 9187fa7a8c bdk: fuse: add all t210b01 fuses 
And use B01 to distinguish the ones only on that SoC.
 2023-07-22 07:10:12 +03:00
CTCaer b674624ad0 bdk: timer: add instruction sleep 
usage:
`isleep(ILOOP(instructions))`

Each loop is 3 cycles, or approximately 7.35ns on 408MHz CPU clock.
 2023-06-09 10:33:11 +03:00
CTCaer 191a0533d9 bdk: clock: add more known pto ids 2023-06-09 10:29:47 +03:00
CTCaer 8502731fbd bdk: tsec: refactor some register names 2023-06-09 10:28:28 +03:00
CTCaer c2ee6be2f5 bdk: sdram: add Samsung 8GB RAM support for T210 
And remove Copper support completely.
 2023-06-08 04:16:51 +03:00
CTCaer 27ae312227 bdk: minor naming edits 2023-03-31 09:11:55 +03:00
CTCaer d258c82d52 bdk: sdmmc: add UHS DDR200 support 
The bdk flag BDK_SDMMC_UHS_DDR200_SUPPORT can be used to enable it.

SD Card DDR200 (DDR208) support

Proper procedure:
1. Check that Vendor Specific Command System is supported.
   Used as Enable DDR200 Bus.
2. Enable DDR200 bus mode via setting 14 to Group 2 via CMD6.
   Access Mode group is left to default 0 (SDR12).
3. Setup clock to 200 or 208 MHz.
4. Set host to DDR bus mode that supports such high clocks.
   Some hosts have special mode, others use DDR50 and others HS400.
5. Execute Tuning.

The true validation that this value in Group 2 activates it, is that DDR50 bus
and clocks/timings work fully after that point.

On Tegra X1, that can be done with DDR50 host mode.
Tuning though can't be done automatically on any DDR mode.
So it needs to be done manually and selected tap will be applied from the
biggest sampling window.

Finally, all that simply works, because the marketing materials for DDR200 are
basically overstatements to sell the feature. DDR200 is simply SDR104 in DDR mode,
so sampling on rising and falling edge and with variable output data window.
It can be supported by any host that is fast enough to support DDR at 200/208MHz
and can do hw/sw tuning for finding the proper sampling window in that mode.

Using a SDMMC controller on DDR200 mode at 400MHz, has latency allowance implications. The MC/EMC must be clocked enough to be able to serve the requests in time (512B in 1.28 ns).
 2023-03-31 08:54:13 +03:00
CTCaer 76a5facbc3 bdk: clock: rename clock_t to clk_rst_t 
To avoid redefines when standard math header is used.
 2023-03-31 08:18:45 +03:00
CTCaer 502fc1ed50 bdk: sdmmc: rename ddr100 to the actual HS100 name 2023-03-31 08:15:40 +03:00
CTCaer 107fbd1d24 bdk: gpio: add debounce set function 
The debounce time is not per pin but per bank. So software should manage proper time for sibling pins
 2023-03-31 07:43:16 +03:00
CTCaer 1edb6583ac bdk: gpio: reorder gpio config 
Since there are some bootloaders that mess with the states of some power gpios, reorder gpio configuration for input/output in order to prevent power pin glitches.
 2023-03-31 07:41:50 +03:00
CTCaer 17cdd5af0d bdk: hwdeinit: restore order of bpmp clock set 
Restore order of bpmp clock scale down in deinit, in order to decrease pressure on clock deinits.
 2023-02-22 14:48:43 +02:00
CTCaer 9a98c1afb9 bdk: stylistic corrections 
And update copyrights
 2023-02-11 23:46:38 +02:00
CTCaer 72abe60a3b bdk: hw init: remove support for broken hwinits 
It's 2023 already.
 2023-02-11 23:19:56 +02:00
CTCaer 114abba815 bdk: hw init: do not touch audio clocks on t210b01 2023-02-11 23:13:41 +02:00
CTCaer ec8c04db8a bdk: bpmp: add 563MHz clock for worst binnings 2023-02-11 23:12:14 +02:00
CTCaer 4d7eb6a647 bdk: clock: improve pllc deinit 2023-02-11 23:11:24 +02:00
CTCaer 5bb9a244ea bdk: utilize new gpio functions 2023-02-11 23:08:32 +02:00
CTCaer 05b5e4f297 bdk: gpio: add simple gpio direction functions 2023-02-11 22:55:22 +02:00
CTCaer 0e1eece04f bdk: hw-init: remove charger forced enable 
Anything that doesn't manage it properly should fix itself.
(Like for example disabling charging on sleep or something. They should use the gpio equivalent.)
 2022-12-19 05:35:04 +02:00
CTCaer 4d823d5909 bdk: slight refactor 2022-12-19 05:22:55 +02:00
CTCaer d0b22bf374 bdk: manage host1x only in hw init 2022-12-19 05:14:39 +02:00
CTCaer fe0bd89c4c bdk: pmc: extend pmc scratch locker 2022-10-11 14:41:42 +03:00
CTCaer f534d5e316 bdk: i2c: fix send packet mode 2022-10-11 14:40:58 +03:00
CTCaer 2ea595e98d bdk: sdram: add new dram ids/configs 
On T210B01 dram ids 7 and 16 got removed.
29 to 34 were added.

Additionally, remove all deprecated and unused dram id enums.
 2022-10-11 10:38:43 +03:00
CTCaer 9d889e2c3e bdk: Add driver for VIC 
VIC is a HW engine that allows for frame/texture buffer manipulation.
 2022-10-11 06:41:38 +03:00
CTCaer bfad719fcd bdk: small refactor 2022-10-11 06:16:38 +03:00
CTCaer 197ce4c76f bdk: sdmmc: timing changes 
- Correct HS102 naming to DDR100
- Fix clock for DDR50 (even if it's unused)
 2022-10-11 04:05:12 +03:00
CTCaer d259d6f6d6 bdk: watchdog: clear timer interrupt also in handling 2022-07-11 22:10:41 +03:00
CTCaer 70523e404f bdk: whitespace refactor 2022-07-11 22:10:11 +03:00
CTCaer 57c8fd1f8c bdk: fiq: watchdog handling 
`BDK_WATCHDOG_FIQ_ENABLE` enables watchdog handling.
`BDK_RESTART_BL_ON_WDT` causes a reload of bootloader on FIQ

These 2 are useful when wanting to detect and handle hangs.
 2022-06-29 12:12:03 +03:00
CTCaer b0c0a86108 bdk: migrate timers/sleeps to timer driver 2022-06-27 10:22:19 +03:00
CTCaer 061e10152f bdk: timer: add timer/watchdog driver 2022-06-27 10:20:25 +03:00
CTCaer 16af97c79a uart: rename print to printf 2022-06-25 05:42:42 +03:00
CTCaer bdb8f6d352 ccplex: name some flow control values 2022-06-25 05:42:19 +03:00
CTCaer e9587a325c bdk: fuse: add ipatch support for T210B01 2022-05-16 13:05:12 +03:00
CTCaer 87fe374b3b bdk: uart: use 2 STOP bits based on baudrate 2022-05-14 12:25:02 +03:00
CTCaer b56e788d12 bdk: pinmux: more proper uart pinmuxing 2022-05-14 12:20:57 +03:00
CTCaer 9e613a7600 bdk: hwinit: simplify uart debug port paths 2022-05-13 03:56:59 +03:00
CTCaer f452d916c9 bdk: clock: add ext peripheral clock control 2022-05-09 06:08:39 +03:00
CTCaer 12aac3a0fc bdk: clock: add 3 megabaud support for UART 2022-05-09 05:47:08 +03:00
CTCaer f7bf4af3ec bdk: uart: refactor and add new functionality 
- Allow to set CTS/RTS mode (only specific combos supported for now)
- Support the above modes in receiving
- Set 2 stop bits to decreases errors on high baudrates
 2022-05-08 05:45:16 +03:00
CTCaer 81730c5f7e bdk: pinmux/pmc: add more defines 2022-05-08 05:22:41 +03:00