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https://github.com/CTCaer/hekate
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bdk: pinmux/pmc: add more defines
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CTCaer
parent
76d1b4e221
commit
81730c5f7e
2 changed files with 130 additions and 87 deletions
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@ -39,6 +39,7 @@
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#define PINMUX_AUX_SDMMC3_DAT2 0x2C
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#define PINMUX_AUX_SDMMC3_DAT3 0x30
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#define PINMUX_AUX_SATA_LED_ACTIVE 0x4C
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#define PINMUX_AUX_GPIO_PA5_T210B01 PINMUX_AUX_SATA_LED_ACTIVE
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#define PINMUX_AUX_DMIC3_CLK 0xB4
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#define PINMUX_AUX_DMIC3_DAT 0xB8
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#define PINMUX_AUX_CAM_I2C_SCL 0xD4
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@ -46,7 +47,9 @@
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#define PINMUX_AUX_UART2_TX 0xF4
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#define PINMUX_AUX_UART3_TX 0x104
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#define PINMUX_AUX_DAP4_DIN 0x148
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#define PINMUX_AUX_DAP4_DOUT 0x14C
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#define PINMUX_AUX_DAP4_SCLK 0x150
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#define PINMUX_AUX_CLK_32K_OUT 0x164
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#define PINMUX_AUX_GPIO_X1_AUD 0x18C
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#define PINMUX_AUX_GPIO_X3_AUD 0x190
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#define PINMUX_AUX_SPDIF_IN 0x1A4
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@ -57,19 +60,25 @@
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#define PINMUX_AUX_AP_WAKE_NFC 0x1CC
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#define PINMUX_AUX_NFC_EN 0x1D0
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#define PINMUX_AUX_NFC_INT 0x1D4
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#define PINMUX_AUX_CAM_RST 0x1E0
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#define PINMUX_AUX_CAM1_PWDN 0x1EC
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#define PINMUX_AUX_CAM2_PWDN 0x1F0
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#define PINMUX_AUX_CAM1_STROBE 0x1F4
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#define PINMUX_AUX_LCD_BL_PWM 0x1FC
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#define PINMUX_AUX_LCD_BL_EN 0x200
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#define PINMUX_AUX_LCD_RST 0x204
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#define PINMUX_AUX_LCD_GPIO1 0x208
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#define PINMUX_AUX_LCD_GPIO2 0x20C
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#define PINMUX_AUX_TOUCH_CLK 0x218
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#define PINMUX_AUX_TOUCH_INT 0x220
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#define PINMUX_AUX_MOTION_INT 0x224
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#define PINMUX_AUX_ALS_PROX_INT 0x228
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#define PINMUX_AUX_BUTTON_HOME 0x240
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#define PINMUX_AUX_GPIO_PE6 0x248
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#define PINMUX_AUX_GPIO_PE7 0x24C
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#define PINMUX_AUX_GPIO_PH6 0x250
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#define PINMUX_AUX_GPIO_PK3 0x260
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#define PINMUX_AUX_GPIO_PK7 0x270
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#define PINMUX_AUX_GPIO_PZ1 0x280
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/* Only in T210B01 */
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#define PINMUX_AUX_SDMMC2_DAT0 0x294
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208
bdk/soc/pmc.h
208
bdk/soc/pmc.h
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@ -22,96 +22,130 @@
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#include <utils/types.h>
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/*! PMC registers. */
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#define APBDEV_PMC_CNTRL 0x0
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#define PMC_CNTRL_MAIN_RST BIT(4)
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#define APBDEV_PMC_SEC_DISABLE 0x4
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#define APBDEV_PMC_PWRGATE_TOGGLE 0x30
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#define APBDEV_PMC_PWRGATE_STATUS 0x38
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#define APBDEV_PMC_NO_IOPOWER 0x44
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#define PMC_NO_IOPOWER_SDMMC1_IO_EN BIT(12)
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#define PMC_NO_IOPOWER_AUDIO_HV BIT(18)
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#define PMC_NO_IOPOWER_GPIO_IO_EN BIT(21)
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#define APBDEV_PMC_SCRATCH0 0x50
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#define PMC_SCRATCH0_MODE_WARMBOOT BIT(0)
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#define PMC_SCRATCH0_MODE_RCM BIT(1)
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#define PMC_SCRATCH0_MODE_PAYLOAD BIT(29)
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#define PMC_SCRATCH0_MODE_FASTBOOT BIT(30)
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#define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
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#define PMC_SCRATCH0_MODE_CUSTOM_ALL (PMC_SCRATCH0_MODE_RECOVERY | PMC_SCRATCH0_MODE_FASTBOOT | PMC_SCRATCH0_MODE_PAYLOAD)
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#define APBDEV_PMC_SCRATCH1 0x54
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#define APBDEV_PMC_SCRATCH20 0xA0
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#define APBDEV_PMC_SECURE_SCRATCH4 0xC0
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#define APBDEV_PMC_SECURE_SCRATCH5 0xC4
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#define APBDEV_PMC_PWR_DET_VAL 0xE4
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#define PMC_PWR_DET_SDMMC1_IO_EN BIT(12)
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#define PMC_PWR_DET_AUDIO_HV BIT(18)
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#define PMC_PWR_DET_GPIO_IO_EN BIT(21)
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#define APBDEV_PMC_DDR_PWR 0xE8
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#define APBDEV_PMC_USB_AO 0xF0
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#define APBDEV_PMC_CRYPTO_OP 0xF4
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#define PMC_CRYPTO_OP_SE_ENABLE 0
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#define PMC_CRYPTO_OP_SE_DISABLE 1
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#define APBDEV_PMC_SCRATCH33 0x120
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#define APBDEV_PMC_SCRATCH37 0x130
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#define PMC_SCRATCH37_KERNEL_PANIC_MAGIC 0x4E415054
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#define APBDEV_PMC_SCRATCH40 0x13C
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#define APBDEV_PMC_OSC_EDPD_OVER 0x1A4
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#define PMC_OSC_EDPD_OVER_OSC_CTRL_OVER 0x400000
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#define APBDEV_PMC_CLK_OUT_CNTRL 0x1A8
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#define PMC_CLK_OUT_CNTRL_CLK1_FORCE_EN BIT(2)
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#define APBDEV_PMC_RST_STATUS 0x1B4
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#define PMC_RST_STATUS_MASK 0x7
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#define PMC_RST_STATUS_POR 0
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#define PMC_RST_STATUS_WATCHDOG 1
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#define PMC_RST_STATUS_SENSOR 2
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#define PMC_RST_STATUS_SW_MAIN 3
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#define PMC_RST_STATUS_LP0 4
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#define PMC_RST_STATUS_AOTAG 5
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#define APBDEV_PMC_IO_DPD_REQ 0x1B8
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#define PMC_IO_DPD_REQ_DPD_OFF BIT(30)
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#define APBDEV_PMC_IO_DPD2_REQ 0x1C0
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#define APBDEV_PMC_VDDP_SEL 0x1CC
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#define APBDEV_PMC_DDR_CFG 0x1D0
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#define APBDEV_PMC_SECURE_SCRATCH6 0x224
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#define APBDEV_PMC_SECURE_SCRATCH7 0x228
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#define APBDEV_PMC_SCRATCH45 0x234
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#define APBDEV_PMC_SCRATCH46 0x238
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#define APBDEV_PMC_SCRATCH49 0x244
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#define APBDEV_PMC_TSC_MULT 0x2B4
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#define APBDEV_PMC_SEC_DISABLE2 0x2C4
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#define APBDEV_PMC_WEAK_BIAS 0x2C8
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#define APBDEV_PMC_REG_SHORT 0x2CC
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#define APBDEV_PMC_SEC_DISABLE3 0x2D8
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#define APBDEV_PMC_SECURE_SCRATCH21 0x334
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#define PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT 0x10
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#define APBDEV_PMC_SECURE_SCRATCH32 0x360
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#define APBDEV_PMC_SECURE_SCRATCH49 0x3A4
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#define APBDEV_PMC_CNTRL2 0x440
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#define PMC_CNTRL2_HOLD_CKE_LOW_EN 0x1000
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#define APBDEV_PMC_IO_DPD3_REQ 0x45C
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#define APBDEV_PMC_IO_DPD4_REQ 0x464
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#define APBDEV_PMC_UTMIP_PAD_CFG1 0x4C4
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#define APBDEV_PMC_UTMIP_PAD_CFG3 0x4CC
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#define APBDEV_PMC_DDR_CNTRL 0x4E4
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#define APBDEV_PMC_SEC_DISABLE4 0x5B0
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#define APBDEV_PMC_SEC_DISABLE5 0x5B4
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#define APBDEV_PMC_SEC_DISABLE6 0x5B8
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#define APBDEV_PMC_SEC_DISABLE7 0x5BC
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#define APBDEV_PMC_SEC_DISABLE8 0x5C0
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#define APBDEV_PMC_SEC_DISABLE9 0x5C4
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#define APBDEV_PMC_SEC_DISABLE10 0x5C8
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#define APBDEV_PMC_SCRATCH188 0x810
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#define APBDEV_PMC_SCRATCH190 0x818
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#define APBDEV_PMC_SCRATCH200 0x840
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#define APBDEV_PMC_CNTRL 0x0
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#define PMC_CNTRL_RTC_CLK_DIS BIT(1)
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#define PMC_CNTRL_RTC_RST BIT(2)
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#define PMC_CNTRL_MAIN_RST BIT(4)
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#define PMC_CNTRL_LATCHWAKE_EN BIT(5)
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#define PMC_CNTRL_BLINK_EN BIT(7)
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#define PMC_CNTRL_PWRREQ_OE BIT(9)
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#define PMC_CNTRL_SYSCLK_OE BIT(11)
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#define PMC_CNTRL_PWRGATE_DIS BIT(12)
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#define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14)
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#define PMC_CNTRL_CPUPWRREQ_OE BIT(16)
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#define PMC_CNTRL_FUSE_OVERRIDE BIT(18)
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#define PMC_CNTRL_SHUTDOWN_OE BIT(22)
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#define APBDEV_PMC_SEC_DISABLE 0x4
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#define APBDEV_PMC_PWRGATE_TOGGLE 0x30
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#define APBDEV_PMC_PWRGATE_STATUS 0x38
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#define APBDEV_PMC_NO_IOPOWER 0x44
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#define PMC_NO_IOPOWER_SDMMC1_IO_EN BIT(12)
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#define PMC_NO_IOPOWER_AUDIO_HV BIT(18)
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#define PMC_NO_IOPOWER_GPIO_IO_EN BIT(21)
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#define APBDEV_PMC_SCRATCH0 0x50
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#define PMC_SCRATCH0_MODE_WARMBOOT BIT(0)
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#define PMC_SCRATCH0_MODE_RCM BIT(1)
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#define PMC_SCRATCH0_MODE_PAYLOAD BIT(29)
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#define PMC_SCRATCH0_MODE_FASTBOOT BIT(30)
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#define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
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#define PMC_SCRATCH0_MODE_CUSTOM_ALL (PMC_SCRATCH0_MODE_RECOVERY | \
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PMC_SCRATCH0_MODE_FASTBOOT | \
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PMC_SCRATCH0_MODE_PAYLOAD)
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#define APBDEV_PMC_BLINK_TIMER 0x40
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#define PMC_BLINK_ON(n) ((n & 0x7FFF))
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#define PMC_BLINK_FORCE BIT(15)
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#define PMC_BLINK_OFF(n) ((u32)(n & 0xFFFF) << 16)
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#define APBDEV_PMC_SCRATCH1 0x54
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#define APBDEV_PMC_SCRATCH20 0xA0
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#define APBDEV_PMC_SECURE_SCRATCH4 0xC0
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#define APBDEV_PMC_SECURE_SCRATCH5 0xC4
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#define APBDEV_PMC_PWR_DET_VAL 0xE4
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#define PMC_PWR_DET_SDMMC1_IO_EN BIT(12)
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#define PMC_PWR_DET_AUDIO_HV BIT(18)
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#define PMC_PWR_DET_GPIO_IO_EN BIT(21)
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#define APBDEV_PMC_DDR_PWR 0xE8
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#define APBDEV_PMC_USB_AO 0xF0
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#define APBDEV_PMC_CRYPTO_OP 0xF4
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#define PMC_CRYPTO_OP_SE_ENABLE 0
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#define PMC_CRYPTO_OP_SE_DISABLE 1
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#define APBDEV_PMC_SCRATCH33 0x120
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#define APBDEV_PMC_SCRATCH37 0x130
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#define PMC_SCRATCH37_KERNEL_PANIC_MAGIC 0x4E415054 // "TPAN"
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#define APBDEV_PMC_SCRATCH40 0x13C
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#define APBDEV_PMC_OSC_EDPD_OVER 0x1A4
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#define PMC_OSC_EDPD_OVER_OSC_CTRL_OVER BIT(22)
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#define APBDEV_PMC_CLK_OUT_CNTRL 0x1A8
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#define PMC_CLK_OUT_CNTRL_CLK1_FORCE_EN BIT(2)
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#define PMC_CLK_OUT_CNTRL_CLK2_FORCE_EN BIT(10)
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#define APBDEV_PMC_RST_STATUS 0x1B4
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#define PMC_RST_STATUS_MASK 7
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#define PMC_RST_STATUS_POR 0
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#define PMC_RST_STATUS_WATCHDOG 1
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#define PMC_RST_STATUS_SENSOR 2
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#define PMC_RST_STATUS_SW_MAIN 3
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#define PMC_RST_STATUS_LP0 4
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#define PMC_RST_STATUS_AOTAG 5
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#define APBDEV_PMC_IO_DPD_REQ 0x1B8
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#define PMC_IO_DPD_REQ_DPD_OFF BIT(30)
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#define APBDEV_PMC_IO_DPD2_REQ 0x1C0
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#define APBDEV_PMC_VDDP_SEL 0x1CC
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#define APBDEV_PMC_DDR_CFG 0x1D0
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#define APBDEV_PMC_SECURE_SCRATCH6 0x224
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#define APBDEV_PMC_SECURE_SCRATCH7 0x228
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#define APBDEV_PMC_SCRATCH45 0x234
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#define APBDEV_PMC_SCRATCH46 0x238
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#define APBDEV_PMC_SCRATCH49 0x244
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#define APBDEV_PMC_TSC_MULT 0x2B4
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#define APBDEV_PMC_SEC_DISABLE2 0x2C4
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#define APBDEV_PMC_WEAK_BIAS 0x2C8
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#define APBDEV_PMC_REG_SHORT 0x2CC
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#define APBDEV_PMC_SEC_DISABLE3 0x2D8
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#define APBDEV_PMC_SECURE_SCRATCH21 0x334
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#define PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT BIT(4)
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#define APBDEV_PMC_SECURE_SCRATCH32 0x360
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#define APBDEV_PMC_SECURE_SCRATCH49 0x3A4
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#define APBDEV_PMC_CNTRL2 0x440
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#define PMC_CNTRL2_WAKE_INT_EN BIT(0)
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#define PMC_CNTRL2_WAKE_DET_EN BIT(9)
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#define PMC_CNTRL2_SYSCLK_ORRIDE BIT(10)
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#define PMC_CNTRL2_HOLD_CKE_LOW_EN BIT(12)
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#define PMC_CNTRL2_ALLOW_PULSE_WAKE BIT(14)
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#define APBDEV_PMC_IO_DPD3_REQ 0x45C
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#define APBDEV_PMC_IO_DPD4_REQ 0x464
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#define APBDEV_PMC_UTMIP_PAD_CFG1 0x4C4
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#define APBDEV_PMC_UTMIP_PAD_CFG3 0x4CC
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#define APBDEV_PMC_DDR_CNTRL 0x4E4
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#define APBDEV_PMC_SEC_DISABLE4 0x5B0
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#define APBDEV_PMC_SEC_DISABLE5 0x5B4
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#define APBDEV_PMC_SEC_DISABLE6 0x5B8
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#define APBDEV_PMC_SEC_DISABLE7 0x5BC
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#define APBDEV_PMC_SEC_DISABLE8 0x5C0
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#define APBDEV_PMC_SEC_DISABLE9 0x5C4
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#define APBDEV_PMC_SEC_DISABLE10 0x5C8
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#define APBDEV_PMC_SCRATCH188 0x810
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#define APBDEV_PMC_SCRATCH190 0x818
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#define APBDEV_PMC_SCRATCH200 0x840
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#define APBDEV_PMC_SECURE_SCRATCH108 0xB08
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#define APBDEV_PMC_SECURE_SCRATCH109 0xB0C
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#define APBDEV_PMC_SECURE_SCRATCH110 0xB10
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#define APBDEV_PMC_TZRAM_PWR_CNTRL 0xBE8
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#define PMC_TZRAM_PWR_CNTRL_SD BIT(0)
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#define APBDEV_PMC_TZRAM_SEC_DISABLE 0xBEC
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#define APBDEV_PMC_TZRAM_NON_SEC_DISABLE 0xBF0
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#define PMC_TZRAM_DISABLE_REG_WRITE BIT(0)
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#define PMC_TZRAM_DISABLE_REG_READ BIT(1)
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// Only in T210B01.
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#define APBDEV_PMC_LED_BREATHING_CTRL 0xB48
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#define PMC_LED_BREATHING_CTRL_ENABLE BIT(0)
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#define PMC_LED_BREATHING_CTRL_COUNTER1_EN BIT(1)
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#define APBDEV_PMC_LED_BREATHING_SLOPE_STEPS 0xB4C
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#define APBDEV_PMC_LED_BREATHING_ON_COUNTER 0xB50
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#define APBDEV_PMC_LED_BREATHING_OFF_COUNTER1 0xB54
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#define APBDEV_PMC_LED_BREATHING_OFF_COUNTER0 0xB58
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#define PMC_LED_BREATHING_COUNTER_HZ 32768
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#define APBDEV_PMC_LED_BREATHING_STATUS 0xB5C
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#define PMC_LED_BREATHING_FSM_STATUS_MASK 0x7
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#define APBDEV_PMC_TZRAM_PWR_CNTRL 0xBE8
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#define PMC_TZRAM_PWR_CNTRL_SD BIT(0)
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#define APBDEV_PMC_TZRAM_SEC_DISABLE 0xBEC
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#define APBDEV_PMC_TZRAM_NON_SEC_DISABLE 0xBF0
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#define PMC_TZRAM_DISABLE_REG_WRITE BIT(0)
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#define PMC_TZRAM_DISABLE_REG_READ BIT(1)
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typedef enum _pmc_sec_lock_t
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{
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