When RAM is slow (no training), it's possible to have the stack failing to negotiate configuration successfully.
The race condition is caused by not flushing cache before sending a configuration packet reply.
Although, cache is write-through, this needs to happen.
- Default data alignment is now 1MB **when it's not set**
- Default volume alignment is now based on data alignment and not hardcoded to 16MB.
- Change max allowed alignment to 64MB.
The above changes allow selecting alignments for volume and data between 1MB and 64MB.
(From the previous 1 to 16MB for data and 16MB for volume).
This allows the custom sprintf to be recognized as printf by gcc and effectively doing format checking.
NOTE: 64bit formatting is not supported for now, even if gcc asks to be set.
- Allow to set CTS/RTS mode (only specific combos supported for now)
- Support the above modes in receiving
- Set 2 stop bits to decreases errors on high baudrates
This will now force a number as negative if bit31 is set and properly create the relevant string.
That means that external handling in order to show sign is now not needed.
Now that vblank writes are fixed we can return to proper backlight set.
Additionally, account for the pwm smoothing when backlight is turned off. That's to avoid visible green tint glitches when display is also turned off.
- Set display color profile to natural (it's still vivid but not overblown.)
- Enable PWM slope and set it to 6 frames in order to have smooth backlight transitions
Nintendo or Nvidia copied pasted the dynamic display code into static arrays in order to do the static hw init in bootloader and boot sysmodule.
Ofc that does double the work that is not needed at all, making it suboptimal.
Clean up every single config based on how tegra display interface hw works in order to save up space and make the process a bit faster.
