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https://github.com/CTCaer/hekate
synced 2024-12-22 03:11:16 +00:00
bdk: di: split normal and vblank dsi reads
And also make vblank reads more robust
This commit is contained in:
CTCaer
parent
8f540b2543
commit
0b8cdaf0ea
2 changed files with 125 additions and 52 deletions
172
bdk/display/di.c
172
bdk/display/di.c
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@ -57,34 +57,10 @@ static void _display_dsi_send_cmd(u8 cmd, u32 param, u32 wait)
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usleep(wait);
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}
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static void _display_dsi_read_rx_fifo(u32 *data)
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static void _display_dsi_wait_vblank(bool enable)
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{
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u32 fifo_count = DSI(_DSIREG(DSI_STATUS)) & DSI_STATUS_RX_FIFO_SIZE;
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for (u32 i = 0; i < fifo_count; i++)
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if (enable)
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{
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// Read or Drain RX FIFO.
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if (data)
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data[i] = DSI(_DSIREG(DSI_RD_DATA));
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else
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(void)DSI(_DSIREG(DSI_RD_DATA));
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}
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}
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int display_dsi_read(u8 cmd, u32 len, void *data, bool video_enabled)
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{
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int res = 0;
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u32 host_control = 0;
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u32 cmd_timeout = video_enabled ? 0 : 250000;
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u32 fifo[DSI_STATUS_RX_FIFO_SIZE] = {0};
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// Drain RX FIFO.
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_display_dsi_read_rx_fifo(NULL);
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// Save host control and enable host cmd packets during video.
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if (video_enabled)
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{
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host_control = DSI(_DSIREG(DSI_HOST_CONTROL));
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// Enable vblank interrupt.
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DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) = DC_CMD_INT_FRAME_END_INT;
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@ -96,18 +72,67 @@ int display_dsi_read(u8 cmd, u32 len, void *data, bool video_enabled)
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while (!(DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & DC_CMD_INT_FRAME_END_INT))
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;
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}
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else
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{
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// Wait for vblank before reseting sync points.
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DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT; // Clear interrupt.
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while (!(DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & DC_CMD_INT_FRAME_END_INT))
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;
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usleep(14);
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// Reset all states of syncpt block.
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DSI(_DSIREG(DSI_INCR_SYNCPT_CNTRL)) = DSI_INCR_SYNCPT_SOFT_RESET;
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usleep(300); // Stabilization delay.
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// Clear syncpt block reset.
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DSI(_DSIREG(DSI_INCR_SYNCPT_CNTRL)) = 0;
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usleep(300); // Stabilization delay.
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// Restore video mode and host control.
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0;
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// Disable and clear vblank interrupt.
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DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) = 0;
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DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT;
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}
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}
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static void _display_dsi_read_rx_fifo(u32 *data)
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{
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u32 fifo_count = DSI(_DSIREG(DSI_STATUS)) & DSI_STATUS_RX_FIFO_SIZE;
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if (fifo_count)
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DSI(_DSIREG(DSI_TRIGGER)) = 0;
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for (u32 i = 0; i < fifo_count; i++)
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{
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// Read or Drain RX FIFO.
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if (data)
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data[i] = DSI(_DSIREG(DSI_RD_DATA));
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else
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(void)DSI(_DSIREG(DSI_RD_DATA));
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}
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}
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int display_dsi_read(u8 cmd, u32 len, void *data)
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{
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int res = 0;
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u32 fifo[DSI_STATUS_RX_FIFO_SIZE] = {0};
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// Drain RX FIFO.
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_display_dsi_read_rx_fifo(NULL);
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// Set reply size.
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_display_dsi_send_cmd(MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
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_display_dsi_wait(cmd_timeout, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
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_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
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// Request register read.
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_display_dsi_send_cmd(MIPI_DSI_DCS_READ, cmd, 0);
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_display_dsi_wait(cmd_timeout, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
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_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
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// Transfer bus control to device for transmitting the reply.
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u32 high_speed = video_enabled ? DSI_HOST_CONTROL_HS : 0;
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DSI(_DSIREG(DSI_HOST_CONTROL)) = DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC | high_speed;
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DSI(_DSIREG(DSI_HOST_CONTROL)) |= DSI_HOST_CONTROL_IMM_BTA;
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// Wait for reply to complete. DSI_HOST_CONTROL_IMM_BTA bit acts as a DSI host read busy.
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_display_dsi_wait(150000, _DSIREG(DSI_HOST_CONTROL), DSI_HOST_CONTROL_IMM_BTA);
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// Wait a bit for the reply.
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@ -146,30 +171,77 @@ int display_dsi_read(u8 cmd, u32 len, void *data, bool video_enabled)
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else
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res = 1;
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// Disable host cmd packets during video and restore host control.
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if (video_enabled)
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return res;
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}
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int display_dsi_vblank_read(u8 cmd, u32 len, void *data)
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{
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int res = 0;
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u32 host_control = 0;
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u32 fifo[DSI_STATUS_RX_FIFO_SIZE] = {0};
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// Drain RX FIFO.
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_display_dsi_read_rx_fifo(NULL);
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// Save host control and enable host cmd packets during video.
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host_control = DSI(_DSIREG(DSI_HOST_CONTROL));
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_display_dsi_wait_vblank(true);
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// Set reply size.
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_display_dsi_send_cmd(MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
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_display_dsi_wait(0, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
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// Request register read.
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_display_dsi_send_cmd(MIPI_DSI_DCS_READ, cmd, 0);
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_display_dsi_wait(0, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
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_display_dsi_wait_vblank(false);
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// Transfer bus control to device for transmitting the reply.
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DSI(_DSIREG(DSI_HOST_CONTROL)) |= DSI_HOST_CONTROL_IMM_BTA;
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// Wait for reply to complete. DSI_HOST_CONTROL_IMM_BTA bit acts as a DSI host read busy.
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_display_dsi_wait(150000, _DSIREG(DSI_HOST_CONTROL), DSI_HOST_CONTROL_IMM_BTA);
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// Wait a bit for the reply.
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usleep(5000);
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// Read RX FIFO.
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_display_dsi_read_rx_fifo(fifo);
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// Parse packet and copy over the data.
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if ((fifo[0] & 0xFF) == DSI_ESCAPE_CMD)
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{
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// Wait for vblank before reseting sync points.
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DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT; // Clear interrupt.
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while (!(DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & DC_CMD_INT_FRAME_END_INT))
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;
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// Act based on reply type.
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switch (fifo[1] & 0xFF)
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{
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case GEN_LONG_RD_RES:
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case DCS_LONG_RD_RES:
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memcpy(data, &fifo[2], MIN((fifo[1] >> 8) & 0xFFFF, len));
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break;
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// Reset all states of syncpt block.
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DSI(_DSIREG(DSI_INCR_SYNCPT_CNTRL)) = DSI_INCR_SYNCPT_SOFT_RESET;
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usleep(300); // Stabilization delay.
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case GEN_1_BYTE_SHORT_RD_RES:
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case DCS_1_BYTE_SHORT_RD_RES:
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memcpy(data, &fifo[2], 1);
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break;
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// Clear syncpt block reset.
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DSI(_DSIREG(DSI_INCR_SYNCPT_CNTRL)) = 0;
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usleep(300); // Stabilization delay.
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case GEN_2_BYTE_SHORT_RD_RES:
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case DCS_2_BYTE_SHORT_RD_RES:
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memcpy(data, &fifo[2], 2);
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break;
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// Restore video mode and host control.
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0;
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DSI(_DSIREG(DSI_HOST_CONTROL)) = host_control;
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// Disable and clear vblank interrupt.
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DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) = 0;
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DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT;
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case ACK_ERROR_RES:
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default:
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res = 1;
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break;
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}
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}
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else
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res = 1;
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// Restore host control.
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DSI(_DSIREG(DSI_HOST_CONTROL)) = host_control;
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return res;
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}
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@ -425,7 +497,7 @@ void display_init()
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_display_id = 0xCCCCCC;
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for (u32 i = 0; i < 3; i++)
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{
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if (!display_dsi_read(MIPI_DCS_GET_DISPLAY_ID, 3, &_display_id, DSI_VIDEO_DISABLED))
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if (!display_dsi_read(MIPI_DCS_GET_DISPLAY_ID, 3, &_display_id))
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break;
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usleep(10000);
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2021 CTCaer
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* Copyright (c) 2018-2022 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -737,7 +737,8 @@ void display_init_cursor(void *crs_fb, u32 size);
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void display_set_pos_cursor(u32 x, u32 y);
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void display_deinit_cursor();
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int display_dsi_read(u8 cmd, u32 len, void *data);
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int display_dsi_vblank_read(u8 cmd, u32 len, void *data);
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void display_dsi_write(u8 cmd, u32 len, void *data, bool video_enabled);
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int display_dsi_read(u8 cmd, u32 len, void *data, bool video_enabled);
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#endif
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