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1679 commits 2 branches 75 tags 6.9 MiB
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142 commits

Author SHA1 Message Date
CTCaer
fe0bd89c4c bdk: pmc: extend pmc scratch locker 2022-10-11 14:41:42 +03:00
CTCaer
f534d5e316 bdk: i2c: fix send packet mode 2022-10-11 14:40:58 +03:00
CTCaer
2ea595e98d bdk: sdram: add new dram ids/configs 
On T210B01 dram ids 7 and 16 got removed.
29 to 34 were added.

Additionally, remove all deprecated and unused dram id enums.
 2022-10-11 10:38:43 +03:00
CTCaer
9d889e2c3e bdk: Add driver for VIC 
VIC is a HW engine that allows for frame/texture buffer manipulation.
 2022-10-11 06:41:38 +03:00
CTCaer
bfad719fcd bdk: small refactor 2022-10-11 06:16:38 +03:00
CTCaer
197ce4c76f bdk: sdmmc: timing changes 
- Correct HS102 naming to DDR100
- Fix clock for DDR50 (even if it's unused)
 2022-10-11 04:05:12 +03:00
CTCaer
d259d6f6d6 bdk: watchdog: clear timer interrupt also in handling 2022-07-11 22:10:41 +03:00
CTCaer
70523e404f bdk: whitespace refactor 2022-07-11 22:10:11 +03:00
CTCaer
57c8fd1f8c bdk: fiq: watchdog handling 
`BDK_WATCHDOG_FIQ_ENABLE` enables watchdog handling.
`BDK_RESTART_BL_ON_WDT` causes a reload of bootloader on FIQ

These 2 are useful when wanting to detect and handle hangs.
 2022-06-29 12:12:03 +03:00
CTCaer
b0c0a86108 bdk: migrate timers/sleeps to timer driver 2022-06-27 10:22:19 +03:00
CTCaer
061e10152f bdk: timer: add timer/watchdog driver 2022-06-27 10:20:25 +03:00
CTCaer
16af97c79a uart: rename print to printf 2022-06-25 05:42:42 +03:00
CTCaer
bdb8f6d352 ccplex: name some flow control values 2022-06-25 05:42:19 +03:00
CTCaer
e9587a325c bdk: fuse: add ipatch support for T210B01 2022-05-16 13:05:12 +03:00
CTCaer
87fe374b3b bdk: uart: use 2 STOP bits based on baudrate 2022-05-14 12:25:02 +03:00
CTCaer
b56e788d12 bdk: pinmux: more proper uart pinmuxing 2022-05-14 12:20:57 +03:00
CTCaer
9e613a7600 bdk: hwinit: simplify uart debug port paths 2022-05-13 03:56:59 +03:00
CTCaer
f452d916c9 bdk: clock: add ext peripheral clock control 2022-05-09 06:08:39 +03:00
CTCaer
12aac3a0fc bdk: clock: add 3 megabaud support for UART 2022-05-09 05:47:08 +03:00
CTCaer
f7bf4af3ec bdk: uart: refactor and add new functionality 
- Allow to set CTS/RTS mode (only specific combos supported for now)
- Support the above modes in receiving
- Set 2 stop bits to decreases errors on high baudrates
 2022-05-08 05:45:16 +03:00
CTCaer
81730c5f7e bdk: pinmux/pmc: add more defines 2022-05-08 05:22:41 +03:00
CTCaer
b9f40fed7a bdk: di: move plld setup code out of display obj 2022-05-08 04:41:05 +03:00
CTCaer
3f65a30b2e bdk: more atf prep 2022-02-15 00:14:53 +02:00
CTCaer
3fdb72ce37 bdk: i2c: correct order of spinlock wait 2022-01-29 01:34:01 +02:00
CTCaer
8327de8e2e bdk: replace NYX flag with proper flags 
- BDK_MINERVA_CFG_FROM_RAM: enables support for getting minerva configuration from nyx storage
- BDK_HW_EXTRA_DEINIT: enables extra deinit in hw_reinit_workaround
- BDK_SDMMC_OC_AND_EXTRA_PRINT: enables eMMC OC support (533 MB/s) and extra error printing
 2022-01-20 13:19:48 +02:00
CTCaer
39d411dc68 bdk: uart: add uart va print 2022-01-20 12:39:32 +02:00
CTCaer
10b479dc1c bdk: clock: add apb/ahb clock control 2022-01-20 12:32:57 +02:00
CTCaer
3dd12321f8 bdk: add activity monitor driver 2022-01-20 12:32:02 +02:00
CTCaer
853f10f774 bdk: pmc: update tzram defines 2022-01-20 12:13:35 +02:00
CTCaer
5e6a7c486b bdk: btn: enable HOME button as input 2022-01-16 01:05:42 +02:00
CTCaer
1a9c6bf983 bdk: correct reg init as per TRM 2022-01-16 01:04:52 +02:00
CTCaer
70504c295e bdk: various functionality independent changes 2022-01-16 01:03:24 +02:00
CTCaer
a5cd962f99 bdk: add global header 2022-01-15 23:58:27 +02:00
CTCaer
c801ef8dda bdk: use size defines where applicable 2021-10-01 15:03:18 +03:00
CTCaer
a1910156d8 bdk: hwinit: save boot reason for later usage 2021-10-01 14:32:42 +03:00
CTCaer
bcec028b0f clock: update device frequency getter function 
- Add missing write commits
- Remove hardcoded values
 2021-09-17 23:16:43 +03:00
CTCaer
8f9d52aa89 clock: move pllx enable to clock object 2021-09-17 23:13:53 +03:00
CTCaer
e9edcfeeb0 bdk: remove all references and defines to sept 2021-08-28 17:10:21 +03:00
CTCaer
70a06a6cae sdram: add support for missing new dram ids 
In preparation of dram chip shortages, add missing new ids that are now confirmed that they will be in mass usage
 2021-08-28 16:56:49 +03:00
CTCaer
7c72c9777a fuse/hwinit: move automatic SBK set into fuse 2021-08-28 16:46:15 +03:00
CTCaer
73df5e6743 fuse: add nx aula hw type 2021-08-28 16:44:16 +03:00
CTCaer
ce6926c36c fuse: remove fuse counting, bit count will be used instead 2021-06-08 05:53:31 +03:00
CTCaer
c29db97f73 hwinit/joycon: move uart clock deinits to joycon driver 2021-05-11 10:24:48 +03:00
CTCaer
d7ce2a81db bpmp: return previous fid when setting a new one 2021-05-11 09:21:12 +03:00
CTCaer
28008ac7ac hwinit: add seamless display (L4T Linux/Android) 
Initial support is for coreboot based preloading.
 2021-04-11 09:18:55 +03:00
CTCaer
513f77a2ad uart: use proper interrupt decoding 2021-03-17 08:51:49 +02:00
CTCaer
a7bf8bf118 se: Refactor with proper names 
Additionally fix some bugs in rsa access control
 2021-02-06 02:55:58 +02:00
CTCaer
8fc5267110 tmp451: Show correct temperature for T210B01 
The thermal measurement substrate transistor was changed in Mariko SoCs.
This ensures that it's properly offset by -12.5 °C.
 2021-01-14 17:58:23 +02:00
CTCaer
c6c396ce2a reg5V: Manage battery source based on charger status 2021-01-11 21:30:59 +02:00
CTCaer
1f37b96359 coreboot mitigation: Reinstate SD controller power 2021-01-04 19:03:50 +02:00
CTCaer
83ab79c51e fuse: Return the proper dram id when raw is requested 2021-01-04 02:41:55 +02:00
CTCaer
745ac609d2 max7762x: Update everything to use the improved pmic management 2021-01-04 02:41:15 +02:00
CTCaer
60b629e57f Move display related objects to display parrent 2020-12-28 05:19:23 +02:00
CTCaer
11ca6caf5f clock: Add more defines and simplify some logic 2020-12-26 17:28:08 +02:00
CTCaer
15afdf53e4 clock: Add module actual frequency getter 2020-12-26 17:25:23 +02:00
CTCaer
d15f958b48 irq: Disable irq if not handled. 2020-12-26 17:22:56 +02:00
CTCaer
5fd3bdede7 pmc: Add defines for power rails 2020-12-26 17:20:26 +02:00
CTCaer
e2dd218f33 pmc: Add latest pmc secure scratch lock 2020-12-26 16:48:00 +02:00
CTCaer
2628044ba8 fuse: Move more parsing into its specific object 2020-12-26 16:34:12 +02:00
CTCaer
b6ec217484 exo: Support uart logging 
This can be enabled via compile time flags or exosphere.ini.
Compile time flags override exosphere.ini
 2020-12-11 18:14:00 +02:00
CTCaer
5b8fb9fb6b Various refactoring and addition of comments 2020-12-11 17:25:59 +02:00
CTCaer
8249d9e1a2 se: Ensure aligned key/iv/ctr/hash copy 2020-12-05 20:39:17 +02:00
CTCaer
c13eabcde8 sdmmc: Add T210B01 support 
The driver was working before this, but adding the changes provides a proper and better sdmmc controller inner state.
 2020-12-02 02:07:15 +02:00
CTCaer
a1188505e8 usb: Add XUSB support mainly for T210B01 2020-12-02 01:13:52 +02:00
CTCaer
5ffbbf40a5 hos: Add Mariko keygen 2020-07-04 21:13:25 +03:00
CTCaer
a36fec5696 clock: Lock clock to always enabled for SE in T210B01 2020-07-04 21:07:25 +03:00
CTCaer
8d2230dc51 fuse: Correct fuse array size for T210B01 2020-07-04 21:04:20 +03:00
CTCaer
ccaf49bece display: Add T210B01 support 2020-06-26 22:29:52 +03:00
CTCaer
147fed39c8 ccplex: Add regulator for T210B01 2020-06-26 19:02:37 +03:00
CTCaer
293c47774d fuse: Add NX hw type getter 2020-06-26 18:45:21 +03:00
CTCaer
795ed8aadc hwinit: Add T210B01 support 2020-06-26 18:42:31 +03:00
CTCaer
cabaa6cfb8 Utilize BIT macro everywhere 2020-11-26 01:41:45 +02:00
CTCaer
ab7a81081c t210: Refactor AHB Gizmo registers 2020-11-15 14:46:42 +02:00
CTCaer
0b314d7f21 clock: Move UTMIPLL init from USB to clock 2020-11-15 14:43:36 +02:00
CTCaer
8305058cf5 clock: Move PLLU init/deinit from USB to clock 2020-11-15 14:42:01 +02:00
CTCaer
669e42960c Utilize ARRAY_SIZE macro 2020-11-15 13:56:45 +02:00
CTCaer
68d57861cd Add missing guard from some macros 
Guard them for future usage, as none of these macros had a non-preset variable used with them yet.
 2020-11-15 13:39:27 +02:00
CTCaer
ce156ab4e7 hos: Automate some eks and bis checks 2020-10-20 11:53:28 +03:00
CTCaer
cb471162d2 i2c: Fix packet mode 2020-10-20 10:37:33 +03:00
CTCaer
6714cae498 i2c: Add packet mode support (32 bytes) 2020-08-27 10:04:52 +03:00
CTCaer
b20a0e74c2 i2c: Refactor 2020-08-27 10:04:26 +03:00
CTCaer
98555b24f8 l4t: Clear boot mode if user canceled autoboot 2020-08-15 13:12:41 +03:00
CTCaer
af0cd34f92 l4t: Add panic dump (PSTORE) 2020-07-19 20:32:22 +03:00
CTCaer
fac1884a43 i2c: Reduce timeout to proper levels (100ms) 2020-07-18 02:33:46 +03:00
CTCaer
adfa7c0780 fuse: Use fuse count function for burnt fuses 2020-07-18 01:15:28 +03:00
CTCaer
45ca2938f5 pmc: Move rail power function to its own object 2020-07-18 00:42:53 +03:00
CTCaer
32e58d2bb3 hw init: Cosmetic refactoring 2020-07-17 18:08:27 +03:00
CTCaer
638a3909c5 Refactor various variables and names 2020-07-17 18:00:32 +03:00
CTCaer
e158d9bc00 clk: Refactor CLK devices bits 2020-07-17 16:50:17 +03:00
CTCaer
2aa9055fae Various fixes 2020-06-15 14:58:50 +03:00
CTCaer
6e256d29c7 Utilize hekate's BDK for hekate main and Nyx 2020-06-14 16:45:45 +03:00
CTCaer
185526d134 Introducing Bootloader Development Kit (BDK) 
BDK will allow developers to use the full collection of drivers,
with limited editing, if any, for making payloads for Nintendo Switch.

Using a single source for everything will also help decoupling
Switch specific code and easily port it to other Tegra X1/X1+ platforms.
And maybe even to lower targets.

Everything is now centrilized into bdk folder.
Every module or project can utilize it by simply including it.

This is just the start and it will continue to improve.
 2020-06-14 15:25:21 +03:00