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Author SHA1 Message Date
CTCaer 6061bb5213 nyx: info: add public key info 
And remove LOT Code 1 since it's not used.
 2023-07-28 03:38:40 +03:00
CTCaer 221614212a nyx: info: add more cal0 info 
Touch vendor, IMU type/mount and analog stick types.
 2023-07-28 03:36:10 +03:00
CTCaer 5b94e8cf8a nyx: info: use fuel gauge reg dump function 2023-07-28 03:35:08 +03:00
CTCaer f291a5cfa7 bdk: max17050: add reg dumping 2023-07-28 03:34:11 +03:00
CTCaer 7e397b3403 nyx: options: change autorcm icon 2023-07-28 03:33:09 +03:00
CTCaer f35c5b0596 nyx: fix first time config save unmounting 
SD card should not get unmounted on the first boot without hekate_ipl.ini.
Move sd card mounting management outside of it.
 2023-07-28 03:32:33 +03:00
CTCaer b142ca0f33 nyx: info: use new fuse names 2023-07-28 03:29:24 +03:00
CTCaer 21da947c02 nyx: hos: deduplicate cal0 dumping 2023-07-28 03:28:21 +03:00
CTCaer 317abb2f4e hekate: add bootwait for each entry 
Allow overriding global bootwait with the one from boot entry.
 2023-07-28 03:23:03 +03:00
CTCaer d3567736c8 hos: allow overriding uCID 2023-07-28 03:06:20 +03:00
CTCaer 9187fa7a8c bdk: fuse: add all t210b01 fuses 
And use B01 to distinguish the ones only on that SoC.
 2023-07-22 07:10:12 +03:00
CTCaer b9bc35a22e bdk: dram: correct old comments 2023-07-21 18:39:46 +03:00
CTCaer 6e954f5cdf nyx: provide the raw calib for Lite gamepad 
Let L4T driver manage it.
 2023-06-11 13:29:04 +03:00
CTCaer d7ad9b874b bdk: use the typedefs on jc calib 2023-06-11 13:27:48 +03:00
CTCaer 820e6d5a6e bdk: update cal0 struct 2023-06-10 23:48:45 +03:00
CTCaer 0215d16405 Bump hekate to v6.0.4 and Nyx to v1.5.4 2023-06-09 11:08:13 +03:00
CTCaer c0c0e34ef0 nyx: info: update dram info 2023-06-09 11:04:31 +03:00
CTCaer 581ac8ec33 nyx: info: always report errors for eMMC 
Even if init fails.
 2023-06-09 11:04:07 +03:00
CTCaer 26bf148188 nyx: add Lite gamepad calibration data dumping 
Adds calibration data dumping via the Joycon BT pairing dumping function.

Calibration for everything about Sio is dumped. So Sticks and IMU.
 2023-06-09 11:03:29 +03:00
CTCaer dc8f6beb8d nyx: info: make cal0 dumping public 2023-06-09 11:01:08 +03:00
CTCaer 25b181bf36 nyx: add missing newlines 
Change line since the text does not fit like that in these places, effectively breaking text color.
 2023-06-09 10:59:03 +03:00
CTCaer 66e5e128f6 l4t: adjust revision amidst the new changes 
Also add helpful message if files are missing.
 2023-06-09 10:56:39 +03:00
CTCaer 84822726cb l4t: add fine tuned voltage support for DRAM 
1000-1175mV for T210 VDDIO/Q via `ram_oc_vdd2`
1000-1175mV for T210B01 VDDIO and 600-650mV for VDDQ via `ram_oc_vdd2` and `ram_oc_vddq`.
 2023-06-09 10:55:32 +03:00
CTCaer b6e1e0d412 l4t: add bpmp-fw support for T210 2023-06-09 10:53:03 +03:00
CTCaer 496737248c l4t: there was never a need to normalize dram freq 2023-06-09 10:51:31 +03:00
CTCaer 4f52e1f24a l4t: refactor bpmp-fw defines for T210B01 2023-06-09 10:50:29 +03:00
CTCaer 3f9c7a7da6 hos: prep boot freq in minerva for cfw also 2023-06-09 10:41:53 +03:00
CTCaer 93ed4d0899 bdk: emc: add temp and feature reporting defines 2023-06-09 10:38:24 +03:00
CTCaer 01afd2de56 bdk: sdmmc: properly report comp pad status 
The reporting of the resistor being shorted or open was swapped. Fix that so it's immediately known what's the issue.
 2023-06-09 10:37:47 +03:00
CTCaer d621d96af1 bdk: sdmmc: refactor comments 2023-06-09 10:36:29 +03:00
CTCaer b674624ad0 bdk: timer: add instruction sleep 
usage:
`isleep(ILOOP(instructions))`

Each loop is 3 cycles, or approximately 7.35ns on 408MHz CPU clock.
 2023-06-09 10:33:11 +03:00
CTCaer 191a0533d9 bdk: clock: add more known pto ids 2023-06-09 10:29:47 +03:00
CTCaer 8502731fbd bdk: tsec: refactor some register names 2023-06-09 10:28:28 +03:00
CTCaer 18f3a1b70c bdk: max77620: reduce max DRAM VDDIO/Q 
Reduce allowed VDDIO/VDDQfor T210B01 and VDDIO for T210B01.
 2023-06-09 10:24:55 +03:00
CTCaer 418f029d11 lib: minerva: add 1966 and 2033 MHz in div table 2023-06-08 05:31:15 +03:00
CTCaer 066efda4cd lib: minerva: normalize output frequency 
Allow frequencies that are not exact to receive proper dividers from the supported ones from table.
 2023-06-08 04:56:14 +03:00
CTCaer d8d15bde44 lib: minerva: add Samsung 8GB support 
And remove frequencies smaller than deep sleep frequency from the tables.
 2023-06-08 04:50:59 +03:00
CTCaer 9d8ebc7e38 lib: minerva: refactor table 
Remove _idx used initially for RE at last.
 2023-06-08 04:49:16 +03:00
CTCaer c2ee6be2f5 bdk: sdram: add Samsung 8GB RAM support for T210 
And remove Copper support completely.
 2023-06-08 04:16:51 +03:00
CTCaer 73a133556d bdk: sdram: correct sku related info 
Validated so rename accordingly.
 2023-06-08 02:57:30 +03:00
CTCaer 7d3663616e bdk: sdram: name 2 of the new ram chips 
Not actually validated, but educated guess, since all previous one were correct in the end.
New Micron still unknown, can be guessed but model doesn't exist in any public list.
 2023-06-08 02:52:03 +03:00
CTCaer e76aebabba bdk: mem: minerva: check table size in clock check 
Don't hardcode table size to 10.
 2023-06-08 02:45:34 +03:00
CTCaer bc0eea11f3 bdk: joycon: add calibration struct 2023-06-08 02:44:35 +03:00
CTCaer 937ab52d14 Bump hekate to v6.0.4 2023-05-09 11:15:34 +03:00
CTCaer e896d388ab hos: 16.0.3 support 2023-05-09 11:15:11 +03:00
CTCaer ded959c449 Bump hekate to v6.0.3 and Nyx to v1.5.3 2023-04-06 17:38:36 +03:00
CTCaer a7fd83c793 nyx: correct build flag 2023-04-06 17:36:22 +03:00
CTCaer dd380d4d47 l4t: increase bw priority to SDMMC1 for L4T 2023-04-06 17:34:26 +03:00
CTCaer 795b4ad26e bdk: sdmmc: increase bw priority to SDMMC1 for L4T 2023-04-06 17:30:01 +03:00
CTCaer bb10b8aea3 bdk: sdmmc: small refactor 2023-04-06 10:19:53 +03:00