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https://github.com/CTCaer/hekate
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l4t: refactor bpmp-fw defines for T210B01
This commit is contained in:
CTCaer
parent
3f9c7a7da6
commit
4f52e1f24a
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@ -79,50 +79,50 @@
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#define MTCTABLE_BASE (SECFW_BASE + SZ_512K) // 512KB after SECFW_BASE.
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// Secure Elements addresses for T210B01.
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#define BPMPFW_BASE (SECFW_BASE) // !! DTS carveout-start must match !!
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#define BPMPFW_ENTRYPOINT (BPMPFW_BASE + 0x40) // Used internally also.
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#define BPMPFW_HEAP_BASE (BPMPFW_BASE + SZ_256K - SZ_1K) // 255KB after BPMPFW_BASE.
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#define BPMPFW_EDTB_BASE (BPMPFW_BASE + SZ_1M - 0) // Top BPMPFW carveout minus EMC DTB size.
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#define BPMPFW_ADTB_BASE (BPMPFW_BASE + 0x26008) // Attached BPMP-FW DTB address.
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#define SC7EXIT_B01_BASE (BPMPFW_HEAP_BASE - SZ_4K) // 4KB before BPMP heap.
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#define BPMPFW_B01_BASE (SECFW_BASE) // !! DTS carveout-start must match !!
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#define BPMPFW_B01_ENTRYPOINT (BPMPFW_B01_BASE + 0x40) // Used internally also.
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#define BPMPFW_B01_HEAP_BASE (BPMPFW_B01_BASE + SZ_256K - SZ_1K) // 255KB after BPMPFW_B01_BASE.
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#define BPMPFW_B01_EDTB_BASE (BPMPFW_B01_BASE + SZ_1M - 0) // Top BPMPFW carveout minus EMC DTB size.
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#define BPMPFW_B01_ADTB_BASE (BPMPFW_B01_BASE + 0x26008) // Attached BPMP-FW DTB address.
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#define SC7EXIT_B01_BASE (BPMPFW_B01_HEAP_BASE - SZ_4K) // 4KB before BPMP heap.
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// BPMP-FW defines. Offsets are 0xD8 below real main binary.
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#define BPMPFW_DTB_ADDR (BPMPFW_BASE + 0x14) // u32. DTB address if not attached.
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#define BPMPFW_CC_INIT_OP (BPMPFW_BASE + 0x17324) // u8. Initial table training OP. 0: OP_SWITCH, 1: OP_TRAIN, 2: OP_TRAIN_SWITCH. Default: OP_TRAIN.
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#define BPMPFW_LOGLEVEL (BPMPFW_BASE + 0x2547C) // u32. Log level. Default 3.
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#define BPMPFW_LOGLEVEL (BPMPFW_BASE + 0x2547C) // u32. Log level. Default 3.
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#define BPMPFW_CC_PT_TIME (BPMPFW_BASE + 0x25644) // u32. Periodic training period (in ms). Default 100 ms.
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#define BPMPFW_CC_DEBUG (BPMPFW_BASE + 0x257F8) // u32. EMC Clock Change debug mask. Default: 0x50000101.
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#define BPMPFW_B01_DTB_ADDR (BPMPFW_B01_BASE + 0x14) // u32. DTB address if not attached.
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#define BPMPFW_B01_CC_INIT_OP (BPMPFW_B01_BASE + 0x17324) // u8. Initial table training OP. 0: OP_SWITCH, 1: OP_TRAIN, 2: OP_TRAIN_SWITCH. Default: OP_TRAIN.
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#define BPMPFW_B01_LOGLEVEL (BPMPFW_B01_BASE + 0x2547C) // u32. Log level. Default 3.
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#define BPMPFW_B01_LOGLEVEL (BPMPFW_B01_BASE + 0x2547C) // u32. Log level. Default 3.
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#define BPMPFW_B01_CC_PT_TIME (BPMPFW_B01_BASE + 0x25644) // u32. Periodic training period (in ms). Default 100 ms.
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#define BPMPFW_B01_CC_DEBUG (BPMPFW_B01_BASE + 0x257F8) // u32. EMC Clock Change debug mask. Default: 0x50000101.
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// BPMP-FW attached DTB defines. Can be generalized.
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#define BPMPFW_DTB_EMC_ENTRIES 4
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#define BPMPFW_DTB_SERIAL_PORT_VAL (BPMPFW_ADTB_BASE + 0x5B) // u8. DTB UART port offset. 0: Disabled.
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#define BPMPFW_DTB_SET_SERIAL_PORT(port) (*(u8 *)BPMPFW_DTB_SERIAL_PORT_VAL = port)
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#define BPMPFW_DTB_EMC_TBL_OFF (BPMPFW_ADTB_BASE + 0xA0)
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#define BPMPFW_DTB_EMC_TBL_SZ 0x1120
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#define BPMPFW_DTB_EMC_NAME_VAL 0xA
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#define BPMPFW_DTB_EMC_ENABLE_OFF 0x20
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#define BPMPFW_DTB_EMC_VALUES_OFF 0x4C
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#define BPMPFW_DTB_EMC_FREQ_VAL 0x8C
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#define BPMPFW_DTB_EMC_SCC_OFF 0x108C
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#define BPMPFW_DTB_EMC_PLLM_DIVM_VAL 0x10A4
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#define BPMPFW_DTB_EMC_PLLM_DIVN_VAL 0x10A8
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#define BPMPFW_DTB_EMC_PLLM_DIVP_VAL 0x10AC
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#define BPMPFW_DTB_EMC_TBL_START(idx) (BPMPFW_DTB_EMC_TBL_OFF + BPMPFW_DTB_EMC_TBL_SZ * (idx))
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#define BPMPFW_DTB_EMC_TBL_SET_VAL(idx, off, val) (*(u32 *)(BPMPFW_DTB_EMC_TBL_START(idx) + (off)) = (val))
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#define BPMPFW_DTB_EMC_TBL_SET_FREQ(idx, freq) (*(u32 *)(BPMPFW_DTB_EMC_TBL_START(idx) + BPMPFW_DTB_EMC_FREQ_VAL) = (freq))
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#define BPMPFW_DTB_EMC_TBL_SCC_OFFSET(idx) ((void *)(BPMPFW_DTB_EMC_TBL_START(idx) + BPMPFW_DTB_EMC_SCC_OFF))
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#define BPMPFW_DTB_EMC_TBL_SET_PLLM_DIVN(idx, n) (*(u32 *)(BPMPFW_DTB_EMC_TBL_START(idx) + BPMPFW_DTB_EMC_PLLM_DIVN_VAL) = (n))
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#define BPMPFW_DTB_EMC_TBL_SET_NAME(idx, name) (strcpy((char *)(BPMPFW_DTB_EMC_TBL_START(idx) + BPMPFW_DTB_EMC_NAME_VAL), (name)))
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#define BPMPFW_DTB_EMC_TBL_ENABLE(idx) (*(char *)(BPMPFW_DTB_EMC_TBL_START(idx) + BPMPFW_DTB_EMC_ENABLE_OFF) = 'n')
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#define BPMPFW_DTB_EMC_TBL_OFFSET(idx) ((void *)(BPMPFW_DTB_EMC_TBL_START(idx) + BPMPFW_DTB_EMC_VALUES_OFF))
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#define BPMPFW_B01_DTB_EMC_ENTRIES 4
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#define BPMPFW_B01_DTB_SERIAL_PORT_VAL (BPMPFW_B01_ADTB_BASE + 0x5B) // u8. DTB UART port offset. 0: Disabled.
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#define BPMPFW_B01_DTB_SET_SERIAL_PORT(port) (*(u8 *)BPMPFW_B01_DTB_SERIAL_PORT_VAL = port)
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#define BPMPFW_B01_DTB_EMC_TBL_OFF (BPMPFW_B01_ADTB_BASE + 0xA0)
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#define BPMPFW_B01_DTB_EMC_TBL_SZ 0x1120
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#define BPMPFW_B01_DTB_EMC_NAME_VAL 0xA
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#define BPMPFW_B01_DTB_EMC_ENABLE_OFF 0x20
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#define BPMPFW_B01_DTB_EMC_VALUES_OFF 0x4C
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#define BPMPFW_B01_DTB_EMC_FREQ_VAL 0x8C
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#define BPMPFW_B01_DTB_EMC_SCC_OFF 0x108C
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#define BPMPFW_B01_DTB_EMC_PLLM_DIVM_VAL 0x10A4
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#define BPMPFW_B01_DTB_EMC_PLLM_DIVN_VAL 0x10A8
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#define BPMPFW_B01_DTB_EMC_PLLM_DIVP_VAL 0x10AC
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#define BPMPFW_B01_DTB_EMC_TBL_START(idx) (BPMPFW_B01_DTB_EMC_TBL_OFF + BPMPFW_B01_DTB_EMC_TBL_SZ * (idx))
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#define BPMPFW_B01_DTB_EMC_TBL_SET_VAL(idx, off, val) (*(u32 *)(BPMPFW_B01_DTB_EMC_TBL_START(idx) + (off)) = (val))
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#define BPMPFW_B01_DTB_EMC_TBL_SET_FREQ(idx, freq) (*(u32 *)(BPMPFW_B01_DTB_EMC_TBL_START(idx) + BPMPFW_B01_DTB_EMC_FREQ_VAL) = (freq))
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#define BPMPFW_B01_DTB_EMC_TBL_SCC_OFFSET(idx) ((void *)(BPMPFW_B01_DTB_EMC_TBL_START(idx) + BPMPFW_B01_DTB_EMC_SCC_OFF))
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#define BPMPFW_B01_DTB_EMC_TBL_SET_PLLM_DIVN(idx, n) (*(u32 *)(BPMPFW_B01_DTB_EMC_TBL_START(idx) + BPMPFW_B01_DTB_EMC_PLLM_DIVN_VAL) = (n))
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#define BPMPFW_B01_DTB_EMC_TBL_SET_NAME(idx, name) (strcpy((char *)(BPMPFW_B01_DTB_EMC_TBL_START(idx) + BPMPFW_B01_DTB_EMC_NAME_VAL), (name)))
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#define BPMPFW_B01_DTB_EMC_TBL_ENABLE(idx) (*(char *)(BPMPFW_B01_DTB_EMC_TBL_START(idx) + BPMPFW_B01_DTB_EMC_ENABLE_OFF) = 'n')
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#define BPMPFW_B01_DTB_EMC_TBL_OFFSET(idx) ((void *)(BPMPFW_B01_DTB_EMC_TBL_START(idx) + BPMPFW_B01_DTB_EMC_VALUES_OFF))
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// MTC table defines for T210B01.
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#define BPMPFW_MTC_TABLE_BASE 0xA0000000
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#define BPMPFW_MTC_FREQ_TABLE_SIZE 4300
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#define BPMPFW_MTC_TABLE_SIZE (BPMPFW_MTC_FREQ_TABLE_SIZE * 3)
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#define BPMPFW_MTC_TABLE(idx) (BPMPFW_MTC_TABLE_BASE + BPMPFW_MTC_TABLE_SIZE * (idx))
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#define BPMPFW_MTC_TABLE_OFFSET(idx, fidx) ((void *)(BPMPFW_MTC_TABLE(idx) + BPMPFW_MTC_FREQ_TABLE_SIZE * (fidx)))
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#define BPMPFW_B01_MTC_TABLE_BASE 0xA0000000
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#define BPMPFW_B01_MTC_FREQ_TABLE_SIZE 4300
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#define BPMPFW_B01_MTC_TABLE_SIZE (BPMPFW_B01_MTC_FREQ_TABLE_SIZE * 3)
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#define BPMPFW_B01_MTC_TABLE(idx) (BPMPFW_B01_MTC_TABLE_BASE + BPMPFW_B01_MTC_TABLE_SIZE * (idx))
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#define BPMPFW_B01_MTC_TABLE_OFFSET(idx, fidx) ((void *)(BPMPFW_B01_MTC_TABLE(idx) + BPMPFW_B01_MTC_FREQ_TABLE_SIZE * (fidx)))
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// BL31 Enable IRAM based config.
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#define BL31_IRAM_PARAMS 0x4D415249 // "IRAM".
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@ -281,7 +281,7 @@ typedef struct _l4t_ctxt_t
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#define DRAM_T210_OC_VOLTAGE 1187500
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#define DRAM_T210_OC_THRESHOLD_FREQ 1862400
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#define DRAM_TBL_PROVIDED_MAX_FREQ 1600000
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#define DRAM_T210B01_TBL_MAX_FREQ 1600000
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// JEDEC frequency table.
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static const u32 ram_jd_t210b01[] = {
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@ -303,23 +303,23 @@ static const u8 mtc_table_idx_t210b01[] = {
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};
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static const l4t_fw_t l4t_fw[] = {
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{ TZDRAM_BASE, "bl31.bin" },
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{ BL33_LOAD_BASE, "bl33.bin" },
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{ SC7ENTRY_BASE, "sc7entry.bin" },
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{ SC7EXIT_BASE, "sc7exit.bin" },
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{ SC7EXIT_B01_BASE, "sc7exit_b01.bin" },
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{ BPMPFW_BASE, "bpmpfw_b01.bin" },
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{ BPMPFW_MTC_TABLE_BASE, "mtc_tbl_b01.bin" },
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{ TZDRAM_BASE, "bl31.bin" },
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{ BL33_LOAD_BASE, "bl33.bin" },
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{ SC7ENTRY_BASE, "sc7entry.bin" },
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{ SC7EXIT_BASE, "sc7exit.bin" },
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{ SC7EXIT_B01_BASE, "sc7exit_b01.bin" },
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{ BPMPFW_B01_BASE, "bpmpfw_b01.bin" },
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{ BPMPFW_B01_MTC_TABLE_BASE, "mtc_tbl_b01.bin" },
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};
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enum {
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BL31_FW = 0,
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BL33_FW = 1,
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SC7ENTRY_FW = 2,
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SC7EXIT_FW = 3,
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SC7EXIT_B01_FW = 4,
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BPMPFW_FW = 5,
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BPMPFW_MTC_TBL = 6
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BL31_FW = 0,
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BL33_FW = 1,
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SC7ENTRY_FW = 2,
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SC7EXIT_FW = 3,
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SC7EXIT_B01_FW = 4,
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BPMPFW_B01_FW = 5,
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BPMPFW_B01_MTC_TBL = 6
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};
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static void _l4t_crit_error(const char *text)
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@ -771,39 +771,39 @@ static void _l4t_late_hw_config(bool t210b01)
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#endif
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}
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static void _l4t_bpmpfw_config(l4t_ctxt_t *ctxt)
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static void _l4t_bpmpfw_b01_config(l4t_ctxt_t *ctxt)
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{
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char *ram_oc_txt = ctxt->ram_oc_txt;
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u32 ram_oc_freq = ctxt->ram_oc_freq;
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u32 ram_oc_divn = 0;
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// Set default parameters.
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*(u32 *)BPMPFW_DTB_ADDR = 0;
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*(u8 *)BPMPFW_CC_INIT_OP = OP_TRAIN;
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*(u32 *)BPMPFW_CC_PT_TIME = 100;
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*(u32 *)BPMPFW_B01_DTB_ADDR = 0;
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*(u8 *)BPMPFW_B01_CC_INIT_OP = OP_TRAIN;
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*(u32 *)BPMPFW_B01_CC_PT_TIME = 100;
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#if DEBUG_LOG_BPMPFW
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// Set default debug parameters.
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*(u32 *)BPMPFW_LOGLEVEL = 3;
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*(u32 *)BPMPFW_CC_DEBUG = 0x50000101;
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*(u32 *)BPMPFW_B01_LOGLEVEL = 3;
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*(u32 *)BPMPFW_B01_CC_DEBUG = 0x50000101;
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// Set serial debug port.
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if (*(u32 *)BPMPFW_ADTB_BASE == DTB_MAGIC)
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BPMPFW_DTB_SET_SERIAL_PORT(ctxt->serial_port);
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if (*(u32 *)BPMPFW_B01_ADTB_BASE == DTB_MAGIC)
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BPMPFW_B01_DTB_SET_SERIAL_PORT(ctxt->serial_port);
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#endif
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// Set and copy MTC tables.
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u32 mtc_idx = mtc_table_idx_t210b01[fuse_read_dramid(true)];
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for (u32 i = 0; i < 3; i++)
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{
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minerva_sdmmc_la_program(BPMPFW_MTC_TABLE_OFFSET(mtc_idx, i), true);
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memcpy(BPMPFW_DTB_EMC_TBL_OFFSET(i), BPMPFW_MTC_TABLE_OFFSET(mtc_idx, i), BPMPFW_MTC_FREQ_TABLE_SIZE);
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minerva_sdmmc_la_program(BPMPFW_B01_MTC_TABLE_OFFSET(mtc_idx, i), true);
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memcpy(BPMPFW_B01_DTB_EMC_TBL_OFFSET(i), BPMPFW_B01_MTC_TABLE_OFFSET(mtc_idx, i), BPMPFW_B01_MTC_FREQ_TABLE_SIZE);
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}
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if (ram_oc_freq > DRAM_TBL_PROVIDED_MAX_FREQ)
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if (ram_oc_freq > DRAM_T210B01_TBL_MAX_FREQ)
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{
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// Final table.
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const u32 tbl_idx = BPMPFW_DTB_EMC_ENTRIES - 1;
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const u32 tbl_idx = BPMPFW_B01_DTB_EMC_ENTRIES - 1;
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// Set Overclock.
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for (u32 i = 0; i < ARRAY_SIZE(ram_jd_t210b01); i++)
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@ -827,12 +827,12 @@ static void _l4t_bpmpfw_config(l4t_ctxt_t *ctxt)
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}
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// Copy table and set parameters.
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memcpy(BPMPFW_DTB_EMC_TBL_OFFSET(tbl_idx), BPMPFW_MTC_TABLE_OFFSET(mtc_idx, 2), BPMPFW_MTC_FREQ_TABLE_SIZE);
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memcpy(BPMPFW_B01_DTB_EMC_TBL_OFFSET(tbl_idx), BPMPFW_B01_MTC_TABLE_OFFSET(mtc_idx, 2), BPMPFW_B01_MTC_FREQ_TABLE_SIZE);
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BPMPFW_DTB_EMC_TBL_SET_NAME(tbl_idx, ram_oc_txt);
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BPMPFW_DTB_EMC_TBL_SET_FREQ(tbl_idx, ram_oc_freq);
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BPMPFW_B01_DTB_EMC_TBL_SET_NAME(tbl_idx, ram_oc_txt);
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BPMPFW_B01_DTB_EMC_TBL_SET_FREQ(tbl_idx, ram_oc_freq);
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pll_spread_spectrum_t210b01_t *ssc = BPMPFW_DTB_EMC_TBL_SCC_OFFSET(tbl_idx);
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pll_spread_spectrum_t210b01_t *ssc = BPMPFW_B01_DTB_EMC_TBL_SCC_OFFSET(tbl_idx);
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if (ram_oc_divn <= DRAM_T210B01_SSC_PARAMS)
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{
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@ -852,13 +852,13 @@ static void _l4t_bpmpfw_config(l4t_ctxt_t *ctxt)
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}
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// Enable table.
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BPMPFW_DTB_EMC_TBL_ENABLE(tbl_idx);
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BPMPFW_B01_DTB_EMC_TBL_ENABLE(tbl_idx);
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UPRINTF("RAM Frequency set to: %d KHz. Voltage: %d mV\n", ram_oc_freq, ram_oc_volt);
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}
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// Save BPMP-FW entrypoint for TZ.
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PMC(APBDEV_PMC_SCRATCH39) = BPMPFW_ENTRYPOINT;
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PMC(APBDEV_PMC_SCRATCH39) = BPMPFW_B01_ENTRYPOINT;
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PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE1) |= BIT(15);
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}
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@ -1191,7 +1191,7 @@ void launch_l4t(const ini_sec_t *ini_sec, int entry_idx, int is_list, bool t210b
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// Set BPMP-FW parameters.
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if (t210b01)
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_l4t_bpmpfw_config(&ctxt);
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_l4t_bpmpfw_b01_config(&ctxt);
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// Set carveouts and save them to PMC for SC7 Exit.
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_l4t_mc_config_carveout(t210b01);
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@ -1213,8 +1213,8 @@ void launch_l4t(const ini_sec_t *ini_sec, int entry_idx, int is_list, bool t210b
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if (t210b01)
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{
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// Prep reset vector for SC7 save state and start BPMP-FW.
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EXCP_VEC(EVP_COP_RESET_VECTOR) = BPMPFW_ENTRYPOINT;
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void (*bpmp_fw_ptr)() = (void *)BPMPFW_ENTRYPOINT;
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EXCP_VEC(EVP_COP_RESET_VECTOR) = BPMPFW_B01_ENTRYPOINT;
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void (*bpmp_fw_ptr)() = (void *)BPMPFW_B01_ENTRYPOINT;
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(*bpmp_fw_ptr)();
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}
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