Commit graph

46 commits

Author SHA1 Message Date
CTCaer
f126486266 bdk: sdmmc: utilize block size defines 2024-03-12 15:47:14 +02:00
CTCaer
41d3565353 bdk: sdmmc: deduplicate function modes get
And parse the whole info
2023-12-27 15:01:20 +02:00
CTCaer
d621d96af1 bdk: sdmmc: refactor comments 2023-06-09 10:36:29 +03:00
CTCaer
811fa4c88b bdk: sdmmc: add SD registers debug printing
Can be enabled with `SDMMC_DEBUG_PRINT_SD_REGS`
2023-04-06 10:13:35 +03:00
CTCaer
f4bf48e76a bdk: sdmmc: add driver type set support 2023-03-31 09:04:10 +03:00
CTCaer
d258c82d52 bdk: sdmmc: add UHS DDR200 support
The bdk flag BDK_SDMMC_UHS_DDR200_SUPPORT can be used to enable it.

SD Card DDR200 (DDR208) support

Proper procedure:
1. Check that Vendor Specific Command System is supported.
   Used as Enable DDR200 Bus.
2. Enable DDR200 bus mode via setting 14 to Group 2 via CMD6.
   Access Mode group is left to default 0 (SDR12).
3. Setup clock to 200 or 208 MHz.
4. Set host to DDR bus mode that supports such high clocks.
   Some hosts have special mode, others use DDR50 and others HS400.
5. Execute Tuning.

The true validation that this value in Group 2 activates it, is that DDR50 bus
and clocks/timings work fully after that point.

On Tegra X1, that can be done with DDR50 host mode.
Tuning though can't be done automatically on any DDR mode.
So it needs to be done manually and selected tap will be applied from the
biggest sampling window.

Finally, all that simply works, because the marketing materials for DDR200 are
basically overstatements to sell the feature. DDR200 is simply SDR104 in DDR mode,
so sampling on rising and falling edge and with variable output data window.
It can be supported by any host that is fast enough to support DDR at 200/208MHz
and can do hw/sw tuning for finding the proper sampling window in that mode.

Using a SDMMC controller on DDR200 mode at 400MHz, has latency allowance implications. The MC/EMC must be clocked enough to be able to serve the requests in time (512B in 1.28 ns).
2023-03-31 08:54:13 +03:00
CTCaer
2f7e841b50 bdk: sdmmc: move sdr12 setup for better readability 2023-03-31 08:29:20 +03:00
CTCaer
b123571c56 bdk: sdmmc: only allow power raise if SDR50 and up
As per spec.
2023-03-31 08:26:19 +03:00
CTCaer
b7164a629f bdk: sdmmc: allow max power limit to be set
Even if it defaults to 1.44W.
Some cards' firmware maybe be bugged.

The 3.3V regulator on all SKUs allow more than 800mA current anyway.
2023-03-31 08:24:52 +03:00
CTCaer
25be98b7e3 bdk: sdmmc: add UHS DDR50 support
But disable it by default in the auto selection.
2023-03-31 08:23:10 +03:00
CTCaer
502fc1ed50 bdk: sdmmc: rename ddr100 to the actual HS100 name 2023-03-31 08:15:40 +03:00
CTCaer
9a222e0e49 bdk: sdmmc: rename divisor param to card clock 2023-03-31 07:53:46 +03:00
CTCaer
298893f404 bdk: sdmmc: remove powersave arg from sdmmc init 2023-03-31 07:51:43 +03:00
CTCaer
1ce5bb10f8 bdk: sdmmc: refactor debug prints 2023-03-31 07:49:26 +03:00
CTCaer
9a98c1afb9 bdk: stylistic corrections
And update copyrights
2023-02-11 23:46:38 +02:00
CTCaer
22bdd0e0ff bdk: sdmmc: remove unused power limits
Also name some magic numbers
2023-02-11 23:15:28 +02:00
CTCaer
4d823d5909 bdk: slight refactor 2022-12-19 05:22:55 +02:00
CTCaer
6257d20db9 bdk: emmc: add emmc_set_partition
Additionally, add SDMMC index info to errors.
2022-12-19 04:53:50 +02:00
CTCaer
197ce4c76f bdk: sdmmc: timing changes
- Correct HS102 naming to DDR100
- Fix clock for DDR50 (even if it's unused)
2022-10-11 04:05:12 +03:00
CTCaer
70523e404f bdk: whitespace refactor 2022-07-11 22:10:11 +03:00
CTCaer
b0c0a86108 bdk: migrate timers/sleeps to timer driver 2022-06-27 10:22:19 +03:00
CTCaer
e5ddac5211 bdk: sdmmc: rename current limit to power limit 2022-06-25 05:53:04 +03:00
CTCaer
489e222aac bdk: sdmmc: expose csd/scr functions 2022-06-25 05:48:54 +03:00
CTCaer
c77c741c07 bdk: sdmmc: correct lower speed mode checks
Both bus widths of 8 and 4 should be checked for HS200 support and host type support, instead of giving 8-bit bus width a free pass.
2022-05-26 03:04:27 +03:00
CTCaer
ee465b98af bdk: sdmmc correct exit on eMMC < 4.0 modules 2022-02-15 00:24:53 +02:00
CTCaer
ef5790cc2c bdk: mc: always on ahb arbitration
- Removed disables
- SDMMC code now just checks if it has access
2022-01-29 01:29:02 +02:00
CTCaer
b08e36a7b0 bdk: add emmc ops
- Add support for lower eMMC bus speed init in case of failures
- Add error count reporting
- Function names and defines changed from nx_emmc to emmc (except autorcm helper function)
- Enabling emuMMC support needs BDK_EMUMMC_ENABLE flag passed over
2022-01-20 13:14:38 +02:00
CTCaer
a5cd962f99 bdk: add global header 2022-01-15 23:58:27 +02:00
CTCaer
dcdf687a07 sdmmc: add support for sandisk emmc device report 2021-07-06 10:15:59 +03:00
CTCaer
a4a056128a sdmmc: Add support for SDSC cards 2021-02-06 04:18:30 +02:00
CTCaer
a8a45b215a nyx: Add emmc info about write cache and enhanced area 2021-02-06 03:44:27 +02:00
CTCaer
38f456a2ee sdmmc: Refactor again
- Refactor various variables and defines
- Removed Card/BGA and OEM ID info as they are static and useless
- Commented out bkops functions completely as not used
- Remove extra buf usage when there's already storage for storing that data
- Optimize various functions to save space
- Clean up useless or duplicate code
2021-02-06 03:41:35 +02:00
CTCaer
fce59fba43 nyx: Add SD card AU info 2020-12-11 17:41:09 +02:00
CTCaer
5b8fb9fb6b Various refactoring and addition of comments 2020-12-11 17:25:59 +02:00
CTCaer
c13eabcde8 sdmmc: Add T210B01 support
The driver was working before this, but adding the changes provides a proper and better sdmmc controller inner state.
2020-12-02 02:07:15 +02:00
CTCaer
cabaa6cfb8 Utilize BIT macro everywhere 2020-11-26 01:41:45 +02:00
CTCaer
89a4eadab0 sdmmc: Refactor some names 2020-11-26 01:08:42 +02:00
CTCaer
55395ea4fd sdmmc: Correct bus speed for SDR25
Fix bus speed on SDR25 even if all UHS cards support SDR50 and SDR104.
2020-11-15 15:11:19 +02:00
CTCaer
4166a3c128 sdmmc: Add more debugging 2020-11-15 15:08:53 +02:00
CTCaer
1f5b371608 Refactor some names
Additionally:
- Do not retry to init sd if all modes failed in Nyx.
- Do not try to read/write if sdmmc controller and card are not initialized.
2020-10-23 06:32:24 +03:00
CTCaer
d71f6d0b99 sdmmc: Restart xfer on Read/Write error 2020-08-28 09:39:06 +03:00
CTCaer
7b03a24196 sdmmc: Add extra error printing 2020-08-15 13:16:37 +03:00
CTCaer
82da1aaf2a sdmmc: Correct name of bus speed 14 2020-07-17 17:38:01 +03:00
CTCaer
3c2d86ef7b sdmmc: Add protected area info (Content Protection) 2020-07-17 17:01:40 +03:00
CTCaer
6e256d29c7 Utilize hekate's BDK for hekate main and Nyx 2020-06-14 16:45:45 +03:00
CTCaer
185526d134 Introducing Bootloader Development Kit (BDK)
BDK will allow developers to use the full collection of drivers,
with limited editing, if any, for making payloads for Nintendo Switch.

Using a single source for everything will also help decoupling
Switch specific code and easily port it to other Tegra X1/X1+ platforms.
And maybe even to lower targets.

Everything is now centrilized into bdk folder.
Every module or project can utilize it by simply including it.

This is just the start and it will continue to improve.
2020-06-14 15:25:21 +03:00
Renamed from bootloader/storage/sdmmc.c (Browse further)