TuxSH
|
3b542e749f
|
thermosphere: add TransportInterface abstraction layer
|
2020-02-04 19:12:21 +00:00 |
|
TuxSH
|
26bda4f32d
|
thermosphere: refactor tegra uart code, etc.
|
2020-02-04 19:12:21 +00:00 |
|
TuxSH
|
a552c254e0
|
thermosphere: pl011 uart refactor
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
57548e67fb
|
thermosphere: fix pl101 uart reg definitions
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
edb942a032
|
thermosphere: add proper memory/instruction barriers for breakpoint stuff
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
0dd5f1f6d4
|
thermosphere: add hypervisor timer code
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
4d8a07943c
|
thermosphere: qemu: get rid of arm tf
qemu impls psci anyway
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
f19c67435a
|
thermosphere: refactor exception handlers & add stolen time/emulated ptimer logic
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
2f999497df
|
thermosphere: rewrite sysreg trapping code, add skeleton code for timer val trap handling; support A32 EL1 once again
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
a67d682c10
|
thermosphere: don't trap memory register writes/don't migrate sw breakpoints
Makes no sense on a system with ASLR
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
2219494675
|
thermosphere: vgic: largely reduce the number of mmio accesses
since we have to use 64 bits for VirqState anyway
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
d560330a9d
|
thermosphere: make the pending virq list ordering stable
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
3424e0bf71
|
thermosphere: fix wrong icfgr shift; fix list handling bug
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
7d30fce54c
|
thermosphere: vgic: fix OOB accesses, fix icfgr and itargetsr handling
qemu actually allows SPIs to use the N-N model
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
81a3b4fff5
|
thermosphere: fix is/ic registers usage; fix offset calculation
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
d43d1af62a
|
thermosphere: fix truncation in vgicCleanupPendingList
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
7573d1ad3e
|
thermosphere: honor irq config for ppis
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
5f83df2599
|
thermosphere: yikes
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
aeca48503b
|
thermosphere: use strict volatile bitfields just in case
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
0fb5f81e8a
|
thermosphere: vgic: fix critical bug in vgicUpdateState, add more checks
Yikes.
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
b0d258209c
|
thermosphere: add CFI where needed, add PANIC macro, etc.
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
c365fff119
|
thermosphere: vgic: mostly fix vSGI handling, remove unimplementable/unused stuff + bugfixes
Still somewhat broken, though
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
0b532a0dfb
|
thermosphere: fix guest access to irq 25, etc; we don't need to raise VI manually
See Armv8a TRM "Virtual IRQ exception"
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
1345aef693
|
thermosphere: add PPI definitions
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
eda6a8d8d6
|
vgic: fix multiple bugs
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
f75f584f2f
|
thermosphere: fix various vgic bugs; fix register access OOB bug (xzr)
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
62fe082cd4
|
thermosphere: vgic: fix enabled state of virqs
|
2020-02-04 19:12:20 +00:00 |
|
TuxSH
|
6cef320bc1
|
thermosphere: fix multiple bugs
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
e7b351ddb8
|
thermosphere: vgic code draft
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
9787bca325
|
thermosphere: also trap GICH (to deny access)
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
bb1ba5308d
|
thermosphere: handle stage2 data aborts, trap gicd accesses
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
442f4ef9ef
|
thermosphere: implement stop point broadcast
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
3af20ff7a2
|
thermopshere: add "execute function" sgi
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
322d796004
|
thermosphere: barrier & active core mask
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
c34df08ed9
|
thermosphere: handle physical IRQs
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
62fd2cd94d
|
thermosphere: add gicv2 register definitions
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
e71974085e
|
thermosphere: sw breakpoint code, etc.
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
577daaebf0
|
thermosphere: remove breakpoint/watchpoint reg dump functions
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
aad18182f4
|
thermosphere: add watchpoint + watchpoint merging code
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
0435b73f63
|
thermosphere: refactor crt0 + watchpoint init
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
bd93b01e57
|
thermosphere: add actual breakpoint code
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
88218f606c
|
thermosphere: add breakpoint/watchpoint enable/reset code
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
5081174d27
|
thermopshere: refactor & fix single-stepping code
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
731d50a3a3
|
thermopshere: refactor jump-to-kernel ,add single-step code
not working under qemu yet though
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
9c9f6c04cc
|
thermosphere: add spinlock code
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
0c0d9f5335
|
thermometer: yeet most a32 support code 👌
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
7f9c80abec
|
thermosphere: impl stage2 translation
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
c33d2ee369
|
thermosphere: rework linkscrips, use discardable sections, better sp pivot on crash
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
0b1ab362c6
|
thermosphere: add shadow page table hooks
note: HCR.TVM not supported by qemu yet
|
2020-02-04 19:12:19 +00:00 |
|
TuxSH
|
823b2c8a6d
|
thermosphere: enable EL2 stage1 translation (doesn't take much space)
Identity map using 1GB L1 blocks
|
2020-02-04 19:12:19 +00:00 |
|