mirror of
https://github.com/CTCaer/hekate
synced 2024-07-03 15:03:29 +00:00
cae9044c17
Supports up to 1600MHz and periodic training. For more check here: https://github.com/CTCaer/minerva_tc
411 lines
16 KiB
C
411 lines
16 KiB
C
/*
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* Minerva Training Cell
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* DRAM Training for Tegra X1 SoC. Supports DDR2/3 and LPDDR3/4.
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*
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* Copyright (c) 2018 CTCaer <ctcaer@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _MTC_H_
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#define _MTC_H_
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#include "mtc_table.h"
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#include "types.h"
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/* Addresses and access macros - Change these for mapped access */
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#define TMR_BASE 0x60005000
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#define CLOCK_BASE 0x60006000
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#define MC_BASE 0x70019000
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#define EMC_BASE 0x7001B000
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#define EMC0_BASE 0x7001E000
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#define EMC1_BASE 0x7001F000
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#define MTC_TABLE 0x8F000000
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#define _REG(base, off) *(vu32 *)((base) + (off))
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#define TMR(off) _REG(TMR_BASE, off)
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#define CLOCK(off) _REG(CLOCK_BASE, off)
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#define MC(off) _REG(MC_BASE, off)
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#define EMC(off) _REG(EMC_BASE, off)
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#define EMC_CH0(off) _REG(EMC0_BASE, off)
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#define EMC_CH1(off) _REG(EMC1_BASE, off)
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/* End of addresses and access macros */
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#define EMC_STATUS_UPDATE_TIMEOUT 1000
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/* Clock controller address offsets */
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#define CLK_RST_CONTROLLER_PLLM_BASE 0x90
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#define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C
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#define PLLM_ENABLE (1 << 30)
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#define PLLM_LOCK (1 << 27)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C
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#define EMC_2X_CLK_SRC_SHIFT 29
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X 0x280
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#define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284
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#define CLK_RST_CONTROLLER_CLK_ENB_X_CLR 0x288
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#define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E8
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x664
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE 0x724
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/* Memory controller address offsets */
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#define MC_EMEM_ADR_CFG 0x54
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/* External Memory controller address offsets */
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#define EMC_INTSTATUS 0x0
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#define CLKCHANGE_COMPLETE_INT (1 << 4)
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#define EMC_DBG 0x8
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#define EMC_CFG 0xC
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#define EMC_PIN 0x24
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#define EMC_TIMING_CONTROL 0x28
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#define EMC_RP 0x38
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#define EMC_R2P 0x44
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#define EMC_W2P 0x48
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#define EMC_TRPAB 0x9C
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#define EMC_MRS_WAIT_CNT2 0xC4
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#define EMC_MRS 0xCC
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#define EMC_EMRS 0xD0
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#define EMC_REF 0xD4
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#define EMC_MRW 0xe8
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#define EMC_SELF_REF 0xE0
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#define EMC_MRR 0xEC
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#define EMC_FBIO_CFG5 0x104
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#define EMC_MPC 0x128
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#define EMC_EMRS2 0x12C
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#define EMC_MRW2 0x134
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#define EMC_MRW3 0x138
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#define EMC_MRW4 0x13C
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#define EMC_AUTO_CAL_CONFIG 0x2A4
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#define EMC_EMC_STATUS 0x2B4
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#define TIMING_UPDATE_STALLED (1 << 23)
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#define MRR_DIVLD (1 << 20)
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#define IN_SELF_REFRESH_MASK (3 << 8)
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#define IN_POWERDOWN_MASK (3 << 4)
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#define REQ_FIFO_EMPTY (1 << 0)
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#define EMC_CFG_2 0x2B8
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#define EMC_CFG_DIG_DLL 0x2BC
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#define EMC_DIG_DLL_STATUS 0x2C4
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#define EMC_AUTO_CAL_CONFIG8 0x2DC
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#define EMC_ZCAL_INTERVAL 0x2E0
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#define EMC_ZCAL_WAIT_CNT 0x2E4
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#define EMC_ZQ_CAL 0x2EC
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#define EMC_SCRATCH0 0x324
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#define EMC_PMACRO_BRICK_CTRL_RFU1 0x330
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#define EMC_TR_CTRL_0 0x3B8
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#define EMC_SWITCH_BACK_CTRL 0x3C0
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#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3CC
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#define EMC_SEL_DPD_CTRL 0x3D8
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#define EMC_CCFIFO_ADDR 0x3E8
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#define EMC_CCFIFO_DATA 0x3EC
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#define EMC_CCFIFO_STATUS 0x3F0
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#define EMC_AUTO_CAL_CONFIG2 0x458
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#define EMC_AUTO_CAL_CONFIG3 0x45C
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#define EMC_TR_DVFS 0x460
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#define EMC_MRW6 0x4A4
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#define EMC_MRW7 0x4A8
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#define EMC_MRW14 0x4C4
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#define EMC_MRW15 0x4D0
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#define EMC_CFG_SYNC 0x4D4
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#define EMC_FDPD_CTRL_CMD_NO_RAMP 0x4D8
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#define EMC_CFG_PIPE_CLK 0x558
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#define EMC_AUTO_CAL_CONFIG7 0x574
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#define EMC_FBIO_CFG7 0x584
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#define EMC_DATA_BRLSHFT_0 0x588
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#define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT 0
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#define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT 3
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#define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT 6
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#define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT 9
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#define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT 12
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#define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT 15
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#define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT 18
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#define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT 21
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#define EMC_DATA_BRLSHFT_1 0x58C
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#define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT 0
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#define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT 3
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#define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT 6
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#define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT 9
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#define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT 12
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#define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT 15
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#define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT 18
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#define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT 21
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#define EMC_CMD_BRLSHFT_0 0x59C
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#define EMC_CMD_BRLSHFT_1 0x5A0
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#define EMC_QUSE_BRLSHFT_0 0x5AC
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#define EMC_AUTO_CAL_CONFIG4 0x5B0
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#define EMC_AUTO_CAL_CONFIG5 0x5B4
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#define EMC_QUSE_BRLSHFT_1 0x5B8
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#define EMC_QUSE_BRLSHFT_2 0x5BC
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#define EMC_QUSE_BRLSHFT_3 0x5C4
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#define EMC_AUTO_CAL_CONFIG6 0x5CC
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#define EMC_DLL_CFG_0 0x5E4
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#define EMC_DLL_CFG_1 0x5E8
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#define EMC_CFG_UPDATE 0x5F4
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#define EMC_PMACRO_QUSE_DDLL_RANK0_0 0x600
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#define EMC_PMACRO_QUSE_DDLL_RANK0_1 0x604
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#define EMC_PMACRO_QUSE_DDLL_RANK0_2 0x608
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#define EMC_PMACRO_QUSE_DDLL_RANK0_3 0x60C
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#define EMC_PMACRO_QUSE_DDLL_RANK1_0 0x620
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#define EMC_PMACRO_QUSE_DDLL_RANK1_1 0x624
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#define EMC_PMACRO_QUSE_DDLL_RANK1_2 0x628
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#define EMC_PMACRO_QUSE_DDLL_RANK1_3 0x62C
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 0x640
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 0x644
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 0x648
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 0x64C
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 0x650
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 0x654
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 0x660
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 0x664
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 0x668
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 0x66C
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0 0x6C0
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1 0x6C4
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2 0x6C8
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3 0x6CC
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0 0x6E0
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1 0x6E4
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2 0x6E8
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3 0x6EC
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0x800
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0x804
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0x808
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0x810
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0x814
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0x818
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0x820
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0x824
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0x828
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0x830
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0x834
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0x838
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0x840
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0x844
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0x848
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0x850
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0x854
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0x858
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0x860
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0x864
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0x868
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0x870
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0x874
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0x878
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 0x880
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 0x884
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 0x888
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 0x890
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 0x894
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 0x898
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 0x8A0
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 0x8A4
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 0x8A8
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 0x8B0
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 0x8B4
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 0x8B8
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0x900
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0x904
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0x908
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0x910
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0x914
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0x918
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0x920
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0x924
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0x928
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0x930
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0x934
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0x938
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0x940
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0x944
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0x948
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0x950
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0x954
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0x958
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0x960
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0x964
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0x968
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0x970
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0x974
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0x978
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0xA00
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0xA04
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0xA08
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0xA10
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0xA14
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0xA18
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0xA20
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0xA24
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0xA28
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0xA30
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0xA34
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0xA38
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0xA40
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0xA44
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0xA48
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0xA50
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0xA54
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0xA58
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0xA60
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0xA64
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0xA68
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0xA70
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0xA74
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0xA78
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0xB00
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0xB04
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0xB08
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0xB10
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0xB14
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0xB18
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0xB20
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0xB24
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0xB28
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0xB30
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0xB34
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0xB38
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0xB40
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0xB44
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0xB48
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0xB50
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0xB54
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0xB58
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0xB60
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0xB64
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0xB68
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0xB70
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0xB74
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0xB78
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#define EMC_PMACRO_IB_VREF_DQ_0 0xBE0
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#define EMC_PMACRO_IB_VREF_DQ_1 0xBE4
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#define EMC_PMACRO_IB_VREF_DQS_0 0xBF0
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#define EMC_PMACRO_IB_VREF_DQS_1 0xBF4
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#define EMC_PMACRO_CFG_PM_GLOBAL_0 0xC30
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#define EMC_PMACRO_BG_BIAS_CTRL_0 0xC3C
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#define EMC_PMACRO_DATA_RX_TERM_MODE 0xC5C
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#define EMC_PMACRO_CMD_PAD_TX_CTRL 0xC60
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#define EMC_PMACRO_DATA_PAD_TX_CTRL 0xC64
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#define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xC68
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#define EMC_PMACRO_AUTOCAL_CFG_COMMON 0xC78
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#define EMC_PMACRO_TRAINING_CTRL_0 0xCF8
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#define CH0_TRAINING_E_WRPTR (1 << 3)
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#define EMC_PMACRO_TRAINING_CTRL_1 0xCFC
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#define EMC_TRAINING_CMD 0xE00
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#define EMC_TRAINING_CTRL 0xE04
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#define EMC_TRAINING_STATUS 0xE08
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#define EMC_TRAINING_PATRAM_CTRL 0xE60
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#define EMC_TRAINING_PATRAM_DQ 0xE64
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#define EMC_TRAINING_PATRAM_DMI 0xE68
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#define EMC_TRAINING_OPT_CA_VREF 0xEC0
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#define EMC_TRAINING_OPT_DQ_OB_VREF 0xEC4
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#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 0xED4
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#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 0xED8
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE0_SHIFT 0
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE1_SHIFT 16
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE2_SHIFT 0
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE3_SHIFT 16
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE4_SHIFT 0
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE5_SHIFT 16
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE6_SHIFT 0
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE7_SHIFT 16
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typedef struct
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{
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int rate_to;
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int rate_from;
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emc_table_t *mtc_table;
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u32 table_entries;
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emc_table_t *current_emc_table;
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u32 train_mode;
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u32 sdram_id;
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bool emc_2X_clk_src_is_pllmb;
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bool fsp_for_src_freq;
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bool train_ram_patterns;
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} mtc_config_t;
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enum train_mode_t
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{
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OP_SWITCH = 0,
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OP_TRAIN = 1,
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OP_TRAIN_SWITCH = 2,
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OP_PERIODIC_TRAIN = 3
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};
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enum comp_seq_t
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{
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DVFS_SEQUENCE = 1,
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WRITE_TRAINING_SEQUENCE = 2,
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PERIODIC_TRAINING_SEQUENCE = 3
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};
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enum tree_update_mode_t
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{
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DVFS_PT1 = 10,
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DVFS_UPDATE = 11,
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TRAINING_PT1 = 12,
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TRAINING_UPDATE = 13,
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PERIODIC_TRAINING_UPDATE = 14
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};
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enum emc_channels
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{
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EMC_CH0 = 0,
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EMC_CH1 = 1
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};
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enum EMC_2X_CLK_SRC
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{
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PLLM_OUT0 = 0x0,
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PLLC_OUT0 = 0x1,
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PLLP_OUT0 = 0x2,
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CLK_M = 0x3,
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PLLM_UD = 0x4,
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PLLMB_UD = 0x5,
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PLLMB_OUT0 = 0x6,
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PLLP_UD = 0x7
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};
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enum DRAM_TYPE
|
|
{
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|
DRAM_TYPE_DDR3 = 0,
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|
DRAM_TYPE_LPDDR4 = 1,
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|
DRAM_TYPE_LPDDR2 = 2,
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DRAM_TYPE_DDR2 = 3
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};
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|
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enum DRAM_DEV_NO
|
|
{
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|
ONE_RANK = 1,
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|
TWO_RANK = 2
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|
};
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#endif
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