/* * Minerva Training Cell * DRAM Training for Tegra X1 SoC. Supports DDR2/3 and LPDDR3/4. * * Copyright (c) 2018 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ #ifndef _MTC_H_ #define _MTC_H_ #include "mtc_table.h" #include "types.h" /* Addresses and access macros - Change these for mapped access */ #define TMR_BASE 0x60005000 #define CLOCK_BASE 0x60006000 #define MC_BASE 0x70019000 #define EMC_BASE 0x7001B000 #define EMC0_BASE 0x7001E000 #define EMC1_BASE 0x7001F000 #define MTC_TABLE 0x8F000000 #define _REG(base, off) *(vu32 *)((base) + (off)) #define TMR(off) _REG(TMR_BASE, off) #define CLOCK(off) _REG(CLOCK_BASE, off) #define MC(off) _REG(MC_BASE, off) #define EMC(off) _REG(EMC_BASE, off) #define EMC_CH0(off) _REG(EMC0_BASE, off) #define EMC_CH1(off) _REG(EMC1_BASE, off) /* End of addresses and access macros */ #define EMC_STATUS_UPDATE_TIMEOUT 1000 /* Clock controller address offsets */ #define CLK_RST_CONTROLLER_PLLM_BASE 0x90 #define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C #define PLLM_ENABLE (1 << 30) #define PLLM_LOCK (1 << 27) #define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C #define EMC_2X_CLK_SRC_SHIFT 29 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_X 0x280 #define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284 #define CLK_RST_CONTROLLER_CLK_ENB_X_CLR 0x288 #define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E8 #define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x664 #define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE 0x724 /* Memory controller address offsets */ #define MC_EMEM_ADR_CFG 0x54 /* External Memory controller address offsets */ #define EMC_INTSTATUS 0x0 #define CLKCHANGE_COMPLETE_INT (1 << 4) #define EMC_DBG 0x8 #define EMC_CFG 0xC #define EMC_PIN 0x24 #define EMC_TIMING_CONTROL 0x28 #define EMC_RP 0x38 #define EMC_R2P 0x44 #define EMC_W2P 0x48 #define EMC_TRPAB 0x9C #define EMC_MRS_WAIT_CNT2 0xC4 #define EMC_MRS 0xCC #define EMC_EMRS 0xD0 #define EMC_REF 0xD4 #define EMC_MRW 0xe8 #define EMC_SELF_REF 0xE0 #define EMC_MRR 0xEC #define EMC_FBIO_CFG5 0x104 #define EMC_MPC 0x128 #define EMC_EMRS2 0x12C #define EMC_MRW2 0x134 #define EMC_MRW3 0x138 #define EMC_MRW4 0x13C #define EMC_AUTO_CAL_CONFIG 0x2A4 #define EMC_EMC_STATUS 0x2B4 #define TIMING_UPDATE_STALLED (1 << 23) #define MRR_DIVLD (1 << 20) #define IN_SELF_REFRESH_MASK (3 << 8) #define IN_POWERDOWN_MASK (3 << 4) #define REQ_FIFO_EMPTY (1 << 0) #define EMC_CFG_2 0x2B8 #define EMC_CFG_DIG_DLL 0x2BC #define EMC_DIG_DLL_STATUS 0x2C4 #define EMC_AUTO_CAL_CONFIG8 0x2DC #define EMC_ZCAL_INTERVAL 0x2E0 #define EMC_ZCAL_WAIT_CNT 0x2E4 #define EMC_ZQ_CAL 0x2EC #define EMC_SCRATCH0 0x324 #define EMC_PMACRO_BRICK_CTRL_RFU1 0x330 #define EMC_TR_CTRL_0 0x3B8 #define EMC_SWITCH_BACK_CTRL 0x3C0 #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3CC #define EMC_SEL_DPD_CTRL 0x3D8 #define EMC_CCFIFO_ADDR 0x3E8 #define EMC_CCFIFO_DATA 0x3EC #define EMC_CCFIFO_STATUS 0x3F0 #define EMC_AUTO_CAL_CONFIG2 0x458 #define EMC_AUTO_CAL_CONFIG3 0x45C #define EMC_TR_DVFS 0x460 #define EMC_MRW6 0x4A4 #define EMC_MRW7 0x4A8 #define EMC_MRW14 0x4C4 #define EMC_MRW15 0x4D0 #define EMC_CFG_SYNC 0x4D4 #define EMC_FDPD_CTRL_CMD_NO_RAMP 0x4D8 #define EMC_CFG_PIPE_CLK 0x558 #define EMC_AUTO_CAL_CONFIG7 0x574 #define EMC_FBIO_CFG7 0x584 #define EMC_DATA_BRLSHFT_0 0x588 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT 0 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT 3 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT 6 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT 9 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT 12 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT 15 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT 18 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT 21 #define EMC_DATA_BRLSHFT_1 0x58C #define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT 0 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT 3 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT 6 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT 9 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT 12 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT 15 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT 18 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT 21 #define EMC_CMD_BRLSHFT_0 0x59C #define EMC_CMD_BRLSHFT_1 0x5A0 #define EMC_QUSE_BRLSHFT_0 0x5AC #define EMC_AUTO_CAL_CONFIG4 0x5B0 #define EMC_AUTO_CAL_CONFIG5 0x5B4 #define EMC_QUSE_BRLSHFT_1 0x5B8 #define EMC_QUSE_BRLSHFT_2 0x5BC #define EMC_QUSE_BRLSHFT_3 0x5C4 #define EMC_AUTO_CAL_CONFIG6 0x5CC #define EMC_DLL_CFG_0 0x5E4 #define EMC_DLL_CFG_1 0x5E8 #define EMC_CFG_UPDATE 0x5F4 #define EMC_PMACRO_QUSE_DDLL_RANK0_0 0x600 #define EMC_PMACRO_QUSE_DDLL_RANK0_1 0x604 #define EMC_PMACRO_QUSE_DDLL_RANK0_2 0x608 #define EMC_PMACRO_QUSE_DDLL_RANK0_3 0x60C #define EMC_PMACRO_QUSE_DDLL_RANK1_0 0x620 #define EMC_PMACRO_QUSE_DDLL_RANK1_1 0x624 #define EMC_PMACRO_QUSE_DDLL_RANK1_2 0x628 #define EMC_PMACRO_QUSE_DDLL_RANK1_3 0x62C #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 0x640 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 0x644 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 0x648 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 0x64C #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 0x650 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 0x654 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 0x660 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 0x664 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 0x668 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 0x66C #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0 0x6C0 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1 0x6C4 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2 0x6C8 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3 0x6CC #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0 0x6E0 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1 0x6E4 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2 0x6E8 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3 0x6EC #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0x800 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0x804 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0x808 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0x810 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0x814 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0x818 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0x820 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0x824 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0x828 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0x830 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0x834 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0x838 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0x840 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0x844 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0x848 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0x850 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0x854 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0x858 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0x860 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0x864 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0x868 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0x870 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0x874 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0x878 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 0x880 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 0x884 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 0x888 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 0x890 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 0x894 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 0x898 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 0x8A0 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 0x8A4 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 0x8A8 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 0x8B0 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 0x8B4 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 0x8B8 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0x900 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0x904 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0x908 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0x910 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0x914 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0x918 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0x920 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0x924 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0x928 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0x930 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0x934 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0x938 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0x940 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0x944 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0x948 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0x950 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0x954 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0x958 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0x960 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0x964 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0x968 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0x970 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0x974 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0x978 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0xA00 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0xA04 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0xA08 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0xA10 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0xA14 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0xA18 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0xA20 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0xA24 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0xA28 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0xA30 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0xA34 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0xA38 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0xA40 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0xA44 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0xA48 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0xA50 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0xA54 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0xA58 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0xA60 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0xA64 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0xA68 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0xA70 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0xA74 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0xA78 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0xB00 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0xB04 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0xB08 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0xB10 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0xB14 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0xB18 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0xB20 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0xB24 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0xB28 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0xB30 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0xB34 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0xB38 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0xB40 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0xB44 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0xB48 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0xB50 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0xB54 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0xB58 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0xB60 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0xB64 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0xB68 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0xB70 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0xB74 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0xB78 #define EMC_PMACRO_IB_VREF_DQ_0 0xBE0 #define EMC_PMACRO_IB_VREF_DQ_1 0xBE4 #define EMC_PMACRO_IB_VREF_DQS_0 0xBF0 #define EMC_PMACRO_IB_VREF_DQS_1 0xBF4 #define EMC_PMACRO_CFG_PM_GLOBAL_0 0xC30 #define EMC_PMACRO_BG_BIAS_CTRL_0 0xC3C #define EMC_PMACRO_DATA_RX_TERM_MODE 0xC5C #define EMC_PMACRO_CMD_PAD_TX_CTRL 0xC60 #define EMC_PMACRO_DATA_PAD_TX_CTRL 0xC64 #define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xC68 #define EMC_PMACRO_AUTOCAL_CFG_COMMON 0xC78 #define EMC_PMACRO_TRAINING_CTRL_0 0xCF8 #define CH0_TRAINING_E_WRPTR (1 << 3) #define EMC_PMACRO_TRAINING_CTRL_1 0xCFC #define EMC_TRAINING_CMD 0xE00 #define EMC_TRAINING_CTRL 0xE04 #define EMC_TRAINING_STATUS 0xE08 #define EMC_TRAINING_PATRAM_CTRL 0xE60 #define EMC_TRAINING_PATRAM_DQ 0xE64 #define EMC_TRAINING_PATRAM_DMI 0xE68 #define EMC_TRAINING_OPT_CA_VREF 0xEC0 #define EMC_TRAINING_OPT_DQ_OB_VREF 0xEC4 #define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 0xED4 #define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 0xED8 #define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE0_SHIFT 0 #define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE1_SHIFT 16 #define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE2_SHIFT 0 #define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE3_SHIFT 16 #define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE4_SHIFT 0 #define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE5_SHIFT 16 #define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE6_SHIFT 0 #define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE7_SHIFT 16 typedef struct { int rate_to; int rate_from; emc_table_t *mtc_table; u32 table_entries; emc_table_t *current_emc_table; u32 train_mode; u32 sdram_id; bool emc_2X_clk_src_is_pllmb; bool fsp_for_src_freq; bool train_ram_patterns; } mtc_config_t; enum train_mode_t { OP_SWITCH = 0, OP_TRAIN = 1, OP_TRAIN_SWITCH = 2, OP_PERIODIC_TRAIN = 3 }; enum comp_seq_t { DVFS_SEQUENCE = 1, WRITE_TRAINING_SEQUENCE = 2, PERIODIC_TRAINING_SEQUENCE = 3 }; enum tree_update_mode_t { DVFS_PT1 = 10, DVFS_UPDATE = 11, TRAINING_PT1 = 12, TRAINING_UPDATE = 13, PERIODIC_TRAINING_UPDATE = 14 }; enum emc_channels { EMC_CH0 = 0, EMC_CH1 = 1 }; enum EMC_2X_CLK_SRC { PLLM_OUT0 = 0x0, PLLC_OUT0 = 0x1, PLLP_OUT0 = 0x2, CLK_M = 0x3, PLLM_UD = 0x4, PLLMB_UD = 0x5, PLLMB_OUT0 = 0x6, PLLP_UD = 0x7 }; enum DRAM_TYPE { DRAM_TYPE_DDR3 = 0, DRAM_TYPE_LPDDR4 = 1, DRAM_TYPE_LPDDR2 = 2, DRAM_TYPE_DDR2 = 3 }; enum DRAM_DEV_NO { ONE_RANK = 1, TWO_RANK = 2 }; #endif