mirror of
https://github.com/CTCaer/hekate
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274 lines
5.4 KiB
C
274 lines
5.4 KiB
C
/*
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* BPMP-Lite IRQ driver for Tegra X1
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*
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* Copyright (c) 2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include "irq.h"
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#include <soc/timer.h>
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#include <soc/t210.h>
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#include <gfx_utils.h>
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#include <mem/heap.h>
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//#define DPRINTF(...) gfx_printf(__VA_ARGS__)
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#define DPRINTF(...)
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extern void irq_disable();
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extern void irq_enable_cpu_irq_exceptions();
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extern void irq_disable_cpu_irq_exceptions();
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typedef struct _irq_ctxt_t
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{
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u32 irq;
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int (*handler)(u32 irq, void *data);
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void *data;
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u32 flags;
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} irq_ctxt_t;
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bool irq_init_done = false;
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irq_ctxt_t irqs[IRQ_MAX_HANDLERS];
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static void _irq_enable_source(u32 irq)
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{
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u32 ctrl_idx = irq >> 5;
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u32 bit = irq % 32;
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// Set as normal IRQ.
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ICTLR(ctrl_idx, PRI_ICTLR_COP_IEP_CLASS) &= ~BIT(bit);
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// Enable IRQ source.
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ICTLR(ctrl_idx, PRI_ICTLR_COP_IER_SET) = BIT(bit);
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}
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static void _irq_disable_source(u32 irq)
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{
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u32 ctrl_idx = irq >> 5;
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u32 bit = irq % 32;
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// Disable IRQ source.
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ICTLR(ctrl_idx, PRI_ICTLR_COP_IER_CLR) = BIT(bit);
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}
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static void _irq_disable_and_ack_all()
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{
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// Disable and ack all IRQ sources.
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for (u32 ctrl_idx = 0; ctrl_idx < 6; ctrl_idx++)
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{
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u32 enabled_irqs = ICTLR(ctrl_idx, PRI_ICTLR_COP_IER);
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ICTLR(ctrl_idx, PRI_ICTLR_COP_IER_CLR) = enabled_irqs;
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ICTLR(ctrl_idx, PRI_ICTLR_FIR_CLR) = enabled_irqs;
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}
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}
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static void _irq_ack_source(u32 irq)
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{
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u32 ctrl_idx = irq >> 5;
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u32 bit = irq % 32;
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// Force stop the interrupt as it's serviced here.
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ICTLR(ctrl_idx, PRI_ICTLR_FIR_CLR) = BIT(bit);
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}
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void irq_free(u32 irq)
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{
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for (u32 idx = 0; idx < IRQ_MAX_HANDLERS; idx++)
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{
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if (irqs[idx].irq == irq && irqs[idx].handler)
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{
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irqs[idx].irq = 0;
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irqs[idx].handler = NULL;
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irqs[idx].data = NULL;
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irqs[idx].flags = 0;
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_irq_disable_source(irq);
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}
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}
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}
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static void _irq_free_all()
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{
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for (u32 idx = 0; idx < IRQ_MAX_HANDLERS; idx++)
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{
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if (irqs[idx].handler)
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{
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_irq_disable_source(irqs[idx].irq);
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irqs[idx].irq = 0;
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irqs[idx].handler = NULL;
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irqs[idx].data = NULL;
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irqs[idx].flags = 0;
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}
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}
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}
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static irq_status_t _irq_handle_source(u32 irq)
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{
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int status = IRQ_NONE;
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_irq_disable_source(irq);
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_irq_ack_source(irq);
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u32 idx;
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for (idx = 0; idx < IRQ_MAX_HANDLERS; idx++)
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{
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if (irqs[idx].irq == irq)
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{
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status = irqs[idx].handler(irqs[idx].irq, irqs[idx].data);
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if (status == IRQ_HANDLED)
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break;
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}
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}
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// Do not re-enable if not handled.
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if (status == IRQ_NONE)
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return status;
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if (irqs[idx].flags & IRQ_FLAG_ONE_OFF)
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irq_free(irq);
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else
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_irq_enable_source(irq);
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return status;
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}
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void irq_handler()
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{
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// Get IRQ source.
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u32 irq = EXCP_VEC(EVP_COP_IRQ_STS) & 0xFF;
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if (!irq_init_done)
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{
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_irq_disable_source(irq);
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_irq_ack_source(irq);
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return;
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}
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DPRINTF("IRQ: %d\n", irq);
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int err = _irq_handle_source(irq);
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if (err == IRQ_NONE)
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{
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DPRINTF("Unhandled IRQ got disabled: %d!\n", irq);
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}
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}
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static void _irq_init()
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{
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_irq_disable_and_ack_all();
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memset(irqs, 0, sizeof(irq_ctxt_t) * IRQ_MAX_HANDLERS);
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irq_init_done = true;
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}
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void irq_end()
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{
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if (!irq_init_done)
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return;
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_irq_free_all();
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irq_disable_cpu_irq_exceptions();
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irq_init_done = false;
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}
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void irq_wait_event(u32 irq)
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{
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irq_disable_cpu_irq_exceptions();
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_irq_enable_source(irq);
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// Halt BPMP and wait for the IRQ. No need to use WAIT_EVENT + LIC_IRQ when BPMP serves the IRQ.
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FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_STOP_UNTIL_IRQ;
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_irq_disable_source(irq);
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_irq_ack_source(irq);
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irq_enable_cpu_irq_exceptions();
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}
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void irq_disable_wait_event()
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{
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irq_enable_cpu_irq_exceptions();
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}
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irq_status_t irq_request(u32 irq, irq_handler_t handler, void *data, irq_flags_t flags)
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{
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if (!irq_init_done)
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_irq_init();
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for (u32 idx = 0; idx < IRQ_MAX_HANDLERS; idx++)
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{
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if (irqs[idx].handler == NULL ||
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(irqs[idx].irq == irq && irqs[idx].flags & IRQ_FLAG_REPLACEABLE))
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{
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DPRINTF("Registered handler, IRQ: %d, Slot: %d\n", irq, idx);
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DPRINTF("Handler: %08p, Flags: %x\n", (u32)handler, flags);
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irqs[idx].irq = irq;
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irqs[idx].handler = handler;
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irqs[idx].data = data;
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irqs[idx].flags = flags;
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_irq_enable_source(irq);
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return IRQ_ENABLED;
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}
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else if (irqs[idx].irq == irq)
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return IRQ_ALREADY_REGISTERED;
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}
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return IRQ_NO_SLOTS_AVAILABLE;
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}
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void __attribute__ ((target("arm"))) fiq_setup()
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{
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/*
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asm volatile("mrs r12, cpsr\n\t"
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"bic r12, r12, #0x1F\n\t"
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"orr r12, r12, #0x11\n\t"
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"msr cpsr_c, r12\n\t");
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register volatile char *text asm ("r8");
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register volatile char *uart_tx asm ("r9");
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register int len asm ("r10");
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len = 5;
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uart_tx = (char *)0x70006040;
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memcpy((char *)text, "FIQ\r\n", len);
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*uart_tx = 0;
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asm volatile("mrs r12, cpsr\n"
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"orr r12, r12, #0x1F\n"
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"msr cpsr_c, r12");
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*/
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}
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void __attribute__ ((target("arm"), interrupt ("FIQ"))) fiq_handler()
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{
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/*
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register volatile char *text asm ("r8");
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register volatile char *uart_tx asm ("r9");
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register int len asm ("r10");
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while (len)
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{
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*uart_tx = *text++;
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len--;
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}
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*/
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}
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