mirror of
https://github.com/CTCaer/hekate
synced 2024-07-01 05:53:29 +00:00
b674624ad0
usage: `isleep(ILOOP(instructions))` Each loop is 3 cycles, or approximately 7.35ns on 408MHz CPU clock.
121 lines
3.1 KiB
C
121 lines
3.1 KiB
C
/*
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* Timer/Watchdog driver for Tegra X1
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*
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* Copyright (c) 2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <soc/bpmp.h>
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#include <soc/irq.h>
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#include <soc/timer.h>
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#include <soc/t210.h>
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#include <utils/types.h>
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#define EXCP_TYPE_ADDR 0x4003FFF8
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#define EXCP_TYPE_WDT 0x544457 // "WDT".
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u32 get_tmr_s()
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{
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(void)RTC(APBDEV_RTC_MILLI_SECONDS);
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return (u32)RTC(APBDEV_RTC_SECONDS);
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}
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u32 get_tmr_ms()
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{
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// The registers must be read with the following order:
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// RTC_MILLI_SECONDS (0x10) -> RTC_SHADOW_SECONDS (0xC)
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return (u32)(RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000));
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}
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u32 get_tmr_us()
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{
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return (u32)TMR(TIMERUS_CNTR_1US);
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}
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void msleep(u32 ms)
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{
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#ifdef USE_RTC_TIMER
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u32 start = (u32)RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000);
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// Casting to u32 is important!
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while (((u32)(RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000)) - start) <= ms)
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;
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#else
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bpmp_msleep(ms);
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#endif
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}
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void usleep(u32 us)
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{
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#ifdef USE_RTC_TIMER
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u32 start = (u32)TMR(TIMERUS_CNTR_1US);
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// Check if timer is at upper limits and use BPMP sleep so it doesn't wake up immediately.
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if ((start + us) < start)
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bpmp_usleep(us);
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else
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while ((u32)(TMR(TIMERUS_CNTR_1US) - start) <= us) // Casting to u32 is important!
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;
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#else
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bpmp_usleep(us);
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#endif
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}
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// Instruction wait loop. Each loop is 3 cycles (SUBS+BGT). Usage: isleep(ILOOP(instr)). Base 408MHz: 7.35ns.
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void __attribute__((target("arm"))) isleep(u32 is)
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{
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asm volatile( "0:" "SUBS %[is_cnt], #1;" "BGT 0b;" : [is_cnt] "+r" (is));
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}
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void timer_usleep(u32 us)
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{
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TMR(TIMER_TMR8_TMR_PTV) = TIMER_EN | us;
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irq_wait_event(IRQ_TMR8);
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TMR(TIMER_TMR8_TMR_PCR) = TIMER_INTR_CLR;
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}
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void watchdog_start(u32 us, u32 mode)
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{
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// WDT4 is for BPMP.
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TMR(TIMER_WDT4_UNLOCK_PATTERN) = TIMER_MAGIC_PTRN;
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TMR(TIMER_TMR9_TMR_PTV) = TIMER_EN | TIMER_PER_EN | us;
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TMR(TIMER_WDT4_CONFIG) = TIMER_SRC(9) | TIMER_PER(1) | mode;
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TMR(TIMER_WDT4_COMMAND) = TIMER_START_CNT;
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}
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void watchdog_end()
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{
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// WDT4 is for BPMP.
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TMR(TIMER_TMR9_TMR_PTV) = 0;
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TMR(TIMER_WDT4_UNLOCK_PATTERN) = TIMER_MAGIC_PTRN;
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TMR(TIMER_WDT4_COMMAND) = TIMER_START_CNT; // Re-arm to clear any interrupts.
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TMR(TIMER_WDT4_COMMAND) = TIMER_CNT_DISABLE;
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TMR(TIMER_TMR9_TMR_PCR) = TIMER_INTR_CLR;
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}
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void watchdog_handle()
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{
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// Disable watchdog and clear its interrupts.
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watchdog_end();
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// Set watchdog magic.
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*(u32 *)EXCP_TYPE_ADDR = EXCP_TYPE_WDT;
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}
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bool watchdog_fired()
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{
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// Return if watchdog got fired. User handles clearing.
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return (*(u32 *)EXCP_TYPE_ADDR == EXCP_TYPE_WDT);
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} |