CTCaer
faf5651607
minerva: more accurate clock tree delays
...
Additionally, do not restore source DPD ctrl when switching frequencies or training is not needed.
2021-04-11 09:50:06 +03:00
CTCaer
8ce5d55eb8
mtc: Confine RAM OC completely inside minerva
...
Enabling OVERCLOCK_FREQ takes care of everything without the need of changing minerva caller.
2021-01-03 14:37:39 +02:00
CTCaer
afb749560a
mtc: Fix temperature deltas for clk tree delays when negative
2021-01-03 14:35:21 +02:00
CTCaer
7a66e0298a
mtc: Refactor various types
2021-01-03 14:33:56 +02:00
CTCaer
dfcdb2e1e6
mtc: Update minerva to simplify some logic
2020-12-26 17:28:49 +02:00
CTCaer
d37fe213d7
mtc: Name sdram ids
2020-06-14 17:39:39 +03:00
CTCaer
6e256d29c7
Utilize hekate's BDK for hekate main and Nyx
2020-06-14 16:45:45 +03:00
CTCaer
84328aa676
minerva: Make use of new minerva
...
- Training and switch is now faster
- Compatibility checks: New Minerva does not allow old binaries. New binaries do not allow old Minerva
- MTC table is now in a safe region
- Periodic training period increased to every 250ms
2019-12-04 21:56:45 +02:00
CTCaer
66c4f30bdf
minerva: Update to v1.2 and use only integers
...
Additionally remove support for DRAM types that Switch platform does not have.
This will reduce periodic training cost to 30us from 6ms.
2019-12-04 21:46:33 +02:00
Kostas Missos
7c42f72b8a
refactor: Remove all unwanted whitespace
2019-10-18 18:02:06 +03:00
ctcaer@gmail.com
52478833de
[MTC] Utilize Minerva Training Cell
2019-06-30 03:49:33 +03:00
Kostas Missos
cfef8b4f72
Update libminerva to v1.1
2018-11-10 13:30:17 +02:00
Kostas Missos
ec1bb508b3
Fix minerva build
...
This is still for testing it out.
The real usage will come later.
2018-11-05 10:54:31 +02:00
Kostas Missos
cae9044c17
Minerva our DRAM trainer
...
Supports up to 1600MHz and periodic training.
For more check here: https://github.com/CTCaer/minerva_tc
2018-11-04 03:15:32 +02:00
