Commit graph

19 commits

Author SHA1 Message Date
CTCaer b37430dc1d bdk: update copyright year 2024-01-07 12:38:10 +02:00
CTCaer eff27d92f2 bdk: sdram: update default wpr overrides
Since it's only used in L4T set them to the correct latest reg tool values.

HOS overrides them anyway.
2024-01-06 22:03:54 +02:00
CTCaer 74e252aaf2 bdk: sdram: update latest reg tool vpr overrides
Set them to default config and remove them from patching.
2024-01-06 21:58:51 +02:00
CTCaer a6ec41744b bdk: sdram: refactor patching offsets 2023-12-27 21:04:04 +02:00
CTCaer 913cdee8e8 bdk: sdram: rename 3rd gen t210b01 hynix ram
Confirmed to be a Hynix H54G46CYRBX267 and not a H9HCNNNBKMMLXR-NEI
2023-12-25 03:02:11 +02:00
CTCaer d73a3fdd7c bdk: sdram: name 1a micron ram chips
Again, as with 3rd gen samsung and hynix, that's an educated guess.
2023-08-22 14:44:27 +03:00
CTCaer b9bc35a22e bdk: dram: correct old comments 2023-07-21 18:39:46 +03:00
CTCaer 7d3663616e bdk: sdram: name 2 of the new ram chips
Not actually validated, but educated guess, since all previous one were correct in the end.
New Micron still unknown, can be guessed but model doesn't exist in any public list.
2023-06-08 02:52:03 +03:00
CTCaer 560f077196 bdk: sdram: rename new dram chips 2022-12-19 05:25:26 +02:00
CTCaer 2ea595e98d bdk: sdram: add new dram ids/configs
On T210B01 dram ids 7 and 16 got removed.
29 to 34 were added.

Additionally, remove all deprecated and unused dram id enums.
2022-10-11 10:38:43 +03:00
CTCaer b0c0a86108 bdk: migrate timers/sleeps to timer driver 2022-06-27 10:22:19 +03:00
CTCaer 37de367fef bdk: sdram: deduplicate dram configs
Additionally add info about new hynix chip and correct ids 3 and 5 on T210B01 based Switch.
2022-05-08 04:58:36 +03:00
CTCaer 83c95d8a3b bdk: sdram: update 20/21/22 ids for new dram
Dram chip is Samsung 4GB built on 1z-nm that allows for 40% lower power usage.
2022-03-23 02:20:55 +02:00
CTCaer 981c986b3f bdk: sdram: name the new micron modules 2021-10-19 09:13:14 +03:00
CTCaer 03d027615c sdram: update config for t210b01 (unused) 2021-09-17 23:09:33 +03:00
CTCaer 70a06a6cae sdram: add support for missing new dram ids
In preparation of dram chip shortages, add missing new ids that are now confirmed that they will be in mass usage
2021-08-28 16:56:49 +03:00
CTCaer f4696da0ef sdram: Update names for Aula 2021-01-04 02:45:32 +02:00
CTCaer cf1f94662c sdram: Correct some dram names 2020-12-02 22:26:06 +02:00
CTCaer 29dc122dd4 sdram: Add T210B01 support & new LPDDR4X tables 2020-06-26 18:53:12 +03:00