Commit graph

15 commits

Author SHA1 Message Date
CTCaer db214f2865 l4t: correct debug print 2023-12-25 04:09:46 +02:00
CTCaer 7040f1ada2 l4t: allow setting dram voltage even if no OC
Mostly for allowing undervolting.
2023-10-12 07:44:00 +03:00
CTCaer 0fe17cfb41 l4t: add latest api version info 2023-07-28 15:42:16 +03:00
CTCaer cb964fe5d2 l4t: allow ram undervolting 2023-07-28 04:04:03 +03:00
CTCaer 010b08d4c7 l4t: t210b01: set real dram rate by default
Since Arachne Register Cell (ARC) is now final and stable,
automatically set rated DRAM frequency for T210B01 by default.
1866 MHz for old ones and 2133 MHz for newer ones.

Setting anything from 1600000 and lower will disable that.
2023-07-28 04:03:01 +03:00
CTCaer 66e5e128f6 l4t: adjust revision amidst the new changes
Also add helpful message if files are missing.
2023-06-09 10:56:39 +03:00
CTCaer 84822726cb l4t: add fine tuned voltage support for DRAM
1000-1175mV for T210 VDDIO/Q via `ram_oc_vdd2`
1000-1175mV for T210B01 VDDIO and 600-650mV for VDDQ via `ram_oc_vdd2` and `ram_oc_vddq`.
2023-06-09 10:55:32 +03:00
CTCaer b6e1e0d412 l4t: add bpmp-fw support for T210 2023-06-09 10:53:03 +03:00
CTCaer 496737248c l4t: there was never a need to normalize dram freq 2023-06-09 10:51:31 +03:00
CTCaer 4f52e1f24a l4t: refactor bpmp-fw defines for T210B01 2023-06-09 10:50:29 +03:00
CTCaer dd380d4d47 l4t: increase bw priority to SDMMC1 for L4T 2023-04-06 17:34:26 +03:00
CTCaer 5193416658 hekate/nyx: stylistic corrections 2023-02-11 23:51:43 +02:00
CTCaer 361aaf8629 l4t: disable AHB aperture and pllc war
We don't need AHB aperture after that point and new deinit fixes the pllc init issue on L4T boot.
2023-02-11 23:25:22 +02:00
CTCaer 1666daf447 l4t: fix several issues
- Fixed an issue where cached data would not be flushed after setting the fw carveout. Now they are flushed before setting it.
- Fixed and off-by-one bug and setting incorrect number of mtc entries.
2022-12-22 12:37:56 +02:00
CTCaer a2a302b9d5 l4t: Add L4T loader for T210 and T210B01 2022-12-20 17:00:33 +02:00