CTCaer
4576ed81ef
sdram: acquire per chip mrr info
2024-02-12 04:08:39 +02:00
CTCaer
2cc6cd45d9
bdk: dram: small refactor
2023-12-27 21:06:09 +02:00
CTCaer
a6ec41744b
bdk: sdram: refactor patching offsets
2023-12-27 21:04:04 +02:00
CTCaer
913cdee8e8
bdk: sdram: rename 3rd gen t210b01 hynix ram
...
Confirmed to be a Hynix H54G46CYRBX267 and not a H9HCNNNBKMMLXR-NEI
2023-12-25 03:02:11 +02:00
CTCaer
d73a3fdd7c
bdk: sdram: name 1a micron ram chips
...
Again, as with 3rd gen samsung and hynix, that's an educated guess.
2023-08-22 14:44:27 +03:00
CTCaer
7d3663616e
bdk: sdram: name 2 of the new ram chips
...
Not actually validated, but educated guess, since all previous one were correct in the end.
New Micron still unknown, can be guessed but model doesn't exist in any public list.
2023-06-08 02:52:03 +03:00
CTCaer
9a98c1afb9
bdk: stylistic corrections
...
And update copyrights
2023-02-11 23:46:38 +02:00
CTCaer
4e15e034b8
bdk: sdram: remove (lp)ddr2/3 support
2023-02-11 22:44:31 +02:00
CTCaer
560f077196
bdk: sdram: rename new dram chips
2022-12-19 05:25:26 +02:00
CTCaer
2ea595e98d
bdk: sdram: add new dram ids/configs
...
On T210B01 dram ids 7 and 16 got removed.
29 to 34 were added.
Additionally, remove all deprecated and unused dram id enums.
2022-10-11 10:38:43 +03:00
CTCaer
c52c11e7bc
bdk: mem: improve emc MRR reading
2022-10-11 03:51:12 +03:00
CTCaer
70523e404f
bdk: whitespace refactor
2022-07-11 22:10:11 +03:00
CTCaer
b0c0a86108
bdk: migrate timers/sleeps to timer driver
2022-06-27 10:22:19 +03:00
CTCaer
37de367fef
bdk: sdram: deduplicate dram configs
...
Additionally add info about new hynix chip and correct ids 3 and 5 on T210B01 based Switch.
2022-05-08 04:58:36 +03:00
CTCaer
83c95d8a3b
bdk: sdram: update 20/21/22 ids for new dram
...
Dram chip is Samsung 4GB built on 1z-nm that allows for 40% lower power usage.
2022-03-23 02:20:55 +02:00
CTCaer
981c986b3f
bdk: sdram: name the new micron modules
2021-10-19 09:13:14 +03:00
CTCaer
70a06a6cae
sdram: add support for missing new dram ids
...
In preparation of dram chip shortages, add missing new ids that are now confirmed that they will be in mass usage
2021-08-28 16:56:49 +03:00
CTCaer
f4696da0ef
sdram: Update names for Aula
2021-01-04 02:45:32 +02:00
CTCaer
745ac609d2
max7762x: Update everything to use the improved pmic management
2021-01-04 02:41:15 +02:00
CTCaer
2628044ba8
fuse: Move more parsing into its specific object
2020-12-26 16:34:12 +02:00
CTCaer
cf1f94662c
sdram: Correct some dram names
2020-12-02 22:26:06 +02:00
CTCaer
29dc122dd4
sdram: Add T210B01 support & new LPDDR4X tables
2020-06-26 18:53:12 +03:00
CTCaer
cabaa6cfb8
Utilize BIT macro everywhere
2020-11-26 01:41:45 +02:00
CTCaer
669e42960c
Utilize ARRAY_SIZE macro
2020-11-15 13:56:45 +02:00
CTCaer
68d57861cd
Add missing guard from some macros
...
Guard them for future usage, as none of these macros had a non-preset variable used with them yet.
2020-11-15 13:39:27 +02:00
CTCaer
485edb4883
emc: Rename Device to Rank
2020-11-15 13:23:37 +02:00
CTCaer
e158d9bc00
clk: Refactor CLK devices bits
2020-07-17 16:50:17 +03:00
CTCaer
6e256d29c7
Utilize hekate's BDK for hekate main and Nyx
2020-06-14 16:45:45 +03:00
CTCaer
185526d134
Introducing Bootloader Development Kit (BDK)
...
BDK will allow developers to use the full collection of drivers,
with limited editing, if any, for making payloads for Nintendo Switch.
Using a single source for everything will also help decoupling
Switch specific code and easily port it to other Tegra X1/X1+ platforms.
And maybe even to lower targets.
Everything is now centrilized into bdk folder.
Every module or project can utilize it by simply including it.
This is just the start and it will continue to improve.
2020-06-14 15:25:21 +03:00
