Commit graph

1684 commits

Author SHA1 Message Date
CTCaer
066efda4cd lib: minerva: normalize output frequency
Allow frequencies that are not exact to receive proper dividers from the supported ones from table.
2023-06-08 04:56:14 +03:00
CTCaer
d8d15bde44 lib: minerva: add Samsung 8GB support
And remove frequencies smaller than deep sleep frequency from the tables.
2023-06-08 04:50:59 +03:00
CTCaer
9d8ebc7e38 lib: minerva: refactor table
Remove _idx used initially for RE at last.
2023-06-08 04:49:16 +03:00
CTCaer
c2ee6be2f5 bdk: sdram: add Samsung 8GB RAM support for T210
And remove Copper support completely.
2023-06-08 04:16:51 +03:00
CTCaer
73a133556d bdk: sdram: correct sku related info
Validated so rename accordingly.
2023-06-08 02:57:30 +03:00
CTCaer
7d3663616e bdk: sdram: name 2 of the new ram chips
Not actually validated, but educated guess, since all previous one were correct in the end.
New Micron still unknown, can be guessed but model doesn't exist in any public list.
2023-06-08 02:52:03 +03:00
CTCaer
e76aebabba bdk: mem: minerva: check table size in clock check
Don't hardcode table size to 10.
2023-06-08 02:45:34 +03:00
CTCaer
bc0eea11f3 bdk: joycon: add calibration struct 2023-06-08 02:44:35 +03:00
CTCaer
937ab52d14 Bump hekate to v6.0.4 2023-05-09 11:15:34 +03:00
CTCaer
e896d388ab hos: 16.0.3 support 2023-05-09 11:15:11 +03:00
CTCaer
ded959c449 Bump hekate to v6.0.3 and Nyx to v1.5.3 2023-04-06 17:38:36 +03:00
CTCaer
a7fd83c793 nyx: correct build flag 2023-04-06 17:36:22 +03:00
CTCaer
dd380d4d47 l4t: increase bw priority to SDMMC1 for L4T 2023-04-06 17:34:26 +03:00
CTCaer
795b4ad26e bdk: sdmmc: increase bw priority to SDMMC1 for L4T 2023-04-06 17:30:01 +03:00
CTCaer
bb10b8aea3 bdk: sdmmc: small refactor 2023-04-06 10:19:53 +03:00
CTCaer
811fa4c88b bdk: sdmmc: add SD registers debug printing
Can be enabled with `SDMMC_DEBUG_PRINT_SD_REGS`
2023-04-06 10:13:35 +03:00
CTCaer
22462e4bf3 nyx: info: optimize random benchmarking
Do not allow SD/eMMC to breath during random reads benchmarking. So only render progress at 15fps.
2023-03-31 09:24:55 +03:00
CTCaer
ca0263fa8c hekate: info: fully deinit/unmount sd card 2023-03-31 09:17:51 +03:00
CTCaer
b1112e0949 hos: set proper exo hos version for 12.1.0
Even if 12.0.0 one is api compatible, there was a master key change on 12.1.0.
2023-03-31 09:17:13 +03:00
CTCaer
3c3fcb29f9 hekate: clear rtc interrupt and stop alarm
Stopping rtc alarm is now done in the function that actually checks it, in order to avoid power offs from HOS if it's fired and user wants to continue booting.

Additionally, clear the interrupt which is the actual thing that is checked by HOS.
2023-03-31 09:15:56 +03:00
CTCaer
8528e6a08a bdk: util: do not edit rtc alarm in power function 2023-03-31 09:12:58 +03:00
CTCaer
27ae312227 bdk: minor naming edits 2023-03-31 09:11:55 +03:00
CTCaer
50811aacfa bdk: touch: reorder power on
So touch IC reset can be properly done on a fast power cycle.
2023-03-31 09:08:20 +03:00
CTCaer
f4bf48e76a bdk: sdmmc: add driver type set support 2023-03-31 09:04:10 +03:00
CTCaer
d258c82d52 bdk: sdmmc: add UHS DDR200 support
The bdk flag BDK_SDMMC_UHS_DDR200_SUPPORT can be used to enable it.

SD Card DDR200 (DDR208) support

Proper procedure:
1. Check that Vendor Specific Command System is supported.
   Used as Enable DDR200 Bus.
2. Enable DDR200 bus mode via setting 14 to Group 2 via CMD6.
   Access Mode group is left to default 0 (SDR12).
3. Setup clock to 200 or 208 MHz.
4. Set host to DDR bus mode that supports such high clocks.
   Some hosts have special mode, others use DDR50 and others HS400.
5. Execute Tuning.

The true validation that this value in Group 2 activates it, is that DDR50 bus
and clocks/timings work fully after that point.

On Tegra X1, that can be done with DDR50 host mode.
Tuning though can't be done automatically on any DDR mode.
So it needs to be done manually and selected tap will be applied from the
biggest sampling window.

Finally, all that simply works, because the marketing materials for DDR200 are
basically overstatements to sell the feature. DDR200 is simply SDR104 in DDR mode,
so sampling on rising and falling edge and with variable output data window.
It can be supported by any host that is fast enough to support DDR at 200/208MHz
and can do hw/sw tuning for finding the proper sampling window in that mode.

Using a SDMMC controller on DDR200 mode at 400MHz, has latency allowance implications. The MC/EMC must be clocked enough to be able to serve the requests in time (512B in 1.28 ns).
2023-03-31 08:54:13 +03:00
CTCaer
7f32c6d211 bdk: sd: better removal detection handling 2023-03-31 08:31:20 +03:00
CTCaer
2f7e841b50 bdk: sdmmc: move sdr12 setup for better readability 2023-03-31 08:29:20 +03:00
CTCaer
29e32f09fb bdk: sdmmc: properly identify sdmmc1 clk config
Remove schmitt trigger config from clock pin on sdmmc1 for identifying previous pinmuxing state.
2023-03-31 08:27:48 +03:00
CTCaer
b123571c56 bdk: sdmmc: only allow power raise if SDR50 and up
As per spec.
2023-03-31 08:26:19 +03:00
CTCaer
b7164a629f bdk: sdmmc: allow max power limit to be set
Even if it defaults to 1.44W.
Some cards' firmware maybe be bugged.

The 3.3V regulator on all SKUs allow more than 800mA current anyway.
2023-03-31 08:24:52 +03:00
CTCaer
25be98b7e3 bdk: sdmmc: add UHS DDR50 support
But disable it by default in the auto selection.
2023-03-31 08:23:10 +03:00
CTCaer
76a5facbc3 bdk: clock: rename clock_t to clk_rst_t
To avoid redefines when standard math header is used.
2023-03-31 08:18:45 +03:00
CTCaer
502fc1ed50 bdk: sdmmc: rename ddr100 to the actual HS100 name 2023-03-31 08:15:40 +03:00
CTCaer
5e134ed54b bdk: sdmmc: refactor defines 2023-03-31 08:00:14 +03:00
CTCaer
4cfe5f241e bdk: sdmmc: remove eMMC OC
Additionally, the flag BDK_SDMMC_OC_AND_EXTRA_PRINT is now just BDK_SDMMC_EXTRA_PRINT
2023-03-31 07:55:17 +03:00
CTCaer
9a222e0e49 bdk: sdmmc: rename divisor param to card clock 2023-03-31 07:53:46 +03:00
CTCaer
298893f404 bdk: sdmmc: remove powersave arg from sdmmc init 2023-03-31 07:51:43 +03:00
CTCaer
1ce5bb10f8 bdk: sdmmc: refactor debug prints 2023-03-31 07:49:26 +03:00
CTCaer
107fbd1d24 bdk: gpio: add debounce set function
The debounce time is not per pin but per bank. So software should manage proper time for sibling pins
2023-03-31 07:43:16 +03:00
CTCaer
1edb6583ac bdk: gpio: reorder gpio config
Since there are some bootloaders that mess with the states of some power gpios, reorder gpio configuration for input/output in order to prevent power pin glitches.
2023-03-31 07:41:50 +03:00
CTCaer
5bdf323e5c Bump hekate to v6.0.2 and Nyx to v1.5.2 2023-02-23 01:25:19 +02:00
CTCaer
d286ee4e9d bdk: sd: only clear inserted when requested
Also rename var to further explain its usage
2023-02-23 01:25:05 +02:00
CTCaer
17cdd5af0d bdk: hwdeinit: restore order of bpmp clock set
Restore order of bpmp clock scale down in deinit, in order to decrease pressure on clock deinits.
2023-02-22 14:48:43 +02:00
CTCaer
26fa363ca4 nyx: reset SD speed to SDR104 if init fails 2023-02-22 13:46:50 +02:00
CTCaer
2e8bfc1f56 hos: add 16.0.0 support 2023-02-22 13:45:46 +02:00
CTCaer
07dafe8185 nyx: fix pkg1 dump/split
Broken since v5.3.1.
2023-02-22 13:24:49 +02:00
CTCaer
7f92f65c26 fatfs/nyx: set minimum year to 2023 2023-02-22 13:23:40 +02:00
CTCaer
55e01ca735 bdk: sd: improve init error handling
- Management of sd init done is now on sd init retry function
 Also manages inserted, since it can set the sd init done to false if failed
- Init will now always check if SD is also initialized, since it doesn't manage it anymore. Because of that, mounting is no longer forced, but checked first.
- Unmount/End will now always set the sd as unmounted, since no data residue is expected after the fact

The above will improve handling of faulty SD cards or faulty SD readers.
2023-02-22 13:19:12 +02:00
CTCaer
a44a4881d4 hekate/nyx: stylistic and copyright updates 2023-02-22 13:04:42 +02:00
CTCaer
c279fa2521 bdk: max77621: ckkadv is basically an enum 2023-02-22 13:00:36 +02:00