nold/hekate
1
0
Fork 0
mirror of https://github.com/CTCaer/hekate synced 2024-07-05 16:03:29 +00:00
Code Issues Packages Projects Releases Wiki Activity
677 commits 2 branches 74 tags 6.5 MiB
Commit graph

23 commits

Author SHA1 Message Date
CTCaer 185526d134 Introducing Bootloader Development Kit (BDK) 
BDK will allow developers to use the full collection of drivers,
with limited editing, if any, for making payloads for Nintendo Switch.

Using a single source for everything will also help decoupling
Switch specific code and easily port it to other Tegra X1/X1+ platforms.
And maybe even to lower targets.

Everything is now centrilized into bdk folder.
Every module or project can utilize it by simply including it.

This is just the start and it will continue to improve.
 2020-06-14 15:25:21 +03:00
CTCaer 1d3d1c8454 clock: Prevent PLLC4 from glitching 2020-06-14 13:19:53 +03:00
CTCaer 7dd3178d48 Equalize hekate main and Nyx common functions 2020-06-13 18:16:29 +03:00
CTCaer 63768ccc99 uart: Add rounded clocking for 1 mbaud 2020-04-30 03:34:05 +03:00
CTCaer 51985ed2ca sdmmc v2: Bus/IO clock refactoring and fixes 
Use the exact same clocks with HOS and utilize low jitter clock parents.

Add back our compatibility mode and the missing timeout clock parent.

Hekate main will continue to use PLLP clock parent for all.
 2020-04-30 01:26:55 +03:00
CTCaer f5040f1e41 Update and add missing copyrights 
Probably more need to change.
 2020-03-14 09:24:24 +02:00
CTCaer 03a8a11933 Small fixes and changes 
- Allow printing of more log on HOS boot when LOGS are OFF.
- A small name refactoring
- Add battery warning symbol when battery < 3200mV
 2020-03-03 04:11:13 +02:00
CTCaer c99a87dd09 clock: Move PLLC config from bpmp.c to clock.c 2020-01-07 06:46:22 +02:00
CTCaer dd8ec0d28b clock: Always wait 2us before deasserting reset 2019-12-04 21:32:51 +02:00
CTCaer 0b1eebefe1 Small refactor and bugfixes 2019-12-04 21:31:39 +02:00
CTCaer a8d529cf6a Refactoring and comment adding 2019-09-12 23:08:38 +03:00
Kostas Missos 718e502983 Add more register names + refactoring 2019-09-09 16:56:37 +03:00
ctcaer@gmail.com 8101fd3f7f Various bugfixes 2019-06-30 03:15:46 +03:00
ctcaer@gmail.com 91606334c4 [sdmmc] Revert 204MHz sd device clock 
Again some Sandisk U1 cards do not behave at all at speeds like that (204MHz / 102MB/s).

Revert back to 163.2MHz / 81.6MB/s.
 2019-04-23 03:34:39 +03:00
ctcaer@gmail.com 8eb5ee867d [GFX] Finish ctxt global usage 
Plus:
- Some whitespace fixes
- Allow UHS bus to reach max 102MB/s from 81.6MB/s
 2019-04-21 17:33:39 +03:00
ctcaer@gmail.com 5ba4848571 Various bugfixes 
- Add error msg for what fails in a particular ini boot entry
- Fix wrongly defined s8 type
- Change raw fuse dump to correct size
 2019-04-14 02:19:04 +03:00
Kostas Missos 4ae42c3a9d Small fixes and whitespace 
Additionally make info functions smaller and show available fuses.
 2019-02-12 00:34:35 +02:00
Kostas Missos 22e179d1cf Add 6.2.0 support to tools 
- Print TSEC info
- Dump pkg1/2
 2018-12-02 11:11:07 +02:00
Kostas Missos 4eb5b5f91b Name more hardcoded regs/vals 2018-11-10 14:11:42 +02:00
Kostas Missos 67a470921a Add PWM backlight support + options 
- No eye blasting backlight
- Option to choose the prefered brightness
- Smooths transitions
 2018-09-19 00:01:42 +03:00
Kostas Missos fdd94ffd2b General bugfixes + hardcoded name replacement 2018-09-18 23:38:54 +03:00
Kostas Missos 382f727be3 Fix all the bugs 
- Mem leaks
- Stack corruption
- Div by 0
- Double frees
 2018-08-23 04:37:02 +03:00
Kostas Missos e5abdd938e Refactor ALL the things + enable LTO 2018-08-13 11:58:24 +03:00
Renamed from ipl/clock.c (Browse further)