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https://github.com/CTCaer/hekate
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memory map: Repartition RAM based on new needs
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parent
2dd474ad26
commit
5ca35aa4fc
2 changed files with 44 additions and 38 deletions
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@ -28,60 +28,66 @@
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/* --- DRAM START --- */
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/* --- DRAM START --- */
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#define DRAM_START 0x80000000
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#define DRAM_START 0x80000000
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/* Do not write anything in this area */
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#define HOS_RSVD 0x1000000 // Do not write anything in this area.
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#define NYX_LOAD_ADDR 0x81000000
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#define NYX_SZ_MAX 0x1000000
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/* Stack theoretical max: 220MB */
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#define IPL_STACK_TOP 0x90010000
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#define IPL_HEAP_START 0x90020000
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#define IPL_HEAP_SZ 0x24FE0000 // 592MB.
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/* --- Gap: 0xB5000000 - 0xB5FFFFFF --- */
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// SDMMC DMA buffers
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#define NYX_LOAD_ADDR 0x81000000
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#define SDXC_BUF_ALIGNED 0xB6000000
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#define NYX_SZ_MAX 0x1000000 // 16MB
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#define MIXD_BUF_ALIGNED 0xB7000000
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/* --- Gap: 0x82000000 - 0x82FFFFFF --- */
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#define EMMC_BUF_ALIGNED MIXD_BUF_ALIGNED
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#define SDMMC_DMA_BUF_SZ 0x1000000 // 16MB (4MB currently used).
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/* Stack theoretical max: 33MB */
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#define SDMMC_UPPER_BUFFER 0xB8000000
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#define IPL_STACK_TOP 0x83100000
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#define SDMMC_UP_BUF_SZ 0x8000000 // 128MB.
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#define IPL_HEAP_START 0x84000000
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#define IPL_HEAP_SZ 0x20000000 // 512MB.
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/* --- Gap: 1040MB 0xA4000000 - 0xE4FFFFFF --- */
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// Virtual disk / Chainloader buffers.
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// Virtual disk / Chainloader buffers.
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#define RAM_DISK_ADDR 0xC1000000
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#define RAM_DISK_ADDR 0xA4000000
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#define RAM_DISK_SZ 0x20000000
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#define RAM_DISK_SZ 0x41000000 // 1040MB.
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//#define DRAM_LIB_ADDR 0xE0000000
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//#define DRAM_LIB_ADDR 0xE0000000
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/* --- Chnldr: 252MB 0xC03C0000 - 0xCFFFFFFF --- */ //! Only used when chainloading.
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/* --- Chnldr: 252MB 0xC03C0000 - 0xCFFFFFFF --- */ //! Only used when chainloading.
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/* --- Gap: 464MB 0xD0000000 - 0xECFFFFFF --- */
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// SDMMC DMA buffers 1
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#define SDMMC_UPPER_BUFFER 0xE5000000
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#define SDMMC_UP_BUF_SZ 0x8000000 // 128MB.
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// Nyx buffers.
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// Nyx buffers.
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#define NYX_STORAGE_ADDR 0xED000000
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#define NYX_STORAGE_ADDR 0xED000000
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#define NYX_RES_ADDR 0xEE000000
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#define NYX_RES_ADDR 0xEE000000
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#define NYX_RES_SZ 0x1000000 // 16MB.
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// Framebuffer addresses.
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// SDMMC DMA buffers 2
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#define IPL_FB_ADDRESS 0xF0000000
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#define SDXC_BUF_ALIGNED 0xEF000000
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#define IPL_FB_SZ 0x384000 // 720 x 1280 x 4.
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#define MIXD_BUF_ALIGNED 0xF0000000
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#define LOG_FB_ADDRESS 0xF0400000
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#define EMMC_BUF_ALIGNED MIXD_BUF_ALIGNED
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#define LOG_FB_SZ 0x334000 // 1280 x 656 x 4.
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#define SDMMC_DMA_BUF_SZ 0x1000000 // 16MB (4MB currently used).
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#define NYX_FB_ADDRESS 0xF0800000
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#define NYX_FB_SZ 0x384000 // 1280 x 720 x 4.
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// Nyx LvGL buffers.
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// Nyx LvGL buffers.
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#define NYX_LV_VDB_ADR 0xF0C00000
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#define NYX_LV_VDB_ADR 0xF1000000
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#define NYX_FB_SZ 0x384000 // 1280 x 720 x 4.
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#define NYX_FB_SZ 0x384000 // 1280 x 720 x 4.
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#define NYX_LV_MEM_ADR 0xF1000000
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#define NYX_LV_MEM_ADR 0xF1400000
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#define NYX_LV_MEM_SZ 0x8000000
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#define NYX_LV_MEM_SZ 0x6600000 // 70MB.
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// Framebuffer addresses.
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#define IPL_FB_ADDRESS 0xF5A00000
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#define IPL_FB_SZ 0x384000 // 720 x 1280 x 4.
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#define LOG_FB_ADDRESS 0xF5E00000
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#define LOG_FB_SZ 0x334000 // 1280 x 656 x 4.
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#define NYX_FB_ADDRESS 0xF6200000
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#define NYX_FB2_ADDRESS 0xF6600000
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#define NYX_FB_SZ 0x384000 // 1280 x 720 x 4.
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#define DRAM_MEM_HOLE_ADR 0xF6A00000
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#define DRAM_MEM_HOLE_SZ 0x8140000
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/* --- Hole: 129MB 0xF6A00000 - 0xFEB3FFFF --- */
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#define DRAM_START2 0xFEB40000
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// NX BIS driver sector cache.
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// NX BIS driver sector cache.
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#define NX_BIS_CACHE_ADDR 0xF9000000
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#define NX_BIS_CACHE_ADDR 0xFEE00000
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#define NX_BIS_CACHE_SZ 0x8800
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#define NX_BIS_CACHE_SZ 0x8800
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/* --- Gap: 111MB 0xF9008800 - 0xFFFFFFFF --- */
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// #define EXT_PAYLOAD_ADDR 0xC03C0000
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// #define RCM_PAYLOAD_ADDR (EXT_PAYLOAD_ADDR + ALIGN(PATCHED_RELOC_SZ, 0x10))
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// #define COREBOOT_ADDR (0xD0000000 - 0x100000)
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// NYX
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// #define EXT_PAYLOAD_ADDR 0xC0000000
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// #define EXT_PAYLOAD_ADDR 0xC0000000
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// #define RCM_PAYLOAD_ADDR (EXT_PAYLOAD_ADDR + ALIGN(PATCHED_RELOC_SZ, 0x10))
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// #define RCM_PAYLOAD_ADDR (EXT_PAYLOAD_ADDR + ALIGN(PATCHED_RELOC_SZ, 0x10))
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// #define COREBOOT_ADDR (0xD0000000 - 0x100000)
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// #define COREBOOT_ADDR (0xD0000000 - rom_size)
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#endif
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#endif
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@ -60,8 +60,8 @@ _reloc_ipl:
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BX R3
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BX R3
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_real_start:
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_real_start:
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/* Initially, we place our stack in IRAM but will move it to SDRAM later. */
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/* We place our stack in SDRAM. */
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LDR SP, =0x90010000
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LDR SP, =0x83100000
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LDR R0, =__bss_start
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LDR R0, =__bss_start
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EOR R1, R1, R1
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EOR R1, R1, R1
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LDR R2, =__bss_end
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LDR R2, =__bss_end
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