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https://github.com/CTCaer/hekate
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Update Clocks and Fuses for USB
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CTCaer
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2261dbce83
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4 changed files with 44 additions and 0 deletions
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@ -43,6 +43,12 @@
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#define CLK_RST_CONTROLLER_PLLM_MISC1 0x98
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#define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C
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#define CLK_RST_CONTROLLER_PLLP_BASE 0xA0
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#define CLK_RST_CONTROLLER_PLLA_BASE 0xB0
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#define CLK_RST_CONTROLLER_PLLA_OUT 0xB4
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#define CLK_RST_CONTROLLER_PLLA_MISC1 0xB8
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#define CLK_RST_CONTROLLER_PLLA_MISC 0xBC
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#define CLK_RST_CONTROLLER_PLLU_BASE 0xC0
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#define CLK_RST_CONTROLLER_PLLU_MISC 0xCC
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#define CLK_RST_CONTROLLER_PLLD_BASE 0xD0
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#define CLK_RST_CONTROLLER_PLLD_MISC1 0xD8
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#define CLK_RST_CONTROLLER_PLLD_MISC 0xDC
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@ -52,6 +58,7 @@
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#define CLK_RST_CONTROLLER_PLLE_MISC 0xEC
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA 0xF8
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB 0xFC
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 0x100
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#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM 0x110
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 0x124
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 0x128
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 0x1BC
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD 0x1C0
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#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE 0x1D4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 0x1D8
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#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC 0x1F4
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X 0x280
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#define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284
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@ -104,20 +112,27 @@
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD 0x3A4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT 0x3B4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 0x3C4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 0x3EC
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SYS 0x400
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SE 0x42C
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#define CLK_RST_CONTROLLER_RST_DEV_V_SET 0x430
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#define CLK_RST_CONTROLLER_RST_DEV_V_CLR 0x434
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#define CLK_RST_CONTROLLER_RST_DEV_W_SET 0x438
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#define CLK_RST_CONTROLLER_RST_DEV_W_CLR 0x43C
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#define CLK_RST_CONTROLLER_CLK_ENB_V_SET 0x440
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#define CLK_RST_CONTROLLER_CLK_ENB_V_CLR 0x444
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#define CLK_RST_CONTROLLER_CLK_ENB_W_SET 0x448
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#define CLK_RST_CONTROLLER_CLK_ENB_W_CLR 0x44C
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#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET 0x450
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#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR 0x454
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#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0 0x480
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#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1 0x484
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#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2 0x488
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#define CLK_RST_CONTROLLER_PLLE_AUX 0x48C
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#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S0 0x4A0
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#define CLK_RST_CONTROLLER_PLLX_MISC_3 0x518
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#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0 0x52C
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE 0x554
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#define CLK_RST_CONTROLLER_SPARE_REG0 0x55C
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#define CLK_RST_CONTROLLER_PLLC4_BASE 0x5A4
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@ -131,6 +146,7 @@
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL 0x66C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM 0x694
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#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC 0x6A0
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#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK 0x6CC
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#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER 0x704
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE 0x710
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@ -141,6 +157,10 @@
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#define PLLCX_BASE_REF_DIS (1 << 29)
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#define PLLCX_BASE_LOCK (1 << 27)
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#define PLLA_BASE_IDDQ (1 << 25)
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#define PLLA_OUT0_CLKEN (1 << 1)
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#define PLLA_OUT0_RSTN_CLR (1 << 0)
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#define PLLC_MISC_RESET (1 << 30)
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#define PLLC_MISC1_IDDQ (1 << 27)
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#define PLLC_OUT1_CLKEN (1 << 1)
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@ -54,6 +54,7 @@
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#define FUSE_PRIVATE_KEY3 0x1B0
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#define FUSE_PRIVATE_KEY4 0x1B4
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#define FUSE_RESERVED_SW 0x1C0
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#define FUSE_USB_CALIB 0x1F0
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#define FUSE_SKU_DIRECT_CONFIG 0x1F4
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#define FUSE_OPT_VENDOR_CODE 0x200
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#define FUSE_OPT_FAB_CODE 0x204
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@ -63,6 +64,7 @@
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#define FUSE_OPT_X_COORDINATE 0x214
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#define FUSE_OPT_Y_COORDINATE 0x218
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#define FUSE_GPU_IDDQ_CALIB 0x228
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#define FUSE_USB_CALIB_EXT 0x350
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/*! Fuse commands. */
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#define FUSE_READ 0x1
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@ -43,6 +43,12 @@
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#define CLK_RST_CONTROLLER_PLLM_MISC1 0x98
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#define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C
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#define CLK_RST_CONTROLLER_PLLP_BASE 0xA0
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#define CLK_RST_CONTROLLER_PLLA_BASE 0xB0
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#define CLK_RST_CONTROLLER_PLLA_OUT 0xB4
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#define CLK_RST_CONTROLLER_PLLA_MISC1 0xB8
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#define CLK_RST_CONTROLLER_PLLA_MISC 0xBC
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#define CLK_RST_CONTROLLER_PLLU_BASE 0xC0
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#define CLK_RST_CONTROLLER_PLLU_MISC 0xCC
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#define CLK_RST_CONTROLLER_PLLD_BASE 0xD0
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#define CLK_RST_CONTROLLER_PLLD_MISC1 0xD8
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#define CLK_RST_CONTROLLER_PLLD_MISC 0xDC
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@ -52,6 +58,7 @@
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#define CLK_RST_CONTROLLER_PLLE_MISC 0xEC
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA 0xF8
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB 0xFC
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 0x100
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#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM 0x110
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 0x124
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 0x128
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@ -70,6 +77,7 @@
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 0x1BC
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD 0x1C0
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#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE 0x1D4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 0x1D8
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#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC 0x1F4
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X 0x280
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#define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284
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@ -104,20 +112,27 @@
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD 0x3A4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT 0x3B4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 0x3C4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 0x3EC
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SYS 0x400
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SE 0x42C
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#define CLK_RST_CONTROLLER_RST_DEV_V_SET 0x430
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#define CLK_RST_CONTROLLER_RST_DEV_V_CLR 0x434
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#define CLK_RST_CONTROLLER_RST_DEV_W_SET 0x438
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#define CLK_RST_CONTROLLER_RST_DEV_W_CLR 0x43C
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#define CLK_RST_CONTROLLER_CLK_ENB_V_SET 0x440
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#define CLK_RST_CONTROLLER_CLK_ENB_V_CLR 0x444
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#define CLK_RST_CONTROLLER_CLK_ENB_W_SET 0x448
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#define CLK_RST_CONTROLLER_CLK_ENB_W_CLR 0x44C
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#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET 0x450
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#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR 0x454
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#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0 0x480
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#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1 0x484
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#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2 0x488
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#define CLK_RST_CONTROLLER_PLLE_AUX 0x48C
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#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S0 0x4A0
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#define CLK_RST_CONTROLLER_PLLX_MISC_3 0x518
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#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0 0x52C
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE 0x554
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#define CLK_RST_CONTROLLER_SPARE_REG0 0x55C
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#define CLK_RST_CONTROLLER_PLLC4_BASE 0x5A4
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@ -131,6 +146,7 @@
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL 0x66C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM 0x694
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#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC 0x6A0
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#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK 0x6CC
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#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER 0x704
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE 0x710
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@ -141,6 +157,10 @@
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#define PLLCX_BASE_REF_DIS (1 << 29)
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#define PLLCX_BASE_LOCK (1 << 27)
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#define PLLA_BASE_IDDQ (1 << 25)
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#define PLLA_OUT0_CLKEN (1 << 1)
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#define PLLA_OUT0_RSTN_CLR (1 << 0)
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#define PLLC_MISC_RESET (1 << 30)
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#define PLLC_MISC1_IDDQ (1 << 27)
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#define PLLC_OUT1_CLKEN (1 << 1)
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@ -54,6 +54,7 @@
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#define FUSE_PRIVATE_KEY3 0x1B0
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#define FUSE_PRIVATE_KEY4 0x1B4
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#define FUSE_RESERVED_SW 0x1C0
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#define FUSE_USB_CALIB 0x1F0
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#define FUSE_SKU_DIRECT_CONFIG 0x1F4
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#define FUSE_OPT_VENDOR_CODE 0x200
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#define FUSE_OPT_FAB_CODE 0x204
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#define FUSE_OPT_X_COORDINATE 0x214
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#define FUSE_OPT_Y_COORDINATE 0x218
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#define FUSE_GPU_IDDQ_CALIB 0x228
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#define FUSE_USB_CALIB_EXT 0x350
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/*! Fuse commands. */
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#define FUSE_READ 0x1
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