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exo: tabs->spaces...

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This commit is contained in:
Michael Scire 2018-08-16 18:56:04 -07:00
parent f41aaccaa2
commit ee0117b59e
6 changed files with 41 additions and 41 deletions
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4
exosphere/src/arm.s
View file

@ -51,7 +51,7 @@ tlb_invalidate_page_inner_shareable:
* *
* This file is based on sample code from ARMv8 ARM. * This file is based on sample code from ARMv8 ARM.
* *
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
/* /*
@ -84,7 +84,7 @@ __asm_dcache_level:
/* x5 <- bit position of #ways */ /* x5 <- bit position of #ways */
loop_set: loop_set:
mov x6, x3 /* x6 <- working copy of #ways */ mov x6, x3 /* x6 <- working copy of #ways */
loop_way: loop_way:
lsl x7, x6, x5 lsl x7, x6, x5
orr x9, x12, x7 /* map way and level to cisw value */ orr x9, x12, x7 /* map way and level to cisw value */

6
exosphere/src/bootup.c
View file

@ -149,10 +149,10 @@ void bootup_misc_mmio(void) {
/* Clear RESET Vector, setup CPU Secure Boot RESET Vectors. */ /* Clear RESET Vector, setup CPU Secure Boot RESET Vectors. */
uint32_t reset_vec; uint32_t reset_vec;
if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500) { if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500) {
reset_vec = TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_WARMBOOT_CRT0_AND_MAIN); reset_vec = TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_WARMBOOT_CRT0_AND_MAIN);
} else { } else {
reset_vec = TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_WARMBOOT_CRT0_AND_MAIN); reset_vec = TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_WARMBOOT_CRT0_AND_MAIN);
} }
EVP_CPU_RESET_VECTOR_0 = 0; EVP_CPU_RESET_VECTOR_0 = 0;
SB_AA64_RESET_LOW_0 = reset_vec | 1; SB_AA64_RESET_LOW_0 = reset_vec | 1;
SB_AA64_RESET_HIGH_0 = 0; SB_AA64_RESET_HIGH_0 = 0;

42
exosphere/src/coldboot_init.c
View file

@ -75,7 +75,7 @@ static void tzram_map_all_segments(uintptr_t *mmu_l3_tbl, unsigned int target_fi
static const uintptr_t offs_5x[] = { TUPLE_FOLD_LEFT_0(EVAL(TZRAM_SEGMENT_ID_MAX), _MMAPTZ5XS, COMMA) }; static const uintptr_t offs_5x[] = { TUPLE_FOLD_LEFT_0(EVAL(TZRAM_SEGMENT_ID_MAX), _MMAPTZ5XS, COMMA) };
for(size_t i = 0, offset = 0; i < TZRAM_SEGMENT_ID_MAX; i++) { for(size_t i = 0, offset = 0; i < TZRAM_SEGMENT_ID_MAX; i++) {
uintptr_t off = (target_firmware < EXOSPHERE_TARGET_FIRMWARE_500) ? offs[i] : offs_5x[i]; uintptr_t off = (target_firmware < EXOSPHERE_TARGET_FIRMWARE_500) ? offs[i] : offs_5x[i];
tzram_map_segment(mmu_l3_tbl, TZRAM_SEGMENT_BASE + offset, 0x7C010000ull + off, sizes[i], is_executable[i]); tzram_map_segment(mmu_l3_tbl, TZRAM_SEGMENT_BASE + offset, 0x7C010000ull + off, sizes[i], is_executable[i]);
offset += increments[i]; offset += increments[i];
} }
@ -85,15 +85,15 @@ static void configure_ttbls(unsigned int target_firmware) {
uintptr_t *mmu_l1_tbl; uintptr_t *mmu_l1_tbl;
uintptr_t *mmu_l2_tbl; uintptr_t *mmu_l2_tbl;
uintptr_t *mmu_l3_tbl; uintptr_t *mmu_l3_tbl;
if (target_firmware < EXOSPHERE_TARGET_FIRMWARE_500) { if (target_firmware < EXOSPHERE_TARGET_FIRMWARE_500) {
mmu_l1_tbl = (uintptr_t *)(TZRAM_GET_SEGMENT_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64); mmu_l1_tbl = (uintptr_t *)(TZRAM_GET_SEGMENT_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64);
mmu_l2_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_L2_TRANSLATION_TABLE); mmu_l2_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_L2_TRANSLATION_TABLE);
mmu_l3_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_L3_TRANSLATION_TABLE); mmu_l3_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_L3_TRANSLATION_TABLE);
} else { } else {
mmu_l1_tbl = (uintptr_t *)(TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64); mmu_l1_tbl = (uintptr_t *)(TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64);
mmu_l2_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_L2_TRANSLATION_TABLE); mmu_l2_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_L2_TRANSLATION_TABLE);
mmu_l3_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_L3_TRANSLATION_TABLE); mmu_l3_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_L3_TRANSLATION_TABLE);
} }
mmu_init_table(mmu_l1_tbl, 64); /* 33-bit address space */ mmu_init_table(mmu_l1_tbl, 64); /* 33-bit address space */
mmu_init_table(mmu_l2_tbl, 4096); mmu_init_table(mmu_l2_tbl, 4096);
@ -131,15 +131,15 @@ static void do_relocation(const coldboot_crt0_reloc_list_t *reloc_list, size_t i
} }
uintptr_t get_coldboot_crt0_temp_stack_address(void) { uintptr_t get_coldboot_crt0_temp_stack_address(void) {
return TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800; return TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800;
} }
uintptr_t get_coldboot_crt0_stack_address(void) { uintptr_t get_coldboot_crt0_stack_address(void) {
if (exosphere_get_target_firmware_for_init() < EXOSPHERE_TARGET_FIRMWARE_500) { if (exosphere_get_target_firmware_for_init() < EXOSPHERE_TARGET_FIRMWARE_500) {
return TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800; return TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800;
} else { } else {
return TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800; return TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800;
} }
} }
@ -177,11 +177,11 @@ void coldboot_init(coldboot_crt0_reloc_list_t *reloc_list, uintptr_t start_cold)
init_dma_controllers(g_exosphere_target_firmware_for_init); init_dma_controllers(g_exosphere_target_firmware_for_init);
configure_ttbls(g_exosphere_target_firmware_for_init); configure_ttbls(g_exosphere_target_firmware_for_init);
if (g_exosphere_target_firmware_for_init < EXOSPHERE_TARGET_FIRMWARE_500) { if (g_exosphere_target_firmware_for_init < EXOSPHERE_TARGET_FIRMWARE_500) {
set_memory_registers_enable_mmu_1x_ttbr0(); set_memory_registers_enable_mmu_1x_ttbr0();
} else { } else {
set_memory_registers_enable_mmu_5x_ttbr0(); set_memory_registers_enable_mmu_5x_ttbr0();
} }
/* Copy or clear the remaining sections */ /* Copy or clear the remaining sections */
for(size_t i = 0; i < reloc_list->nb_relocs_post_mmu_init; i++) { for(size_t i = 0; i < reloc_list->nb_relocs_post_mmu_init; i++) {

8
exosphere/src/lp0.c
View file

@ -29,15 +29,15 @@
/* Save security engine, and go to sleep. */ /* Save security engine, and go to sleep. */
void save_se_and_power_down_cpu(void) { void save_se_and_power_down_cpu(void) {
/* TODO: Remove set suspend call once exo warmboots fully */ /* TODO: Remove set suspend call once exo warmboots fully */
set_suspend_for_debug(); set_suspend_for_debug();
uint32_t tzram_cmac[0x4] = {0}; uint32_t tzram_cmac[0x4] = {0};
uint8_t *tzram_encryption_dst = (uint8_t *)(LP0_ENTRY_GET_RAM_SEGMENT_ADDRESS(LP0_ENTRY_RAM_SEGMENT_ID_ENCRYPTED_TZRAM)); uint8_t *tzram_encryption_dst = (uint8_t *)(LP0_ENTRY_GET_RAM_SEGMENT_ADDRESS(LP0_ENTRY_RAM_SEGMENT_ID_ENCRYPTED_TZRAM));
uint8_t *tzram_encryption_src = (uint8_t *)(LP0_ENTRY_GET_RAM_SEGMENT_ADDRESS(LP0_ENTRY_RAM_SEGMENT_ID_CURRENT_TZRAM)); uint8_t *tzram_encryption_src = (uint8_t *)(LP0_ENTRY_GET_RAM_SEGMENT_ADDRESS(LP0_ENTRY_RAM_SEGMENT_ID_CURRENT_TZRAM));
if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500) { if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500) {
tzram_encryption_src += 0x2000ull; tzram_encryption_src += 0x2000ull;
} }
uint8_t *tzram_store_address = (uint8_t *)(WARMBOOT_GET_RAM_SEGMENT_ADDRESS(WARMBOOT_RAM_SEGMENT_ID_TZRAM)); uint8_t *tzram_store_address = (uint8_t *)(WARMBOOT_GET_RAM_SEGMENT_ADDRESS(WARMBOOT_RAM_SEGMENT_ID_TZRAM));
clear_priv_smc_in_progress(); clear_priv_smc_in_progress();

2
exosphere/src/start.s
View file

@ -101,7 +101,7 @@ __start_cold:
br x16 br x16
_post_cold_crt0_reloc: _post_cold_crt0_reloc:
/* Setup stack for coldboot crt0. */ /* Setup stack for coldboot crt0. */
msr spsel, #0 msr spsel, #0
bl get_coldboot_crt0_temp_stack_address bl get_coldboot_crt0_temp_stack_address
mov sp, x0 mov sp, x0

16
exosphere/src/warmboot_init.c
View file

@ -10,7 +10,7 @@
#define MC_BASE (MMIO_GET_DEVICE_PA(MMIO_DEVID_MC)) #define MC_BASE (MMIO_GET_DEVICE_PA(MMIO_DEVID_MC))
#define WARMBOOT_GET_TZRAM_SEGMENT_PA(x) ((g_exosphere_target_firmware_for_init < EXOSPHERE_TARGET_FIRMWARE_500) \ #define WARMBOOT_GET_TZRAM_SEGMENT_PA(x) ((g_exosphere_target_firmware_for_init < EXOSPHERE_TARGET_FIRMWARE_500) \
? TZRAM_GET_SEGMENT_PA(x) : TZRAM_GET_SEGMENT_5X_PA(x)) ? TZRAM_GET_SEGMENT_PA(x) : TZRAM_GET_SEGMENT_5X_PA(x))
/* start.s */ /* start.s */
void __set_memory_registers(uintptr_t ttbr0, uintptr_t vbar, uint64_t cpuectlr, uint32_t scr, void __set_memory_registers(uintptr_t ttbr0, uintptr_t vbar, uint64_t cpuectlr, uint32_t scr,
@ -147,12 +147,12 @@ void _set_memory_registers_enable_mmu(const uintptr_t ttbr0) {
void set_memory_registers_enable_mmu_1x_ttbr0(void) { void set_memory_registers_enable_mmu_1x_ttbr0(void) {
static const uintptr_t ttbr0 = TZRAM_GET_SEGMENT_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64; static const uintptr_t ttbr0 = TZRAM_GET_SEGMENT_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64;
_set_memory_registers_enable_mmu(ttbr0); _set_memory_registers_enable_mmu(ttbr0);
} }
void set_memory_registers_enable_mmu_5x_ttbr0(void) { void set_memory_registers_enable_mmu_5x_ttbr0(void) {
static const uintptr_t ttbr0 = TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64; static const uintptr_t ttbr0 = TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64;
_set_memory_registers_enable_mmu(ttbr0); _set_memory_registers_enable_mmu(ttbr0);
} }
#if 0 /* Since we decided not to identity-unmap TZRAM */ #if 0 /* Since we decided not to identity-unmap TZRAM */
@ -189,9 +189,9 @@ void warmboot_init(void) {
/*identity_remap_tzram();*/ /*identity_remap_tzram();*/
/* Nintendo pointlessly fully invalidate the TLB & invalidate the data cache on the modified ranges here */ /* Nintendo pointlessly fully invalidate the TLB & invalidate the data cache on the modified ranges here */
if (g_exosphere_target_firmware_for_init < EXOSPHERE_TARGET_FIRMWARE_500) { if (g_exosphere_target_firmware_for_init < EXOSPHERE_TARGET_FIRMWARE_500) {
set_memory_registers_enable_mmu_1x_ttbr0(); set_memory_registers_enable_mmu_1x_ttbr0();
} else { } else {
set_memory_registers_enable_mmu_5x_ttbr0(); set_memory_registers_enable_mmu_5x_ttbr0();
} }
} }