From ee0117b59ededc829604aa01b7773b3a5b53cf60 Mon Sep 17 00:00:00 2001 From: Michael Scire Date: Thu, 16 Aug 2018 18:56:04 -0700 Subject: [PATCH] exo: tabs->spaces... --- exosphere/src/arm.s | 4 ++-- exosphere/src/bootup.c | 6 ++--- exosphere/src/coldboot_init.c | 44 +++++++++++++++++------------------ exosphere/src/lp0.c | 8 +++---- exosphere/src/start.s | 4 ++-- exosphere/src/warmboot_init.c | 16 ++++++------- 6 files changed, 41 insertions(+), 41 deletions(-) diff --git a/exosphere/src/arm.s b/exosphere/src/arm.s index 7cf4d0cda..b1dc29109 100644 --- a/exosphere/src/arm.s +++ b/exosphere/src/arm.s @@ -51,7 +51,7 @@ tlb_invalidate_page_inner_shareable: * * This file is based on sample code from ARMv8 ARM. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -84,7 +84,7 @@ __asm_dcache_level: /* x5 <- bit position of #ways */ loop_set: - mov x6, x3 /* x6 <- working copy of #ways */ + mov x6, x3 /* x6 <- working copy of #ways */ loop_way: lsl x7, x6, x5 orr x9, x12, x7 /* map way and level to cisw value */ diff --git a/exosphere/src/bootup.c b/exosphere/src/bootup.c index 7a945ec8f..a1fd2522a 100644 --- a/exosphere/src/bootup.c +++ b/exosphere/src/bootup.c @@ -149,10 +149,10 @@ void bootup_misc_mmio(void) { /* Clear RESET Vector, setup CPU Secure Boot RESET Vectors. */ uint32_t reset_vec; if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500) { - reset_vec = TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_WARMBOOT_CRT0_AND_MAIN); + reset_vec = TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_WARMBOOT_CRT0_AND_MAIN); } else { - reset_vec = TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_WARMBOOT_CRT0_AND_MAIN); - } + reset_vec = TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_WARMBOOT_CRT0_AND_MAIN); + } EVP_CPU_RESET_VECTOR_0 = 0; SB_AA64_RESET_LOW_0 = reset_vec | 1; SB_AA64_RESET_HIGH_0 = 0; diff --git a/exosphere/src/coldboot_init.c b/exosphere/src/coldboot_init.c index 65952539e..c88704638 100644 --- a/exosphere/src/coldboot_init.c +++ b/exosphere/src/coldboot_init.c @@ -73,9 +73,9 @@ static void tzram_map_all_segments(uintptr_t *mmu_l3_tbl, unsigned int target_fi static const bool is_executable[] = { TUPLE_FOLD_LEFT_3(EVAL(TZRAM_SEGMENT_ID_MAX), _MMAPTZS, COMMA) }; static const uintptr_t offs_5x[] = { TUPLE_FOLD_LEFT_0(EVAL(TZRAM_SEGMENT_ID_MAX), _MMAPTZ5XS, COMMA) }; - + for(size_t i = 0, offset = 0; i < TZRAM_SEGMENT_ID_MAX; i++) { - uintptr_t off = (target_firmware < EXOSPHERE_TARGET_FIRMWARE_500) ? offs[i] : offs_5x[i]; + uintptr_t off = (target_firmware < EXOSPHERE_TARGET_FIRMWARE_500) ? offs[i] : offs_5x[i]; tzram_map_segment(mmu_l3_tbl, TZRAM_SEGMENT_BASE + offset, 0x7C010000ull + off, sizes[i], is_executable[i]); offset += increments[i]; } @@ -85,15 +85,15 @@ static void configure_ttbls(unsigned int target_firmware) { uintptr_t *mmu_l1_tbl; uintptr_t *mmu_l2_tbl; uintptr_t *mmu_l3_tbl; - if (target_firmware < EXOSPHERE_TARGET_FIRMWARE_500) { - mmu_l1_tbl = (uintptr_t *)(TZRAM_GET_SEGMENT_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64); - mmu_l2_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_L2_TRANSLATION_TABLE); - mmu_l3_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_L3_TRANSLATION_TABLE); - } else { - mmu_l1_tbl = (uintptr_t *)(TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64); - mmu_l2_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_L2_TRANSLATION_TABLE); - mmu_l3_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_L3_TRANSLATION_TABLE); - } + if (target_firmware < EXOSPHERE_TARGET_FIRMWARE_500) { + mmu_l1_tbl = (uintptr_t *)(TZRAM_GET_SEGMENT_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64); + mmu_l2_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_L2_TRANSLATION_TABLE); + mmu_l3_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_L3_TRANSLATION_TABLE); + } else { + mmu_l1_tbl = (uintptr_t *)(TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64); + mmu_l2_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_L2_TRANSLATION_TABLE); + mmu_l3_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_L3_TRANSLATION_TABLE); + } mmu_init_table(mmu_l1_tbl, 64); /* 33-bit address space */ mmu_init_table(mmu_l2_tbl, 4096); @@ -131,15 +131,15 @@ static void do_relocation(const coldboot_crt0_reloc_list_t *reloc_list, size_t i } uintptr_t get_coldboot_crt0_temp_stack_address(void) { - return TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800; + return TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800; } uintptr_t get_coldboot_crt0_stack_address(void) { - if (exosphere_get_target_firmware_for_init() < EXOSPHERE_TARGET_FIRMWARE_500) { - return TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800; - } else { - return TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800; - } + if (exosphere_get_target_firmware_for_init() < EXOSPHERE_TARGET_FIRMWARE_500) { + return TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800; + } else { + return TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800; + } } @@ -177,11 +177,11 @@ void coldboot_init(coldboot_crt0_reloc_list_t *reloc_list, uintptr_t start_cold) init_dma_controllers(g_exosphere_target_firmware_for_init); configure_ttbls(g_exosphere_target_firmware_for_init); - if (g_exosphere_target_firmware_for_init < EXOSPHERE_TARGET_FIRMWARE_500) { - set_memory_registers_enable_mmu_1x_ttbr0(); - } else { - set_memory_registers_enable_mmu_5x_ttbr0(); - } + if (g_exosphere_target_firmware_for_init < EXOSPHERE_TARGET_FIRMWARE_500) { + set_memory_registers_enable_mmu_1x_ttbr0(); + } else { + set_memory_registers_enable_mmu_5x_ttbr0(); + } /* Copy or clear the remaining sections */ for(size_t i = 0; i < reloc_list->nb_relocs_post_mmu_init; i++) { diff --git a/exosphere/src/lp0.c b/exosphere/src/lp0.c index e52e3ae52..520042c5c 100644 --- a/exosphere/src/lp0.c +++ b/exosphere/src/lp0.c @@ -29,15 +29,15 @@ /* Save security engine, and go to sleep. */ void save_se_and_power_down_cpu(void) { - /* TODO: Remove set suspend call once exo warmboots fully */ + /* TODO: Remove set suspend call once exo warmboots fully */ set_suspend_for_debug(); uint32_t tzram_cmac[0x4] = {0}; uint8_t *tzram_encryption_dst = (uint8_t *)(LP0_ENTRY_GET_RAM_SEGMENT_ADDRESS(LP0_ENTRY_RAM_SEGMENT_ID_ENCRYPTED_TZRAM)); uint8_t *tzram_encryption_src = (uint8_t *)(LP0_ENTRY_GET_RAM_SEGMENT_ADDRESS(LP0_ENTRY_RAM_SEGMENT_ID_CURRENT_TZRAM)); - if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500) { - tzram_encryption_src += 0x2000ull; - } + if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_500) { + tzram_encryption_src += 0x2000ull; + } uint8_t *tzram_store_address = (uint8_t *)(WARMBOOT_GET_RAM_SEGMENT_ADDRESS(WARMBOOT_RAM_SEGMENT_ID_TZRAM)); clear_priv_smc_in_progress(); diff --git a/exosphere/src/start.s b/exosphere/src/start.s index 185291859..0374248da 100644 --- a/exosphere/src/start.s +++ b/exosphere/src/start.s @@ -101,7 +101,7 @@ __start_cold: br x16 _post_cold_crt0_reloc: - /* Setup stack for coldboot crt0. */ + /* Setup stack for coldboot crt0. */ msr spsel, #0 bl get_coldboot_crt0_temp_stack_address mov sp, x0 @@ -131,7 +131,7 @@ _post_cold_crt0_reloc: ldr x1, =0x80010000 /* Set size in coldboot relocation list. */ str x21, [x0, #0x8] - + bl coldboot_init ldr x16, =__jump_to_main_cold diff --git a/exosphere/src/warmboot_init.c b/exosphere/src/warmboot_init.c index d3d73374c..427792054 100644 --- a/exosphere/src/warmboot_init.c +++ b/exosphere/src/warmboot_init.c @@ -10,7 +10,7 @@ #define MC_BASE (MMIO_GET_DEVICE_PA(MMIO_DEVID_MC)) #define WARMBOOT_GET_TZRAM_SEGMENT_PA(x) ((g_exosphere_target_firmware_for_init < EXOSPHERE_TARGET_FIRMWARE_500) \ - ? TZRAM_GET_SEGMENT_PA(x) : TZRAM_GET_SEGMENT_5X_PA(x)) + ? TZRAM_GET_SEGMENT_PA(x) : TZRAM_GET_SEGMENT_5X_PA(x)) /* start.s */ void __set_memory_registers(uintptr_t ttbr0, uintptr_t vbar, uint64_t cpuectlr, uint32_t scr, @@ -147,12 +147,12 @@ void _set_memory_registers_enable_mmu(const uintptr_t ttbr0) { void set_memory_registers_enable_mmu_1x_ttbr0(void) { static const uintptr_t ttbr0 = TZRAM_GET_SEGMENT_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64; - _set_memory_registers_enable_mmu(ttbr0); + _set_memory_registers_enable_mmu(ttbr0); } void set_memory_registers_enable_mmu_5x_ttbr0(void) { static const uintptr_t ttbr0 = TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64; - _set_memory_registers_enable_mmu(ttbr0); + _set_memory_registers_enable_mmu(ttbr0); } #if 0 /* Since we decided not to identity-unmap TZRAM */ @@ -189,9 +189,9 @@ void warmboot_init(void) { /*identity_remap_tzram();*/ /* Nintendo pointlessly fully invalidate the TLB & invalidate the data cache on the modified ranges here */ - if (g_exosphere_target_firmware_for_init < EXOSPHERE_TARGET_FIRMWARE_500) { - set_memory_registers_enable_mmu_1x_ttbr0(); - } else { - set_memory_registers_enable_mmu_5x_ttbr0(); - } + if (g_exosphere_target_firmware_for_init < EXOSPHERE_TARGET_FIRMWARE_500) { + set_memory_registers_enable_mmu_1x_ttbr0(); + } else { + set_memory_registers_enable_mmu_5x_ttbr0(); + } }