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https://github.com/Atmosphere-NX/Atmosphere
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thermosphere: unfuck qemu JIT, fix exc. handling bug, add cache funcs
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parent
1f767fcce9
commit
af80d5816b
6 changed files with 274 additions and 25 deletions
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@ -132,7 +132,7 @@ export LIBPATHS := $(foreach dir,$(LIBDIRS),-L$(dir)/lib)
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all: $(BUILD)
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ifeq ($(PLATFORM), qemu)
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QEMUFLAGS := -nographic -machine virt,secure=on,virtualization=on,gic-version=2 -cpu cortex-a57 -smp 2 -m 1024\
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QEMUFLAGS := -nographic -machine virt,secure=on,virtualization=on,gic-version=2 -cpu cortex-a57 -smp 4 -m 1024\
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-bios bl1.bin -d unimp -semihosting-config enable,target=native -serial mon:stdio
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# NOTE: copy bl1.bin, bl2.bin, bl31.bin from your own build of Arm Trusted Firmware!
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10
thermosphere/src/arm.h
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10
thermosphere/src/arm.h
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@ -0,0 +1,10 @@
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#pragma once
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void flush_dcache_all(void);
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void invalidate_dcache_all(void);
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void flush_dcache_range(const void *start, const void *end);
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void invalidate_dcache_range(const void *start, const void *end);
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void invalidate_icache_all_inner_shareable(void);
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void invalidate_icache_all(void);
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214
thermosphere/src/arm.s
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214
thermosphere/src/arm.s
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@ -0,0 +1,214 @@
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/*
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* Copyright (c) 2018-2019 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* The following functions are taken/adapted from https://github.com/u-boot/u-boot/blob/master/arch/arm/cpu/armv8/cache.S */
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/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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* This file is based on sample code from ARMv8 ARM.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* void __asm_dcache_level(level)
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*
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* flush or invalidate one level cache.
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*
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* x0: cache level
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* x1: 0 clean & invalidate, 1 invalidate only
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* x2~x9: clobbered
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*/
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.section .text.__asm_dcache_level, "ax", %progbits
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.type __asm_dcache_level, %function
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__asm_dcache_level:
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lsl x12, x0, #1
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msr csselr_el1, x12 /* select cache level */
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isb /* sync change of cssidr_el1 */
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mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
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and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
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add x2, x2, #4 /* x2 <- log2(cache line size) */
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mov x3, #0x3ff
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and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
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clz w5, w3 /* bit position of #ways */
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mov x4, #0x7fff
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and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
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/* x12 <- cache level << 1 */
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/* x2 <- line length offset */
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/* x3 <- number of cache ways - 1 */
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/* x4 <- number of cache sets - 1 */
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/* x5 <- bit position of #ways */
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loop_set:
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mov x6, x3 /* x6 <- working copy of #ways */
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loop_way:
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lsl x7, x6, x5
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orr x9, x12, x7 /* map way and level to cisw value */
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lsl x7, x4, x2
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orr x9, x9, x7 /* map set number to cisw value */
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tbz w1, #0, 1f
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dc isw, x9
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b 2f
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1: dc cisw, x9 /* clean & invalidate by set/way */
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2: subs x6, x6, #1 /* decrement the way */
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b.ge loop_way
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subs x4, x4, #1 /* decrement the set */
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b.ge loop_set
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ret
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/*
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* void __asm_flush_dcache_all(int invalidate_only)
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*
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* x0: 0 clean & invalidate, 1 invalidate only
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*
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* flush or invalidate all data cache by SET/WAY.
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*/
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.section .text.__asm_dcache_all, "ax", %progbits
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.type __asm_dcache_all, %function
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__asm_dcache_all:
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mov x1, x0
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dsb sy
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mrs x10, clidr_el1 /* read clidr_el1 */
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lsr x11, x10, #24
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and x11, x11, #0x7 /* x11 <- loc */
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cbz x11, finished /* if loc is 0, exit */
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mov x15, lr
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mov x0, #0 /* start flush at cache level 0 */
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/* x0 <- cache level */
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/* x10 <- clidr_el1 */
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/* x11 <- loc */
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/* x15 <- return address */
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loop_level:
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lsl x12, x0, #1
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add x12, x12, x0 /* x0 <- tripled cache level */
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lsr x12, x10, x12
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and x12, x12, #7 /* x12 <- cache type */
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cmp x12, #2
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b.lt skip /* skip if no cache or icache */
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bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */
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skip:
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add x0, x0, #1 /* increment cache level */
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cmp x11, x0
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b.gt loop_level
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mov x0, #0
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msr csselr_el1, x0 /* restore csselr_el1 */
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dsb sy
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isb
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mov lr, x15
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finished:
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ret
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.section .text.flush_dcache_all, "ax", %progbits
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.type flush_dcache_all, %function
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.global flush_dcache_all
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flush_dcache_all:
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mov x0, #0
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b __asm_dcache_all
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.section .text.invalidate_dcache_all, "ax", %progbits
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.type invalidate_dcache_all, %function
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.global invalidate_dcache_all
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invalidate_dcache_all:
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mov x0, #1
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b __asm_dcache_all
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/*
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* void __asm_flush_dcache_range(start, end) (renamed -> flush_dcache_range)
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*
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* clean & invalidate data cache in the range
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*
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* x0: start address
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* x1: end address
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*/
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.section .text.flush_dcache_range, "ax", %progbits
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.type flush_dcache_range, %function
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.global flush_dcache_range
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flush_dcache_range:
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mrs x3, ctr_el0
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lsr x3, x3, #16
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and x3, x3, #0xf
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mov x2, #4
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lsl x2, x2, x3 /* cache line size */
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/* x2 <- minimal cache line size in cache system */
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sub x3, x2, #1
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bic x0, x0, x3
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1: dc civac, x0 /* clean & invalidate data or unified cache */
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add x0, x0, x2
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cmp x0, x1
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b.lo 1b
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dsb sy
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ret
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/*
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* void __asm_invalidate_dcache_range(start, end) (-> invalidate_dcache_range)
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*
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* invalidate data cache in the range
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*
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* x0: start address
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* x1: end address
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*/
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.section .text.invalidate_dcache_range, "ax", %progbits
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.type invalidate_dcache_range, %function
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.global invalidate_dcache_range
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invalidate_dcache_range:
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mrs x3, ctr_el0
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ubfm x3, x3, #16, #19
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mov x2, #4
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lsl x2, x2, x3 /* cache line size */
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/* x2 <- minimal cache line size in cache system */
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sub x3, x2, #1
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bic x0, x0, x3
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1: dc ivac, x0 /* invalidate data or unified cache */
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add x0, x0, x2
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cmp x0, x1
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b.lo 1b
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dsb sy
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ret
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/*
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* void __asm_invalidate_icache_all(void) (-> invalidate_icache_inner_shareable)
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*
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* invalidate all icache entries.
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*/
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.section .text.invalidate_icache_all_inner_shareable, "ax", %progbits
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.type invalidate_icache_all_inner_shareable, %function
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.global invalidate_icache_all_inner_shareable
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invalidate_icache_all_inner_shareable:
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dsb ish
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isb
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ic ialluis
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dsb ish
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isb
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ret
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.section .text.invalidate_icache_all, "ax", %progbits
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.type invalidate_icache_all, %function
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.global invalidate_icache_all
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invalidate_icache_all:
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dsb ish
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isb
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ic iallu
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dsb ish
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isb
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ret
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@ -55,6 +55,13 @@
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bl _save_all_regs
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.endm
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.macro save_all_regs_reload_x18
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save_all_regs
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// Reload our x18 value (currentCoreCtx)
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ldp x18, xzr, [sp, #0x120]
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.endm
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.macro pivot_stack_for_crash
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// Note: reset x18 assumed uncorrupted
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// Note: replace sp_el0 with crashing sp
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@ -124,8 +131,6 @@ vector_entry irq_sp0
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mov x30, x29
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// Reload our x18 value (currentCoreCtx)
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ldp x18, xzr, [sp, #0x120]
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ret
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vector_entry fiq_sp0
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@ -194,7 +199,7 @@ vector_entry serror_spx
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/* Lower EL, A64 */
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vector_entry synch_a64
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save_all_regs
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save_all_regs_reload_x18
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mov x0, sp
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mrs x1, esr_el2
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@ -1,13 +1,19 @@
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#include "utils.h"
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#include "core_ctx.h"
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#include "log.h"
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#include "platform/uart.h"
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int main(void)
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{
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if (currentCoreCtx->coreId == 0) {
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uartInit(115200);
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serialLog("fifo flush fifo flush\n");
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serialLog("Hello from Thermosphere!\n");
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__builtin_trap();
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}
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else {
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serialLog("Core %u booted\n", currentCoreCtx->coreId);
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}
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return 0;
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}
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@ -40,17 +40,35 @@ _startCommon:
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msr daifset, 0b1111
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msr spsel, #1
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mrs x20, sctlr_el2
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// Set VBAR
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ldr x8, =__vectors_start__
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msr vbar_el2, x8
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// Set system to sane defaults, aarch64 for el1
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mov x4, #0x0838
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movk x4, #0xC5, lsl #16
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orr x1, x4, #0x30000000
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mov x2, #(1 << 31)
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mov x3, #0xFFFFFFFF
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msr sctlr_el2, x1
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msr hcr_el2, x2
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msr dacr32_el2, x3
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dsb sy
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isb
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// Mov x20 (and no other register (?)) with != 0 is needed to unfuck QEMU's JIT
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mov x20, #0x31
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// Get core ID
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mrs x20, mpidr_el1
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and x20, x20, #0xFF
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mrs x10, mpidr_el1
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and x10, x10, #0xFF
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// Set tmp stack
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ldr x8, =__stacks_top__
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/* lsl x9, x20, #10
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sub x8, x8, x9*/
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mov sp, x8
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lsl x9, x10, #10
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sub sp, x8, x9
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// Set up x18
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adrp x18, g_coreCtxs
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@ -66,26 +84,22 @@ _startCommon:
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_store_arg:
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str x0, [x18, #0]
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// Set VBAR
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ldr x8, =__vectors_start__
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msr vbar_el2, x8
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// Make sure the regs have been set
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dsb sy
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isb
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// Don't call init array to save space?
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// Clear BSS & call main for the first core executing this code
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cbz x20, _jump_to_kernel
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cbz x20, _jump_to_main
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ldr x0, =__bss_start__
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mov w1, #0
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ldr x2, =__end__
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sub x2, x2, x0
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bl memset
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dsb sy
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isb
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_jump_to_main:
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bl main
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_jump_to_kernel:
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// Jump to kernel
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mov x8, #(0b1111 << 6 | 0b0101) // EL1h+DAIF
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msr spsr_el2, x8
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