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https://github.com/Atmosphere-NX/Atmosphere
synced 2024-12-23 04:41:12 +00:00
thermosphere: use x18 but qemu shits the bed
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parent
3769493300
commit
1f767fcce9
6 changed files with 64 additions and 39 deletions
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@ -49,13 +49,12 @@ INCLUDES := include ../common/include
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#---------------------------------------------------------------------------------
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# options for code generation
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#---------------------------------------------------------------------------------
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ARCH := -march=armv8-a -mtune=cortex-a57 -mgeneral-regs-only #<- important
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ARCH := -march=armv8-a -mtune=cortex-a57 -mgeneral-regs-only -ffixed-x18 #<- important
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DEFINES := -D__CCPLEX__ -DATMOSPHERE_GIT_BRANCH=\"$(AMSBRANCH)\" -DATMOSPHERE_GIT_REV=\"$(AMSREV)\"\
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-DATMOSPHERE_RELEASE_VERSION_HASH="0x$(AMSHASH)" $(PLATFORM_DEFINES)
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CFLAGS := \
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-g \
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-Os \
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-ffixed-x18 \
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-ffunction-sections \
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-fdata-sections \
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-fomit-frame-pointer \
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@ -133,7 +132,7 @@ export LIBPATHS := $(foreach dir,$(LIBDIRS),-L$(dir)/lib)
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all: $(BUILD)
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ifeq ($(PLATFORM), qemu)
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QEMUFLAGS := -nographic -machine virt,secure=on,virtualization=on -cpu cortex-a57 -smp 2 -m 1024\
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QEMUFLAGS := -nographic -machine virt,secure=on,virtualization=on,gic-version=2 -cpu cortex-a57 -smp 2 -m 1024\
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-bios bl1.bin -d unimp -semihosting-config enable,target=native -serial mon:stdio
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# NOTE: copy bl1.bin, bl2.bin, bl31.bin from your own build of Arm Trusted Firmware!
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@ -16,7 +16,7 @@
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#include "core_ctx.h"
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CoreCtx g_coreCtxInstances[4] = {
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CoreCtx g_coreCtxs[4] = {
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{ .coreId = 0 },
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{ .coreId = 1 },
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{ .coreId = 2 },
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@ -18,8 +18,10 @@
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#include "utils.h"
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typedef struct CoreCtx {
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u32 coreId;
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u64 kernelArgument;
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u64 kernelEntrypoint;
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u32 coreId; // @ 0x0C
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} CoreCtx;
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extern CoreCtx g_coreCtxInstances[4];
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register CoreCtx *currentCoreCtx asm("x18");
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extern CoreCtx g_coreCtxs[4];
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register CoreCtx *currentCoreCtx asm("x18");
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@ -56,17 +56,17 @@
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.endm
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.macro pivot_stack_for_crash
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// Ditch sp_el0 & elr_el1
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// We don't use E2H so that's fine.
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msr elr_el1, x0
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mov x0, sp
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msr sp_el0, x0 // save stack pointer for the crash
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bic x0, x0, #0xFF
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bic x0, x0, #0x300
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add x0, x0, #0x1000
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add x0, x0, #0x400
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mov sp, x0
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mrs x0, elr_el1
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// Note: reset x18 assumed uncorrupted
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// Note: replace sp_el0 with crashing sp
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mrs x18, esr_el2
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mov x18, sp
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msr sp_el0, x18
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bic x18, x18, #0xFF
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bic x18, x18, #0x300
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add x18, x18, #0x400
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mov sp, x18
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ldp x18, xzr, [sp, #-0x10]
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add sp, sp, #0x1000
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.endm
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/* Actual Vectors for Thermosphere. */
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@ -123,6 +123,9 @@ vector_entry irq_sp0
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stp x23, xzr, [sp, #0x110]
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mov x30, x29
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// Reload our x18 value (currentCoreCtx)
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ldp x18, xzr, [sp, #0x120]
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ret
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vector_entry fiq_sp0
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@ -17,6 +17,7 @@
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#include "hvc.h"
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#include "traps.h"
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#include "sysreg_traps.h"
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#include "core_ctx.h"
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#include "log.h"
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@ -121,11 +122,11 @@ void handleLowerElSyncException(ExceptionStackFrame *frame, ExceptionSyndromeReg
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void handleSameElSyncException(ExceptionStackFrame *frame, ExceptionSyndromeRegister esr)
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{
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serialLog("Same EL sync exception, EC = 0x%02llx IL=%llu ISS=0x%06llx\n", (u64)esr.ec, esr.il, esr.iss);
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serialLog("Same EL sync exception on core %x, EC = 0x%02llx IL=%llu ISS=0x%06llx\n", currentCoreCtx->coreId, (u64)esr.ec, esr.il, esr.iss);
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dumpStackFrame(frame, true);
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}
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void handleUnknownException(u32 offset)
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{
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serialLog("Unknown exception! (offset 0x%03lx)\n", offset);
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serialLog("Unknown exception on core %x! (offset 0x%03lx)\n", offset, currentCoreCtx->coreId);
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}
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@ -25,53 +25,73 @@
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_start:
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b start
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nop
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b start2
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.global g_kernelEntrypoint
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g_kernelEntrypoint:
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_initialKernelEntrypoint:
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.quad 0
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start:
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mov x19, #1
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b _startCommon
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start2:
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mov x19, #0
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_startCommon:
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// Disable interrupts, select sp_el2
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msr daifset, 0b1111
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msr spsel, #1
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// Save arg, load entrypoint & spsr
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mov x19, x0
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ldr x8, g_kernelEntrypoint
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msr elr_el2, x8
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mov x8, #(0b1111 << 6 | 0b0101) // EL1h+DAIF
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msr spsr_el2, x8
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mrs x20, sctlr_el2
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// Get core ID
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mrs x20, mpidr_el1
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and x20, x20, #0xFF
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// Make sure the regs have been set
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dsb sy
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isb
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// Set tmp stack
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ldr x8, =__stacks_top__
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/* lsl x9, x20, #10
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sub x8, x8, x9*/
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mov sp, x8
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// Set up x18
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adrp x18, g_coreCtxs
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add x18, x18, #:lo12:g_coreCtxs
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add x18, x18, x20, lsl #3
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stp x18, xzr, [sp, #-0x10]!
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// Store entrypoint if first core
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cbz x19, _store_arg
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ldr x8, _initialKernelEntrypoint
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str x8, [x18, #8]
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_store_arg:
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str x0, [x18, #0]
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// Set VBAR
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ldr x8, =__vectors_start__
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msr vbar_el2, x8
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// Set tmp stack
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ldr x8, =__stacks_top__
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mov sp, x8
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// Make sure the regs have been set
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dsb sy
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isb
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// Don't call init array to save space?
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// Clear BSS
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// Clear BSS & call main for the first core executing this code
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cbz x20, _jump_to_kernel
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ldr x0, =__bss_start__
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mov w1, #0
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ldr x2, =__end__
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sub x2, x2, x0
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bl memset
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// TODO
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bl main
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_jump_to_kernel:
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// Jump to kernel
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mov x0, x19
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mov x8, #(0b1111 << 6 | 0b0101) // EL1h+DAIF
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msr spsr_el2, x8
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ldp x0, x1, [x18]
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msr elr_el2, x1
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dsb sy
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isb
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eret
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