nold/Atmosphere
1
0
Fork 0
mirror of https://github.com/Atmosphere-NX/Atmosphere synced 2024-11-15 01:26:34 +00:00
Code Issues Projects Releases Packages Wiki Activity

fusee: mariko sdram initialization

Browse source
This commit is contained in:
hexkyz 2020-11-23 19:11:15 +00:00 committed by Michael Scire
parent 4111aa0a83
commit 736360e965
35 changed files with 12590 additions and 8104 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

40
fusee/fusee-mtc/src/emc.h
View file

@ -1086,4 +1086,44 @@
#define EMC_PMC_SCRATCH2 0x444 #define EMC_PMC_SCRATCH2 0x444
#define EMC_PMC_SCRATCH3 0x448 #define EMC_PMC_SCRATCH3 0x448
#define EMC_PMACRO_PERBIT_FGCG_CTRL_0 0xd40
#define EMC_PMACRO_PERBIT_FGCG_CTRL_1 0xd44
#define EMC_PMACRO_PERBIT_FGCG_CTRL_2 0xd48
#define EMC_PMACRO_PERBIT_FGCG_CTRL_3 0xd4c
#define EMC_PMACRO_PERBIT_FGCG_CTRL_4 0xd50
#define EMC_PMACRO_PERBIT_FGCG_CTRL_5 0xd54
#define EMC_PMACRO_PERBIT_RFU_CTRL_0 0xd60
#define EMC_PMACRO_PERBIT_RFU_CTRL_1 0xd64
#define EMC_PMACRO_PERBIT_RFU_CTRL_2 0xd68
#define EMC_PMACRO_PERBIT_RFU_CTRL_3 0xd6c
#define EMC_PMACRO_PERBIT_RFU_CTRL_4 0xd70
#define EMC_PMACRO_PERBIT_RFU_CTRL_5 0xd74
#define EMC_PMACRO_PERBIT_RFU1_CTRL_0 0xd80
#define EMC_PMACRO_PERBIT_RFU1_CTRL_1 0xd84
#define EMC_PMACRO_PERBIT_RFU1_CTRL_2 0xd88
#define EMC_PMACRO_PERBIT_RFU1_CTRL_3 0xd8c
#define EMC_PMACRO_PERBIT_RFU1_CTRL_4 0xd90
#define EMC_PMACRO_PERBIT_RFU1_CTRL_5 0xd94
#define EMC_PMACRO_PMU_OUT_EOFF1_0 0xda0
#define EMC_PMACRO_PMU_OUT_EOFF1_1 0xda4
#define EMC_PMACRO_PMU_OUT_EOFF1_2 0xda8
#define EMC_PMACRO_PMU_OUT_EOFF1_3 0xdac
#define EMC_PMACRO_PMU_OUT_EOFF1_4 0xdb0
#define EMC_PMACRO_PMU_OUT_EOFF1_5 0xdb4
#define EMC_PMACRO_COMP_PMU_OUT 0xdc0
#define EMC_PMACRO_DATA_PI_CTRL 0x110
#define EMC_PMACRO_CMD_PI_CTRL 0x114
#define EMC_AUTO_CAL_CONFIG9 0x42c
#define EMC_TRTM 0xbc
#define EMC_TWTM 0xf8
#define EMC_TRATM 0xfc
#define EMC_TWATM 0x108
#define EMC_TR2REF 0x10c
#define EMC_PMACRO_DSR_VTTGEN_CTRL_0 0xc6c
#endif #endif

2
fusee/fusee-mtc/src/fuse.c
View file

@ -187,7 +187,7 @@ uint32_t fuse_get_reserved_odm(uint32_t index) {
/* Get the DramId. */ /* Get the DramId. */
uint32_t fuse_get_dram_id(void) { uint32_t fuse_get_dram_id(void) {
return ((fuse_get_reserved_odm(4) >> 3) & 0x7); return ((fuse_get_reserved_odm(4) >> 3) & 0x1F);
} }
/* Derive the DeviceId. */ /* Derive the DeviceId. */

1
fusee/fusee-mtc/src/mc.h
View file

@ -497,6 +497,7 @@
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08 #define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08
#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0 #define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0
#define MC_DA_CONFIG0 0x9dc #define MC_DA_CONFIG0 0x9dc
#define MC_UNTRANSLATED_REGION_CHECK 0x948
/* Memory Controller clients */ /* Memory Controller clients */
#define CLIENT_ACCESS_NUM_CLIENTS 32 #define CLIENT_ACCESS_NUM_CLIENTS 32

40
fusee/fusee-primary/src/emc.h
View file

@ -1086,4 +1086,44 @@
#define EMC_PMC_SCRATCH2 0x444 #define EMC_PMC_SCRATCH2 0x444
#define EMC_PMC_SCRATCH3 0x448 #define EMC_PMC_SCRATCH3 0x448
#define EMC_PMACRO_PERBIT_FGCG_CTRL_0 0xd40
#define EMC_PMACRO_PERBIT_FGCG_CTRL_1 0xd44
#define EMC_PMACRO_PERBIT_FGCG_CTRL_2 0xd48
#define EMC_PMACRO_PERBIT_FGCG_CTRL_3 0xd4c
#define EMC_PMACRO_PERBIT_FGCG_CTRL_4 0xd50
#define EMC_PMACRO_PERBIT_FGCG_CTRL_5 0xd54
#define EMC_PMACRO_PERBIT_RFU_CTRL_0 0xd60
#define EMC_PMACRO_PERBIT_RFU_CTRL_1 0xd64
#define EMC_PMACRO_PERBIT_RFU_CTRL_2 0xd68
#define EMC_PMACRO_PERBIT_RFU_CTRL_3 0xd6c
#define EMC_PMACRO_PERBIT_RFU_CTRL_4 0xd70
#define EMC_PMACRO_PERBIT_RFU_CTRL_5 0xd74
#define EMC_PMACRO_PERBIT_RFU1_CTRL_0 0xd80
#define EMC_PMACRO_PERBIT_RFU1_CTRL_1 0xd84
#define EMC_PMACRO_PERBIT_RFU1_CTRL_2 0xd88
#define EMC_PMACRO_PERBIT_RFU1_CTRL_3 0xd8c
#define EMC_PMACRO_PERBIT_RFU1_CTRL_4 0xd90
#define EMC_PMACRO_PERBIT_RFU1_CTRL_5 0xd94
#define EMC_PMACRO_PMU_OUT_EOFF1_0 0xda0
#define EMC_PMACRO_PMU_OUT_EOFF1_1 0xda4
#define EMC_PMACRO_PMU_OUT_EOFF1_2 0xda8
#define EMC_PMACRO_PMU_OUT_EOFF1_3 0xdac
#define EMC_PMACRO_PMU_OUT_EOFF1_4 0xdb0
#define EMC_PMACRO_PMU_OUT_EOFF1_5 0xdb4
#define EMC_PMACRO_COMP_PMU_OUT 0xdc0
#define EMC_PMACRO_DATA_PI_CTRL 0x110
#define EMC_PMACRO_CMD_PI_CTRL 0x114
#define EMC_AUTO_CAL_CONFIG9 0x42c
#define EMC_TRTM 0xbc
#define EMC_TWTM 0xf8
#define EMC_TRATM 0xfc
#define EMC_TWATM 0x108
#define EMC_TR2REF 0x10c
#define EMC_PMACRO_DSR_VTTGEN_CTRL_0 0xc6c
#endif #endif

2
fusee/fusee-primary/src/fuse.c
View file

@ -187,7 +187,7 @@ uint32_t fuse_get_reserved_odm(uint32_t index) {
/* Get the DramId. */ /* Get the DramId. */
uint32_t fuse_get_dram_id(void) { uint32_t fuse_get_dram_id(void) {
return ((fuse_get_reserved_odm(4) >> 3) & 0x7); return ((fuse_get_reserved_odm(4) >> 3) & 0x1F);
} }
/* Derive the DeviceId. */ /* Derive the DeviceId. */

12
fusee/fusee-primary/src/hwinit.c
View file

@ -320,10 +320,10 @@ void nx_hwinit_erista(bool enable_log) {
/* mc_config_carveout(); */ /* mc_config_carveout(); */
/* Initialize SDRAM. */ /* Initialize SDRAM. */
sdram_init(); sdram_init_erista();
/* Save SDRAM LP0 parameters. */ /* Save SDRAM parameters to scratch. */
sdram_lp0_save_params(sdram_get_params()); sdram_save_params_erista(sdram_get_params_erista(fuse_get_dram_id()));
} }
void nx_hwinit_mariko(bool enable_log) { void nx_hwinit_mariko(bool enable_log) {
@ -394,4 +394,10 @@ void nx_hwinit_mariko(bool enable_log) {
MAKE_PMC_REG(0xBE8) &= 0xFFFFFFFE; MAKE_PMC_REG(0xBE8) &= 0xFFFFFFFE;
MAKE_PMC_REG(0xBF0) = 0x3; MAKE_PMC_REG(0xBF0) = 0x3;
MAKE_PMC_REG(0xBEC) = 0x3; MAKE_PMC_REG(0xBEC) = 0x3;
/* Initialize SDRAM. */
sdram_init_mariko();
/* Save SDRAM parameters to scratch. */
sdram_save_params_mariko(sdram_get_params_mariko(fuse_get_dram_id()));
} }

2
fusee/fusee-primary/src/hwinit.h
View file

@ -24,7 +24,7 @@
#define I2S_BASE 0x702D1000 #define I2S_BASE 0x702D1000
#define MAKE_I2S_REG(n) MAKE_REG32(I2S_BASE + n) #define MAKE_I2S_REG(n) MAKE_REG32(I2S_BASE + n)
void nx_hwinit_mariko(bool enable_log);
void nx_hwinit_erista(bool enable_log); void nx_hwinit_erista(bool enable_log);
void nx_hwinit_mariko(bool enable_log);
#endif #endif

1
fusee/fusee-primary/src/mc.h
View file

@ -497,6 +497,7 @@
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08 #define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08
#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0 #define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0
#define MC_DA_CONFIG0 0x9dc #define MC_DA_CONFIG0 0x9dc
#define MC_UNTRANSLATED_REGION_CHECK 0x948
/* Memory Controller clients */ /* Memory Controller clients */
#define CLIENT_ACCESS_NUM_CLIENTS 32 #define CLIENT_ACCESS_NUM_CLIENTS 32

2551
fusee/fusee-primary/src/sdram.c
View file

File diff suppressed because it is too large Load diff

9
fusee/fusee-primary/src/sdram.h
View file

@ -18,8 +18,11 @@
#ifndef FUSEE_SDRAM_H_ #ifndef FUSEE_SDRAM_H_
#define FUSEE_SDRAM_H_ #define FUSEE_SDRAM_H_
void sdram_init(); void sdram_init_erista(void);
const void *sdram_get_params(); void sdram_init_mariko(void);
void sdram_lp0_save_params(const void *params); const void *sdram_get_params_erista(uint32_t dram_id);
const void *sdram_get_params_mariko(uint32_t dram_id);
void sdram_save_params_erista(const void *save_params);
void sdram_save_params_mariko(const void *save_params);
#endif #endif

2256
fusee/fusee-primary/src/sdram.inl
View file

File diff suppressed because it is too large Load diff

1125
fusee/fusee-primary/src/sdram_lp0.c
View file

File diff suppressed because it is too large Load diff

212
fusee/fusee-primary/src/sdram_lz.inl
View file

@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2018 naehrwert * Copyright (c) 2018 naehrwert
* Copyright (c) 2018-2020 Atmosphère-NX
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@ -14,7 +15,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>. * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
static const uint8_t _dram_cfg_lz[1262] = { static const uint8_t sdram_params_erista_lz[1262] = {
0x17, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x17, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00,
0x00, 0x2C, 0x17, 0x04, 0x09, 0x00, 0x17, 0x04, 0x04, 0x17, 0x08, 0x08, 0x00, 0x2C, 0x17, 0x04, 0x09, 0x00, 0x17, 0x04, 0x04, 0x17, 0x08, 0x08,
0x17, 0x10, 0x10, 0x00, 0x00, 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, 0x17, 0x10, 0x10, 0x00, 0x00, 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00,
@ -122,3 +123,212 @@ static const uint8_t _dram_cfg_lz[1262] = {
0xAC, 0x38, 0x07, 0x17, 0x0D, 0x8E, 0x68, 0xA3, 0x72, 0x17, 0x83, 0x10, 0xAC, 0x38, 0x07, 0x17, 0x0D, 0x8E, 0x68, 0xA3, 0x72, 0x17, 0x83, 0x10,
0x8E, 0x68 0x8E, 0x68
}; };
static const uint8_t sdram_params_mariko_lz[1727] = {
0x19, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00,
0x00, 0x2C, 0x19, 0x04, 0x09, 0x00, 0x19, 0x04, 0x04, 0x19, 0x08, 0x08,
0x19, 0x10, 0x10, 0x19, 0x20, 0x20, 0x19, 0x40, 0x40, 0x19, 0x2A, 0x2A,
0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x19, 0x04, 0x04, 0x19, 0x09,
0x14, 0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x19, 0x06, 0x0E,
0x88, 0x19, 0x04, 0x04, 0x00, 0x20, 0x12, 0x19, 0x0A, 0x0C, 0x19, 0x06,
0x08, 0x00, 0x00, 0xBC, 0xBC, 0xC5, 0xB3, 0x3C, 0x9E, 0x00, 0x00, 0x02,
0x03, 0xE0, 0xC1, 0x04, 0x04, 0x04, 0x04, 0x19, 0x04, 0x04, 0x19, 0x04,
0x04, 0x3F, 0x3F, 0x3F, 0x3F, 0x19, 0x04, 0x04, 0x19, 0x04, 0x04, 0x19,
0x04, 0x38, 0x04, 0x08, 0x00, 0x00, 0x50, 0x50, 0x50, 0x00, 0xA1, 0x01,
0x00, 0x00, 0x30, 0x19, 0x04, 0x39, 0x10, 0x00, 0x16, 0x00, 0x10, 0x90,
0x19, 0x06, 0x81, 0x00, 0x19, 0x07, 0x74, 0x03, 0x19, 0x04, 0x04, 0x00,
0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x3A, 0x00,
0x00, 0x00, 0x1D, 0x19, 0x0B, 0x81, 0x14, 0x09, 0x00, 0x00, 0x00, 0x04,
0x19, 0x0B, 0x10, 0x0B, 0x19, 0x07, 0x28, 0x08, 0x19, 0x07, 0x0C, 0x19,
0x04, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x15, 0x19, 0x07, 0x08, 0x1B, 0x19,
0x07, 0x28, 0x20, 0x00, 0x00, 0x00, 0x06, 0x19, 0x04, 0x04, 0x19, 0x07,
0x08, 0x19, 0x04, 0x64, 0x19, 0x04, 0x18, 0x19, 0x04, 0x30, 0x19, 0x04,
0x10, 0x19, 0x08, 0x81, 0x00, 0x19, 0x04, 0x10, 0x19, 0x04, 0x4C, 0x0E,
0x00, 0x00, 0x00, 0x05, 0x19, 0x07, 0x1C, 0x19, 0x09, 0x82, 0x24, 0x19,
0x07, 0x6C, 0x19, 0x07, 0x83, 0x57, 0x80, 0x19, 0x04, 0x0A, 0x12, 0x00,
0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x1A, 0x00, 0x00, 0x00, 0x16, 0x19,
0x07, 0x0C, 0x0A, 0x19, 0x04, 0x48, 0x19, 0x07, 0x61, 0xC1, 0x19, 0x07,
0x50, 0x19, 0x04, 0x04, 0x19, 0x04, 0x13, 0x19, 0x04, 0x1C, 0x19, 0x04,
0x08, 0x14, 0x19, 0x07, 0x60, 0x19, 0x08, 0x54, 0x3B, 0x19, 0x04, 0x04,
0x19, 0x07, 0x14, 0x19, 0x04, 0x04, 0x04, 0x19, 0x07, 0x81, 0x6C, 0x19,
0x0C, 0x0C, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91, 0x3F, 0x3A,
0x19, 0x04, 0x5A, 0xF3, 0x0C, 0x04, 0x05, 0x1B, 0x06, 0x02, 0x03, 0x07,
0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A, 0x24, 0x0B, 0x1E,
0x0D, 0x0C, 0x26, 0x26, 0x03, 0x02, 0x1B, 0x1C, 0x23, 0x03, 0x04, 0x07,
0x05, 0x06, 0x25, 0x25, 0x02, 0x0A, 0x0B, 0x1D, 0x0D, 0x08, 0x0C, 0x09,
0x1E, 0x24, 0x26, 0x26, 0x08, 0x24, 0x06, 0x07, 0x9A, 0x19, 0x05, 0x83,
0x3F, 0xFF, 0x00, 0xFF, 0x19, 0x10, 0x84, 0x00, 0x04, 0x00, 0x01, 0x88,
0x00, 0x00, 0x02, 0x88, 0x00, 0x00, 0x0D, 0x88, 0x00, 0x00, 0x00, 0xC0,
0x31, 0x31, 0x03, 0x88, 0x00, 0x00, 0x0B, 0x88, 0x5D, 0x5D, 0x0E, 0x8C,
0x5D, 0x5D, 0x0C, 0x88, 0x08, 0x08, 0x0D, 0x8C, 0x00, 0x00, 0x0D, 0x8C,
0x16, 0x16, 0x16, 0x88, 0x19, 0x06, 0x2C, 0x11, 0x08, 0x19, 0x10, 0x85,
0x5F, 0x10, 0x00, 0xCC, 0x00, 0x0A, 0x00, 0x33, 0x00, 0x00, 0x00, 0x20,
0xF3, 0x25, 0x08, 0x11, 0x19, 0x04, 0x69, 0x0F, 0x19, 0x04, 0x18, 0x19,
0x04, 0x28, 0x01, 0x03, 0x00, 0x70, 0x00, 0x0C, 0x00, 0x01, 0x19, 0x04,
0x0C, 0x08, 0x44, 0x00, 0x10, 0x04, 0x04, 0x00, 0x06, 0x13, 0x07, 0x19,
0x06, 0x1C, 0xA0, 0x00, 0x2C, 0x00, 0x01, 0x37, 0x0F, 0x19, 0x05, 0x82,
0x52, 0x02, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x04, 0x00, 0x1F, 0x22, 0x20,
0x80, 0x0F, 0xF4, 0x20, 0x02, 0x29, 0x29, 0x29, 0x29, 0x19, 0x04, 0x04,
0x19, 0x08, 0x08, 0x78, 0x19, 0x06, 0x85, 0x1A, 0x19, 0x05, 0x58, 0x19,
0x40, 0x85, 0x74, 0x22, 0x00, 0x0E, 0x00, 0x10, 0x19, 0x09, 0x84, 0x22,
0x19, 0x12, 0x18, 0x43, 0x00, 0x49, 0x00, 0x45, 0x00, 0x42, 0x00, 0x47,
0x00, 0x49, 0x00, 0x47, 0x00, 0x46, 0x19, 0x05, 0x83, 0x60, 0x00, 0x00,
0x10, 0x19, 0x18, 0x18, 0x00, 0x28, 0x00, 0x28, 0x19, 0x04, 0x04, 0x19,
0x08, 0x08, 0x19, 0x10, 0x10, 0x00, 0x22, 0x19, 0x05, 0x5A, 0x19, 0x04,
0x5C, 0x19, 0x04, 0x5E, 0x1B, 0x19, 0x05, 0x88, 0x24, 0x19, 0x10, 0x7C,
0x19, 0x09, 0x82, 0x54, 0x40, 0x06, 0x00, 0xCC, 0x00, 0x09, 0x00, 0x4F,
0x00, 0x51, 0x80, 0x19, 0x07, 0x18, 0x19, 0x08, 0x08, 0x19, 0x05, 0x84,
0x40, 0xAB, 0x00, 0x0A, 0x04, 0x11, 0x19, 0x08, 0x82, 0x5C, 0x19, 0x0C,
0x38, 0x19, 0x1C, 0x87, 0x64, 0x19, 0x0B, 0x0C, 0x19, 0x08, 0x89, 0x28,
0x19, 0x05, 0x14, 0x01, 0x22, 0x04, 0xFF, 0x9F, 0xAF, 0x4F, 0x19, 0x09,
0x10, 0x19, 0x0B, 0x28, 0x9F, 0xFF, 0x37, 0x19, 0x06, 0x81, 0x18, 0x32,
0x54, 0x76, 0x10, 0x47, 0x32, 0x65, 0x10, 0x34, 0x76, 0x25, 0x01, 0x34,
0x67, 0x25, 0x01, 0x75, 0x64, 0x32, 0x01, 0x72, 0x56, 0x34, 0x10, 0x23,
0x74, 0x56, 0x01, 0x45, 0x32, 0x67, 0x19, 0x04, 0x24, 0x49, 0x92, 0x24,
0x19, 0x04, 0x04, 0x19, 0x11, 0x78, 0x12, 0x19, 0x04, 0x04, 0x19, 0x13,
0x81, 0x10, 0x20, 0x41, 0x13, 0x1F, 0x14, 0x00, 0x01, 0x00, 0x19, 0x04,
0x7C, 0xFF, 0xFF, 0xFF, 0x7F, 0x1F, 0xD7, 0x36, 0x19, 0x07, 0x89, 0x00,
0x09, 0x00, 0x00, 0x34, 0x10, 0x19, 0x09, 0x87, 0x70, 0x19, 0x14, 0x81,
0x4C, 0x03, 0x00, 0x05, 0x19, 0x05, 0x86, 0x2B, 0x10, 0x02, 0x19, 0x06,
0x87, 0x5D, 0x21, 0x19, 0x07, 0x88, 0x15, 0x19, 0x07, 0x41, 0x19, 0x06,
0x3D, 0x19, 0x07, 0x2C, 0x80, 0x00, 0x40, 0x00, 0x04, 0x10, 0x80, 0x19,
0x05, 0x88, 0x04, 0x81, 0x10, 0x09, 0x28, 0x93, 0x32, 0xA5, 0x44, 0x5B,
0x8A, 0x67, 0x76, 0x19, 0x60, 0x8A, 0x54, 0x10, 0x10, 0x19, 0x04, 0x04,
0x00, 0x00, 0x00, 0xEF, 0x00, 0xEF, 0x19, 0x08, 0x14, 0x1C, 0x1C, 0x1C,
0x1C, 0x19, 0x11, 0x83, 0x18, 0x03, 0x08, 0x19, 0x04, 0x04, 0x00, 0x00,
0x24, 0xFF, 0xFF, 0x00, 0x44, 0x57, 0x6E, 0x00, 0x28, 0x72, 0x39, 0x00,
0x10, 0x9C, 0x4B, 0x00, 0x10, 0x19, 0x05, 0x83, 0x24, 0x08, 0x4C, 0x00,
0x00, 0x80, 0x20, 0x10, 0x0A, 0x00, 0x28, 0x10, 0x00, 0x80, 0x19, 0x08,
0x83, 0x68, 0x19, 0x0C, 0x83, 0x40, 0x19, 0x08, 0x08, 0x05, 0x19, 0x0B,
0x84, 0x0C, 0x04, 0x19, 0x07, 0x10, 0x07, 0x19, 0x06, 0x62, 0x02, 0x01,
0x02, 0x03, 0x00, 0x04, 0x05, 0xA3, 0x72, 0x0F, 0x0F, 0x00, 0x70, 0x19,
0x06, 0x42, 0x1F, 0x19, 0x0A, 0x82, 0x28, 0xFF, 0x00, 0xFF, 0x19, 0x05,
0x87, 0x18, 0x19, 0x07, 0x89, 0x56, 0x19, 0x06, 0x20, 0xF0, 0x19, 0x09,
0x88, 0x24, 0x43, 0xC3, 0xBA, 0xE4, 0xD3, 0x1E, 0x19, 0x0C, 0x8A, 0x0B,
0x19, 0x0A, 0x1C, 0x19, 0x10, 0x81, 0x4C, 0x19, 0x05, 0x44, 0x19, 0x09,
0x0E, 0x19, 0x05, 0x8B, 0x66, 0x19, 0x08, 0x8A, 0x6B, 0x19, 0x11, 0x2C,
0x76, 0x0C, 0x19, 0x0A, 0x8B, 0x4B, 0x19, 0x0F, 0x84, 0x78, 0x19, 0x06,
0x34, 0x19, 0x17, 0x3A, 0x7E, 0x16, 0x40, 0x19, 0x0C, 0x8C, 0x03, 0x19,
0x2A, 0x38, 0x1E, 0x19, 0x0A, 0x38, 0x19, 0x13, 0x81, 0x28, 0x00, 0xC0,
0x19, 0x17, 0x55, 0x46, 0x24, 0x19, 0x0A, 0x81, 0x28, 0x19, 0x14, 0x38,
0x19, 0x18, 0x81, 0x60, 0x46, 0x2C, 0x19, 0x06, 0x38, 0xEC, 0x19, 0x0D,
0x16, 0x19, 0x16, 0x82, 0x3C, 0x19, 0x87, 0x2C, 0x90, 0x38, 0x16, 0x00,
0x0D, 0x00, 0x0B, 0x19, 0x05, 0x84, 0x26, 0x19, 0x16, 0x18, 0x43, 0x00,
0x45, 0x00, 0x45, 0x00, 0x43, 0x00, 0x46, 0x00, 0x47, 0x00, 0x41, 0x00,
0x46, 0x00, 0x0C, 0x19, 0x05, 0x83, 0x3A, 0x0D, 0x19, 0x18, 0x18, 0x19,
0x21, 0x90, 0x38, 0x16, 0x19, 0x05, 0x5A, 0x19, 0x04, 0x5C, 0x19, 0x04,
0x5E, 0x17, 0x19, 0x07, 0x90, 0x70, 0x19, 0x89, 0x5C, 0x90, 0x38, 0x50,
0x05, 0x19, 0x1E, 0x90, 0x38, 0xAF, 0xC9, 0x19, 0x3C, 0x90, 0x38, 0x19,
0x0C, 0x89, 0x30, 0x19, 0x81, 0x0C, 0x90, 0x38, 0x19, 0x04, 0x18, 0x05,
0x19, 0x0F, 0x83, 0x5C, 0x0C, 0x19, 0x81, 0x5A, 0x90, 0x38, 0x08, 0x00,
0x00, 0x02, 0x08, 0x00, 0x00, 0x0D, 0x08, 0x19, 0x07, 0x90, 0x38, 0x08,
0x00, 0x00, 0x0B, 0x08, 0x5D, 0x5D, 0x0E, 0x0C, 0x5D, 0x5D, 0x0C, 0x08,
0x08, 0x08, 0x0D, 0x0C, 0x00, 0x00, 0x0D, 0x0C, 0x14, 0x14, 0x16, 0x08,
0x19, 0x06, 0x2C, 0x19, 0x56, 0x90, 0x38, 0x19, 0x04, 0x30, 0x19, 0x0C,
0x90, 0x38, 0x35, 0x35, 0x35, 0x35, 0x19, 0x04, 0x04, 0x19, 0x81, 0x24,
0x90, 0x38, 0x10, 0x19, 0x05, 0xA0, 0x4A, 0x19, 0x06, 0x06, 0x19, 0x0C,
0x0C, 0x19, 0x08, 0x08, 0x19, 0x37, 0x90, 0x38, 0x19, 0x08, 0x18, 0x80,
0x01, 0x00, 0x00, 0x40, 0x19, 0x82, 0x34, 0x90, 0x38, 0x19, 0x08, 0x12,
0x19, 0x81, 0x14, 0x90, 0x38, 0x19, 0x05, 0x82, 0x74, 0x19, 0x18, 0x90,
0x38, 0x20, 0x19, 0x32, 0x90, 0x38, 0x19, 0x08, 0x10, 0x19, 0x0C, 0x90,
0x38, 0x01, 0x19, 0x49, 0x90, 0x38, 0x80, 0x2A, 0x19, 0x06, 0x84, 0x20,
0x19, 0x95, 0x3E, 0xA0, 0x70, 0x19, 0x83, 0x2C, 0x90, 0x38, 0x14, 0x14,
0x19, 0x4D, 0x90, 0x38, 0x19, 0x05, 0x8A, 0x08, 0x19, 0x87, 0x2A, 0x90,
0x38, 0x19, 0x84, 0x30, 0xA0, 0x70, 0x19, 0x84, 0x7A, 0x90, 0x38, 0x32,
0x32, 0x32, 0x32, 0x19, 0x04, 0x04, 0x19, 0x54, 0x90, 0x38, 0x18, 0x00,
0x0F, 0x19, 0x15, 0x90, 0x38, 0x19, 0x08, 0x18, 0x48, 0x00, 0x44, 0x00,
0x45, 0x00, 0x44, 0x00, 0x47, 0x19, 0x07, 0x90, 0x20, 0x0D, 0x19, 0x05,
0x83, 0x0E, 0x0D, 0x19, 0x18, 0x18, 0x00, 0x78, 0x00, 0x78, 0x19, 0x04,
0x04, 0x19, 0x08, 0x08, 0x19, 0x10, 0x10, 0x00, 0x18, 0x19, 0x05, 0x5A,
0x19, 0x04, 0x5C, 0x19, 0x06, 0x90, 0x38, 0x18, 0x19, 0x8B, 0x57, 0x90,
0x38, 0x19, 0x81, 0x6F, 0xC1, 0x60, 0x19, 0x8D, 0x31, 0xA0, 0x70, 0x19,
0x82, 0x18, 0xD2, 0x18, 0x19, 0x04, 0x34, 0x19, 0x82, 0x00, 0xD2, 0x18,
0x19, 0x82, 0x03, 0x90, 0x38, 0x19, 0x84, 0x1D, 0xD2, 0x18, 0x19, 0x08,
0x83, 0x7C, 0x19, 0x85, 0x16, 0xD2, 0x18, 0x19, 0x82, 0x76, 0xB1, 0x28,
0x19, 0x6F, 0x90, 0x38, 0x19, 0x81, 0x71, 0xA0, 0x70, 0x19, 0x50, 0xB1,
0x28, 0x19, 0x20, 0x90, 0x38, 0x19, 0x84, 0x54, 0xB1, 0x28, 0x19, 0x10,
0x90, 0x38, 0x19, 0x87, 0x04, 0xA0, 0x70, 0x19, 0x81, 0x6F, 0x90, 0x38,
0x19, 0x81, 0x15, 0xA0, 0x70, 0x19, 0x81, 0x2C, 0xC1, 0x60, 0x19, 0x57,
0x90, 0x38, 0x19, 0x8C, 0x51, 0xA0, 0x70, 0x06, 0x1B, 0x04, 0x1C, 0x07,
0x03, 0x05, 0x02, 0x00, 0x25, 0x25, 0x03, 0x00, 0x1E, 0x1D, 0x08, 0x0D,
0x0A, 0x0C, 0x09, 0x0B, 0x26, 0x26, 0x05, 0x02, 0x04, 0x03, 0x05, 0x00,
0x06, 0x1C, 0x1B, 0x07, 0x25, 0x25, 0x07, 0x0A, 0x0B, 0x1D, 0x0C, 0x0D,
0x09, 0x00, 0x08, 0x1E, 0x26, 0x26, 0x09, 0x24, 0x06, 0x08, 0x2A, 0x19,
0x82, 0x0C, 0xA0, 0x70, 0x10, 0x00, 0x14, 0x00, 0x0B, 0x00, 0x13, 0x19,
0x18, 0x18, 0x00, 0x47, 0x00, 0x45, 0x00, 0x4F, 0x00, 0x4D, 0x00, 0x46,
0x00, 0x46, 0x00, 0x48, 0x00, 0x48, 0x00, 0x08, 0x00, 0x0C, 0x00, 0x0C,
0x00, 0x0B, 0x19, 0x18, 0x18, 0x19, 0x21, 0x90, 0x38, 0x10, 0x19, 0x05,
0x5A, 0x19, 0x04, 0x5C, 0x19, 0x04, 0x5E, 0x13, 0x19, 0x13, 0x8D, 0x5D,
0x19, 0x78, 0xA0, 0x70, 0x28, 0x40, 0xFF, 0x9F, 0x9F, 0x19, 0x1D, 0x90,
0x38, 0x57, 0x21, 0x03, 0x64, 0x67, 0x04, 0x32, 0x51, 0x21, 0x56, 0x73,
0x04, 0x12, 0x60, 0x35, 0x47, 0x73, 0x56, 0x04, 0x12, 0x10, 0x72, 0x65,
0x43, 0x37, 0x21, 0x40, 0x65, 0x64, 0x21, 0x30, 0x57, 0x19, 0x3E, 0x90,
0x38, 0x9F, 0x19, 0x06, 0x90, 0x38, 0xCF, 0x33, 0x19, 0x54, 0x90, 0x38,
0x10, 0x08, 0x01, 0x03, 0x00, 0x50, 0x00, 0x40, 0x01, 0x19, 0x06, 0x90,
0x38, 0x08, 0x29, 0x32, 0x93, 0xA5, 0x54, 0x4A, 0x6B, 0x76, 0x87, 0x19,
0x82, 0x29, 0xA0, 0x70, 0xCB, 0xFA, 0xE4, 0xD3, 0xFE, 0x19, 0x82, 0x3A,
0x90, 0x38, 0x9C, 0x19, 0x84, 0x6F, 0xD2, 0x18, 0x19, 0x82, 0x60, 0xB1,
0x28, 0x19, 0x85, 0x44, 0xD2, 0x18, 0x19, 0x83, 0x48, 0xB1, 0x28
};
static const uint32_t sdram_params_index_table_erista[28] = {
0,
1,
2,
3,
4,
5,
6,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
};
static const uint32_t sdram_params_index_table_mariko[28] = {
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0,
1,
2,
3,
4,
1,
2,
3,
4,
5,
6,
7,
6,
8,
9,
0xA,
7,
6,
0xB,
0xB,
0xB,
};

933
fusee/fusee-primary/src/sdram_param_t210.h
View file

@ -1,933 +0,0 @@
/*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* See file CREDITS for list of people who contributed to this
* project.
*/
/**
* Defines the SDRAM parameter structure.
*
* Note that PLLM is used by EMC.
*/
#ifndef _SDRAM_PARAM_T210_H_
#define _SDRAM_PARAM_T210_H_
#include <stdint.h>
#define MEMORY_TYPE_NONE 0
#define MEMORY_TYPE_DDR 0
#define MEMORY_TYPE_LPDDR 0
#define MEMORY_TYPE_DDR2 0
#define MEMORY_TYPE_LPDDR2 1
#define MEMORY_TYPE_DDR3 2
#define MEMORY_TYPE_LPDDR4 3
/**
* Defines the SDRAM parameter structure
*/
typedef struct _sdram_params
{
/* Specifies the type of memory device */
uint32_t memory_type;
/* MC/EMC clock source configuration */
/* Specifies the M value for PllM */
uint32_t pllm_input_divider;
/* Specifies the N value for PllM */
uint32_t pllm_feedback_divider;
/* Specifies the time to wait for PLLM to lock (in microseconds) */
uint32_t pllm_stable_time;
/* Specifies misc. control bits */
uint32_t pllm_setup_control;
/* Specifies the P value for PLLM */
uint32_t pllm_post_divider;
/* Specifies value for Charge Pump Gain Control */
uint32_t pllm_kcp;
/* Specifies VCO gain */
uint32_t pllm_kvco;
/* Spare BCT param */
uint32_t emc_bct_spare0;
/* Spare BCT param */
uint32_t emc_bct_spare1;
/* Spare BCT param */
uint32_t emc_bct_spare2;
/* Spare BCT param */
uint32_t emc_bct_spare3;
/* Spare BCT param */
uint32_t emc_bct_spare4;
/* Spare BCT param */
uint32_t emc_bct_spare5;
/* Spare BCT param */
uint32_t emc_bct_spare6;
/* Spare BCT param */
uint32_t emc_bct_spare7;
/* Spare BCT param */
uint32_t emc_bct_spare8;
/* Spare BCT param */
uint32_t emc_bct_spare9;
/* Spare BCT param */
uint32_t emc_bct_spare10;
/* Spare BCT param */
uint32_t emc_bct_spare11;
/* Spare BCT param */
uint32_t emc_bct_spare12;
/* Spare BCT param */
uint32_t emc_bct_spare13;
/* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */
uint32_t emc_clock_source;
uint32_t emc_clock_source_dll;
/* Defines possible override for PLLLM_MISC2 */
uint32_t clk_rst_pllm_misc20_override;
/* enables override for PLLLM_MISC2 */
uint32_t clk_rst_pllm_misc20_override_enable;
/* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */
uint32_t clear_clock2_mc1;
/* Auto-calibration of EMC pads */
/* Specifies the value for EMC_AUTO_CAL_INTERVAL */
uint32_t emc_auto_cal_interval;
/*
* Specifies the value for EMC_AUTO_CAL_CONFIG
* Note: Trigger bits are set by the SDRAM code.
*/
uint32_t emc_auto_cal_config;
/* Specifies the value for EMC_AUTO_CAL_CONFIG2 */
uint32_t emc_auto_cal_config2;
/* Specifies the value for EMC_AUTO_CAL_CONFIG3 */
uint32_t emc_auto_cal_config3;
uint32_t emc_auto_cal_config4;
uint32_t emc_auto_cal_config5;
uint32_t emc_auto_cal_config6;
uint32_t emc_auto_cal_config7;
uint32_t emc_auto_cal_config8;
/* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */
uint32_t emc_auto_cal_vref_sel0;
uint32_t emc_auto_cal_vref_sel1;
/* Specifies the value for EMC_AUTO_CAL_CHANNEL */
uint32_t emc_auto_cal_channel;
/* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */
uint32_t emc_pmacro_auto_cal_cfg0;
uint32_t emc_pmacro_auto_cal_cfg1;
uint32_t emc_pmacro_auto_cal_cfg2;
uint32_t emc_pmacro_rx_term;
uint32_t emc_pmacro_dq_tx_drive;
uint32_t emc_pmacro_ca_tx_drive;
uint32_t emc_pmacro_cmd_tx_drive;
uint32_t emc_pmacro_auto_cal_common;
uint32_t emc_pmacro_zcrtl;
/*
* Specifies the time for the calibration
* to stabilize (in microseconds)
*/
uint32_t emc_auto_cal_wait;
uint32_t emc_xm2_comp_pad_ctrl;
uint32_t emc_xm2_comp_pad_ctrl2;
uint32_t emc_xm2_comp_pad_ctrl3;
/*
* DRAM size information
* Specifies the value for EMC_ADR_CFG
*/
uint32_t emc_adr_cfg;
/*
* Specifies the time to wait after asserting pin
* CKE (in microseconds)
*/
uint32_t emc_pin_program_wait;
/* Specifies the extra delay before/after pin RESET/CKE command */
uint32_t emc_pin_extra_wait;
uint32_t emc_pin_gpio_enable;
uint32_t emc_pin_gpio;
/*
* Specifies the extra delay after the first writing
* of EMC_TIMING_CONTROL
*/
uint32_t emc_timing_control_wait;
/* Timing parameters required for the SDRAM */
/* Specifies the value for EMC_RC */
uint32_t emc_rc;
/* Specifies the value for EMC_RFC */
uint32_t emc_rfc;
uint32_t emc_rfc_pb;
uint32_t emc_ref_ctrl2;
/* Specifies the value for EMC_RFC_SLR */
uint32_t emc_rfc_slr;
/* Specifies the value for EMC_RAS */
uint32_t emc_ras;
/* Specifies the value for EMC_RP */
uint32_t emc_rp;
/* Specifies the value for EMC_R2R */
uint32_t emc_r2r;
/* Specifies the value for EMC_W2W */
uint32_t emc_w2w;
/* Specifies the value for EMC_R2W */
uint32_t emc_r2w;
/* Specifies the value for EMC_W2R */
uint32_t emc_w2r;
/* Specifies the value for EMC_R2P */
uint32_t emc_r2p;
/* Specifies the value for EMC_W2P */
uint32_t emc_w2p;
/* Specifies the value for EMC_RD_RCD */
uint32_t emc_tppd;
uint32_t emc_ccdmw;
uint32_t emc_rd_rcd;
/* Specifies the value for EMC_WR_RCD */
uint32_t emc_wr_rcd;
/* Specifies the value for EMC_RRD */
uint32_t emc_rrd;
/* Specifies the value for EMC_REXT */
uint32_t emc_rext;
/* Specifies the value for EMC_WEXT */
uint32_t emc_wext;
/* Specifies the value for EMC_WDV */
uint32_t emc_wdv;
uint32_t emc_wdv_chk;
uint32_t emc_wsv;
uint32_t emc_wev;
/* Specifies the value for EMC_WDV_MASK */
uint32_t emc_wdv_mask;
uint32_t emc_ws_duration;
uint32_t emc_we_duration;
/* Specifies the value for EMC_QUSE */
uint32_t emc_quse;
/* Specifies the value for EMC_QUSE_WIDTH */
uint32_t emc_quse_width;
/* Specifies the value for EMC_IBDLY */
uint32_t emc_ibdly;
uint32_t emc_obdly;
/* Specifies the value for EMC_EINPUT */
uint32_t emc_einput;
/* Specifies the value for EMC_EINPUT_DURATION */
uint32_t emc_einput_duration;
/* Specifies the value for EMC_PUTERM_EXTRA */
uint32_t emc_puterm_extra;
/* Specifies the value for EMC_PUTERM_WIDTH */
uint32_t emc_puterm_width;
uint32_t emc_qrst;
uint32_t emc_qsafe;
uint32_t emc_rdv;
uint32_t emc_rdv_mask;
uint32_t emc_rdv_early;
uint32_t emc_rdv_early_mask;
/* Specifies the value for EMC_QPOP */
uint32_t emc_qpop;
/* Specifies the value for EMC_REFRESH */
uint32_t emc_refresh;
/* Specifies the value for EMC_BURST_REFRESH_NUM */
uint32_t emc_burst_refresh_num;
/* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */
uint32_t emc_prerefresh_req_cnt;
/* Specifies the value for EMC_PDEX2WR */
uint32_t emc_pdex2wr;
/* Specifies the value for EMC_PDEX2RD */
uint32_t emc_pdex2rd;
/* Specifies the value for EMC_PCHG2PDEN */
uint32_t emc_pchg2pden;
/* Specifies the value for EMC_ACT2PDEN */
uint32_t emc_act2pden;
/* Specifies the value for EMC_AR2PDEN */
uint32_t emc_ar2pden;
/* Specifies the value for EMC_RW2PDEN */
uint32_t emc_rw2pden;
uint32_t emc_cke2pden;
uint32_t emc_pdex2che;
uint32_t emc_pdex2mrr;
/* Specifies the value for EMC_TXSR */
uint32_t emc_txsr;
/* Specifies the value for EMC_TXSRDLL */
uint32_t emc_txsr_dll;
/* Specifies the value for EMC_TCKE */
uint32_t emc_tcke;
/* Specifies the value for EMC_TCKESR */
uint32_t emc_tckesr;
/* Specifies the value for EMC_TPD */
uint32_t emc_tpd;
/* Specifies the value for EMC_TFAW */
uint32_t emc_tfaw;
/* Specifies the value for EMC_TRPAB */
uint32_t emc_trpab;
/* Specifies the value for EMC_TCLKSTABLE */
uint32_t emc_tclkstable;
/* Specifies the value for EMC_TCLKSTOP */
uint32_t emc_tclkstop;
/* Specifies the value for EMC_TREFBW */
uint32_t emc_trefbw;
/* FBIO configuration values */
/* Specifies the value for EMC_FBIO_CFG5 */
uint32_t emc_fbio_cfg5;
/* Specifies the value for EMC_FBIO_CFG7 */
uint32_t emc_fbio_cfg7;
uint32_t emc_fbio_cfg8;
/* Command mapping for CMD brick 0 */
uint32_t emc_cmd_mapping_cmd0_0;
uint32_t emc_cmd_mapping_cmd0_1;
uint32_t emc_cmd_mapping_cmd0_2;
uint32_t emc_cmd_mapping_cmd1_0;
uint32_t emc_cmd_mapping_cmd1_1;
uint32_t emc_cmd_mapping_cmd1_2;
uint32_t emc_cmd_mapping_cmd2_0;
uint32_t emc_cmd_mapping_cmd2_1;
uint32_t emc_cmd_mapping_cmd2_2;
uint32_t emc_cmd_mapping_cmd3_0;
uint32_t emc_cmd_mapping_cmd3_1;
uint32_t emc_cmd_mapping_cmd3_2;
uint32_t emc_cmd_mapping_byte;
/* Specifies the value for EMC_FBIO_SPARE */
uint32_t emc_fbio_spare;
/* Specifies the value for EMC_CFG_RSV */
uint32_t emc_cfg_rsv;
/* MRS command values */
/* Specifies the value for EMC_MRS */
uint32_t emc_mrs;
/* Specifies the MP0 command to initialize mode registers */
uint32_t emc_emrs;
/* Specifies the MP2 command to initialize mode registers */
uint32_t emc_emrs2;
/* Specifies the MP3 command to initialize mode registers */
uint32_t emc_emrs3;
/* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */
uint32_t emc_mrw1;
/* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */
uint32_t emc_mrw2;
/* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */
uint32_t emc_mrw3;
/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
uint32_t emc_mrw4;
/* Specifies the programming to LPDDR4 Mode Register 3 at cold boot */
uint32_t emc_mrw6;
/* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */
uint32_t emc_mrw8;
/* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */
uint32_t emc_mrw9;
/* Specifies the programming to LPDDR4 Mode Register 12 at cold boot */
uint32_t emc_mrw10;
/* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */
uint32_t emc_mrw12;
/* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */
uint32_t emc_mrw13;
/* Specifies the programming to LPDDR4 Mode Register 22 at cold boot */
uint32_t emc_mrw14;
/*
* Specifies the programming to extra LPDDR2 Mode Register
* at cold boot
*/
uint32_t emc_mrw_extra;
/*
* Specifies the programming to extra LPDDR2 Mode Register
* at warm boot
*/
uint32_t emc_warm_boot_mrw_extra;
/*
* Specify the enable of extra Mode Register programming at
* warm boot
*/
uint32_t emc_warm_boot_extramode_reg_write_enable;
/*
* Specify the enable of extra Mode Register programming at
* cold boot
*/
uint32_t emc_extramode_reg_write_enable;
/* Specifies the EMC_MRW reset command value */
uint32_t emc_mrw_reset_command;
/* Specifies the EMC Reset wait time (in microseconds) */
uint32_t emc_mrw_reset_ninit_wait;
/* Specifies the value for EMC_MRS_WAIT_CNT */
uint32_t emc_mrs_wait_cnt;
/* Specifies the value for EMC_MRS_WAIT_CNT2 */
uint32_t emc_mrs_wait_cnt2;
/* EMC miscellaneous configurations */
/* Specifies the value for EMC_CFG */
uint32_t emc_cfg;
/* Specifies the value for EMC_CFG_2 */
uint32_t emc_cfg2;
/* Specifies the pipe bypass controls */
uint32_t emc_cfg_pipe;
uint32_t emc_cfg_pipe_clk;
uint32_t emc_fdpd_ctrl_cmd_no_ramp;
uint32_t emc_cfg_update;
/* Specifies the value for EMC_DBG */
uint32_t emc_dbg;
uint32_t emc_dbg_write_mux;
/* Specifies the value for EMC_CMDQ */
uint32_t emc_cmd_q;
/* Specifies the value for EMC_MC2EMCQ */
uint32_t emc_mc2emc_q;
/* Specifies the value for EMC_DYN_SELF_REF_CONTROL */
uint32_t emc_dyn_self_ref_control;
/* Specifies the value for MEM_INIT_DONE */
uint32_t ahb_arbitration_xbar_ctrl_meminit_done;
/* Specifies the value for EMC_CFG_DIG_DLL */
uint32_t emc_cfg_dig_dll;
uint32_t emc_cfg_dig_dll_1;
/* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */
uint32_t emc_cfg_dig_dll_period;
/* Specifies the value of *DEV_SELECTN of various EMC registers */
uint32_t emc_dev_select;
/* Specifies the value for EMC_SEL_DPD_CTRL */
uint32_t emc_sel_dpd_ctrl;
/* Pads trimmer delays */
uint32_t emc_fdpd_ctrl_dq;
uint32_t emc_fdpd_ctrl_cmd;
uint32_t emc_pmacro_ib_vref_dq_0;
uint32_t emc_pmacro_ib_vref_dq_1;
uint32_t emc_pmacro_ib_vref_dqs_0;
uint32_t emc_pmacro_ib_vref_dqs_1;
uint32_t emc_pmacro_ib_rxrt;
uint32_t emc_cfg_pipe1;
uint32_t emc_cfg_pipe2;
/* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */
uint32_t emc_pmacro_quse_ddll_rank0_0;
uint32_t emc_pmacro_quse_ddll_rank0_1;
uint32_t emc_pmacro_quse_ddll_rank0_2;
uint32_t emc_pmacro_quse_ddll_rank0_3;
uint32_t emc_pmacro_quse_ddll_rank0_4;
uint32_t emc_pmacro_quse_ddll_rank0_5;
uint32_t emc_pmacro_quse_ddll_rank1_0;
uint32_t emc_pmacro_quse_ddll_rank1_1;
uint32_t emc_pmacro_quse_ddll_rank1_2;
uint32_t emc_pmacro_quse_ddll_rank1_3;
uint32_t emc_pmacro_quse_ddll_rank1_4;
uint32_t emc_pmacro_quse_ddll_rank1_5;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_0;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_1;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_2;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_3;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_4;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_5;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_0;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_1;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_2;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_3;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_0;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_1;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_2;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_3;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_0;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_1;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_2;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_3;
uint32_t emc_pmacro_ddll_long_cmd_0;
uint32_t emc_pmacro_ddll_long_cmd_1;
uint32_t emc_pmacro_ddll_long_cmd_2;
uint32_t emc_pmacro_ddll_long_cmd_3;
uint32_t emc_pmacro_ddll_long_cmd_4;
uint32_t emc_pmacro_ddll_short_cmd_0;
uint32_t emc_pmacro_ddll_short_cmd_1;
uint32_t emc_pmacro_ddll_short_cmd_2;
/*
* Specifies the delay after asserting CKE pin during a WarmBoot0
* sequence (in microseconds)
*/
uint32_t warm_boot_wait;
/* Specifies the value for EMC_ODT_WRITE */
uint32_t emc_odt_write;
/* Periodic ZQ calibration */
/*
* Specifies the value for EMC_ZCAL_INTERVAL
* Value 0 disables ZQ calibration
*/
uint32_t emc_zcal_interval;
/* Specifies the value for EMC_ZCAL_WAIT_CNT */
uint32_t emc_zcal_wait_cnt;
/* Specifies the value for EMC_ZCAL_MRW_CMD */
uint32_t emc_zcal_mrw_cmd;
/* DRAM initialization sequence flow control */
/* Specifies the MRS command value for resetting DLL */
uint32_t emc_mrs_reset_dll;
/* Specifies the command for ZQ initialization of device 0 */
uint32_t emc_zcal_init_dev0;
/* Specifies the command for ZQ initialization of device 1 */
uint32_t emc_zcal_init_dev1;
/*
* Specifies the wait time after programming a ZQ initialization
* command (in microseconds)
*/
uint32_t emc_zcal_init_wait;
/*
* Specifies the enable for ZQ calibration at cold boot [bit 0]
* and warm boot [bit 1]
*/
uint32_t emc_zcal_warm_cold_boot_enables;
/*
* Specifies the MRW command to LPDDR2 for ZQ calibration
* on warmboot
*/
/* Is issued to both devices separately */
uint32_t emc_mrw_lpddr2zcal_warm_boot;
/*
* Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
* Is issued to both devices separately
*/
uint32_t emc_zqcal_ddr3_warm_boot;
uint32_t emc_zqcal_lpddr4_warm_boot;
/*
* Specifies the wait time for ZQ calibration on warmboot
* (in microseconds)
*/
uint32_t emc_zcal_warm_boot_wait;
/*
* Specifies the enable for DRAM Mode Register programming
* at warm boot
*/
uint32_t emc_mrs_warm_boot_enable;
/*
* Specifies the wait time after sending an MRS DLL reset command
* in microseconds)
*/
uint32_t emc_mrs_reset_dll_wait;
/* Specifies the extra MRS command to initialize mode registers */
uint32_t emc_mrs_extra;
/* Specifies the extra MRS command at warm boot */
uint32_t emc_warm_boot_mrs_extra;
/* Specifies the EMRS command to enable the DDR2 DLL */
uint32_t emc_emrs_ddr2_dll_enable;
/* Specifies the MRS command to reset the DDR2 DLL */
uint32_t emc_mrs_ddr2_dll_reset;
/* Specifies the EMRS command to set OCD calibration */
uint32_t emc_emrs_ddr2_ocd_calib;
/*
* Specifies the wait between initializing DDR and setting OCD
* calibration (in microseconds)
*/
uint32_t emc_ddr2_wait;
/* Specifies the value for EMC_CLKEN_OVERRIDE */
uint32_t emc_clken_override;
/*
* Specifies LOG2 of the extra refresh numbers after booting
* Program 0 to disable
*/
uint32_t emc_extra_refresh_num;
/* Specifies the master override for all EMC clocks */
uint32_t emc_clken_override_allwarm_boot;
/* Specifies the master override for all MC clocks */
uint32_t mc_clken_override_allwarm_boot;
/* Specifies digital dll period, choosing between 4 to 64 ms */
uint32_t emc_cfg_dig_dll_period_warm_boot;
/* Pad controls */
/* Specifies the value for PMC_VDDP_SEL */
uint32_t pmc_vddp_sel;
/* Specifies the wait time after programming PMC_VDDP_SEL */
uint32_t pmc_vddp_sel_wait;
/* Specifies the value for PMC_DDR_PWR */
uint32_t pmc_ddr_pwr;
/* Specifies the value for PMC_DDR_CFG */
uint32_t pmc_ddr_cfg;
/* Specifies the value for PMC_IO_DPD3_REQ */
uint32_t pmc_io_dpd3_req;
/* Specifies the wait time after programming PMC_IO_DPD3_REQ */
uint32_t pmc_io_dpd3_req_wait;
uint32_t pmc_io_dpd4_req_wait;
/* Specifies the value for PMC_REG_SHORT */
uint32_t pmc_reg_short;
/* Specifies the value for PMC_NO_IOPOWER */
uint32_t pmc_no_io_power;
uint32_t pmc_ddr_ctrl_wait;
uint32_t pmc_ddr_ctrl;
/* Specifies the value for EMC_ACPD_CONTROL */
uint32_t emc_acpd_control;
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */
uint32_t emc_swizzle_rank0_byte0;
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */
uint32_t emc_swizzle_rank0_byte1;
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */
uint32_t emc_swizzle_rank0_byte2;
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */
uint32_t emc_swizzle_rank0_byte3;
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */
uint32_t emc_swizzle_rank1_byte0;
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */
uint32_t emc_swizzle_rank1_byte1;
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */
uint32_t emc_swizzle_rank1_byte2;
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */
uint32_t emc_swizzle_rank1_byte3;
/* Specifies the value for EMC_TXDSRVTTGEN */
uint32_t emc_txdsrvttgen;
/* Specifies the value for EMC_DATA_BRLSHFT_0 */
uint32_t emc_data_brlshft0;
uint32_t emc_data_brlshft1;
uint32_t emc_dqs_brlshft0;
uint32_t emc_dqs_brlshft1;
uint32_t emc_cmd_brlshft0;
uint32_t emc_cmd_brlshft1;
uint32_t emc_cmd_brlshft2;
uint32_t emc_cmd_brlshft3;
uint32_t emc_quse_brlshft0;
uint32_t emc_quse_brlshft1;
uint32_t emc_quse_brlshft2;
uint32_t emc_quse_brlshft3;
uint32_t emc_dll_cfg0;
uint32_t emc_dll_cfg1;
uint32_t emc_pmc_scratch1;
uint32_t emc_pmc_scratch2;
uint32_t emc_pmc_scratch3;
uint32_t emc_pmacro_pad_cfg_ctrl;
uint32_t emc_pmacro_vttgen_ctrl0;
uint32_t emc_pmacro_vttgen_ctrl1;
uint32_t emc_pmacro_vttgen_ctrl2;
uint32_t emc_pmacro_brick_ctrl_rfu1;
uint32_t emc_pmacro_cmd_brick_ctrl_fdpd;
uint32_t emc_pmacro_brick_ctrl_rfu2;
uint32_t emc_pmacro_data_brick_ctrl_fdpd;
uint32_t emc_pmacro_bg_bias_ctrl0;
uint32_t emc_pmacro_data_pad_rx_ctrl;
uint32_t emc_pmacro_cmd_pad_rx_ctrl;
uint32_t emc_pmacro_data_rx_term_mode;
uint32_t emc_pmacro_cmd_rx_term_mode;
uint32_t emc_pmacro_data_pad_tx_ctrl;
uint32_t emc_pmacro_common_pad_tx_ctrl;
uint32_t emc_pmacro_cmd_pad_tx_ctrl;
uint32_t emc_cfg3;
uint32_t emc_pmacro_tx_pwrd0;
uint32_t emc_pmacro_tx_pwrd1;
uint32_t emc_pmacro_tx_pwrd2;
uint32_t emc_pmacro_tx_pwrd3;
uint32_t emc_pmacro_tx_pwrd4;
uint32_t emc_pmacro_tx_pwrd5;
uint32_t emc_config_sample_delay;
uint32_t emc_pmacro_brick_mapping0;
uint32_t emc_pmacro_brick_mapping1;
uint32_t emc_pmacro_brick_mapping2;
uint32_t emc_pmacro_tx_sel_clk_src0;
uint32_t emc_pmacro_tx_sel_clk_src1;
uint32_t emc_pmacro_tx_sel_clk_src2;
uint32_t emc_pmacro_tx_sel_clk_src3;
uint32_t emc_pmacro_tx_sel_clk_src4;
uint32_t emc_pmacro_tx_sel_clk_src5;
uint32_t emc_pmacro_ddll_bypass;
uint32_t emc_pmacro_ddll_pwrd0;
uint32_t emc_pmacro_ddll_pwrd1;
uint32_t emc_pmacro_ddll_pwrd2;
uint32_t emc_pmacro_cmd_ctrl0;
uint32_t emc_pmacro_cmd_ctrl1;
uint32_t emc_pmacro_cmd_ctrl2;
/* DRAM size information */
/* Specifies the value for MC_EMEM_ADR_CFG */
uint32_t mc_emem_adr_cfg;
/* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */
uint32_t mc_emem_adr_cfg_dev0;
/* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */
uint32_t mc_emem_adr_cfg_dev1;
uint32_t mc_emem_adr_cfg_channel_mask;
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */
uint32_t mc_emem_adr_cfg_bank_mask0;
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */
uint32_t mc_emem_adr_cfg_bank_mask1;
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */
uint32_t mc_emem_adr_cfg_bank_mask2;
/*
* Specifies the value for MC_EMEM_CFG which holds the external memory
* size (in KBytes)
*/
uint32_t mc_emem_cfg;
/* MC arbitration configuration */
/* Specifies the value for MC_EMEM_ARB_CFG */
uint32_t mc_emem_arb_cfg;
/* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */
uint32_t mc_emem_arb_outstanding_req;
uint32_t emc_emem_arb_refpb_hp_ctrl;
uint32_t emc_emem_arb_refpb_bank_ctrl;
/* Specifies the value for MC_EMEM_ARB_TIMING_RCD */
uint32_t mc_emem_arb_timing_rcd;
/* Specifies the value for MC_EMEM_ARB_TIMING_RP */
uint32_t mc_emem_arb_timing_rp;
/* Specifies the value for MC_EMEM_ARB_TIMING_RC */
uint32_t mc_emem_arb_timing_rc;
/* Specifies the value for MC_EMEM_ARB_TIMING_RAS */
uint32_t mc_emem_arb_timing_ras;
/* Specifies the value for MC_EMEM_ARB_TIMING_FAW */
uint32_t mc_emem_arb_timing_faw;
/* Specifies the value for MC_EMEM_ARB_TIMING_RRD */
uint32_t mc_emem_arb_timing_rrd;
/* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */
uint32_t mc_emem_arb_timing_rap2pre;
/* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */
uint32_t mc_emem_arb_timing_wap2pre;
/* Specifies the value for MC_EMEM_ARB_TIMING_R2R */
uint32_t mc_emem_arb_timing_r2r;
/* Specifies the value for MC_EMEM_ARB_TIMING_W2W */
uint32_t mc_emem_arb_timing_w2w;
/* Specifies the value for MC_EMEM_ARB_TIMING_R2W */
uint32_t mc_emem_arb_timing_r2w;
/* Specifies the value for MC_EMEM_ARB_TIMING_W2R */
uint32_t mc_emem_arb_timing_w2r;
uint32_t mc_emem_arb_timing_rfcpb;
/* Specifies the value for MC_EMEM_ARB_DA_TURNS */
uint32_t mc_emem_arb_da_turns;
/* Specifies the value for MC_EMEM_ARB_DA_COVERS */
uint32_t mc_emem_arb_da_covers;
/* Specifies the value for MC_EMEM_ARB_MISC0 */
uint32_t mc_emem_arb_misc0;
/* Specifies the value for MC_EMEM_ARB_MISC1 */
uint32_t mc_emem_arb_misc1;
uint32_t mc_emem_arb_misc2;
/* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */
uint32_t mc_emem_arb_ring1_throttle;
/* Specifies the value for MC_EMEM_ARB_OVERRIDE */
uint32_t mc_emem_arb_override;
/* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */
uint32_t mc_emem_arb_override1;
/* Specifies the value for MC_EMEM_ARB_RSV */
uint32_t mc_emem_arb_rsv;
uint32_t mc_da_cfg0;
uint32_t mc_emem_arb_timing_ccdmw;
/* Specifies the value for MC_CLKEN_OVERRIDE */
uint32_t mc_clken_override;
/* Specifies the value for MC_STAT_CONTROL */
uint32_t mc_stat_control;
/* Specifies the value for MC_VIDEO_PROTECT_BOM */
uint32_t mc_video_protect_bom;
/* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */
uint32_t mc_video_protect_bom_adr_hi;
/* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */
uint32_t mc_video_protect_size_mb;
/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */
uint32_t mc_video_protect_vpr_override;
/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */
uint32_t mc_video_protect_vpr_override1;
/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */
uint32_t mc_video_protect_gpu_override0;
/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */
uint32_t mc_video_protect_gpu_override1;
/* Specifies the value for MC_SEC_CARVEOUT_BOM */
uint32_t mc_sec_carveout_bom;
/* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */
uint32_t mc_sec_carveout_adr_hi;
/* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */
uint32_t mc_sec_carveout_size_mb;
/* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */
uint32_t mc_video_protect_write_access;
/* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */
uint32_t mc_sec_carveout_protect_write_access;
uint32_t mc_generalized_carveout1_bom;
uint32_t mc_generalized_carveout1_bom_hi;
uint32_t mc_generalized_carveout1_size_128kb;
uint32_t mc_generalized_carveout1_access0;
uint32_t mc_generalized_carveout1_access1;
uint32_t mc_generalized_carveout1_access2;
uint32_t mc_generalized_carveout1_access3;
uint32_t mc_generalized_carveout1_access4;
uint32_t mc_generalized_carveout1_force_internal_access0;
uint32_t mc_generalized_carveout1_force_internal_access1;
uint32_t mc_generalized_carveout1_force_internal_access2;
uint32_t mc_generalized_carveout1_force_internal_access3;
uint32_t mc_generalized_carveout1_force_internal_access4;
uint32_t mc_generalized_carveout1_cfg0;
uint32_t mc_generalized_carveout2_bom;
uint32_t mc_generalized_carveout2_bom_hi;
uint32_t mc_generalized_carveout2_size_128kb;
uint32_t mc_generalized_carveout2_access0;
uint32_t mc_generalized_carveout2_access1;
uint32_t mc_generalized_carveout2_access2;
uint32_t mc_generalized_carveout2_access3;
uint32_t mc_generalized_carveout2_access4;
uint32_t mc_generalized_carveout2_force_internal_access0;
uint32_t mc_generalized_carveout2_force_internal_access1;
uint32_t mc_generalized_carveout2_force_internal_access2;
uint32_t mc_generalized_carveout2_force_internal_access3;
uint32_t mc_generalized_carveout2_force_internal_access4;
uint32_t mc_generalized_carveout2_cfg0;
uint32_t mc_generalized_carveout3_bom;
uint32_t mc_generalized_carveout3_bom_hi;
uint32_t mc_generalized_carveout3_size_128kb;
uint32_t mc_generalized_carveout3_access0;
uint32_t mc_generalized_carveout3_access1;
uint32_t mc_generalized_carveout3_access2;
uint32_t mc_generalized_carveout3_access3;
uint32_t mc_generalized_carveout3_access4;
uint32_t mc_generalized_carveout3_force_internal_access0;
uint32_t mc_generalized_carveout3_force_internal_access1;
uint32_t mc_generalized_carveout3_force_internal_access2;
uint32_t mc_generalized_carveout3_force_internal_access3;
uint32_t mc_generalized_carveout3_force_internal_access4;
uint32_t mc_generalized_carveout3_cfg0;
uint32_t mc_generalized_carveout4_bom;
uint32_t mc_generalized_carveout4_bom_hi;
uint32_t mc_generalized_carveout4_size_128kb;
uint32_t mc_generalized_carveout4_access0;
uint32_t mc_generalized_carveout4_access1;
uint32_t mc_generalized_carveout4_access2;
uint32_t mc_generalized_carveout4_access3;
uint32_t mc_generalized_carveout4_access4;
uint32_t mc_generalized_carveout4_force_internal_access0;
uint32_t mc_generalized_carveout4_force_internal_access1;
uint32_t mc_generalized_carveout4_force_internal_access2;
uint32_t mc_generalized_carveout4_force_internal_access3;
uint32_t mc_generalized_carveout4_force_internal_access4;
uint32_t mc_generalized_carveout4_cfg0;
uint32_t mc_generalized_carveout5_bom;
uint32_t mc_generalized_carveout5_bom_hi;
uint32_t mc_generalized_carveout5_size_128kb;
uint32_t mc_generalized_carveout5_access0;
uint32_t mc_generalized_carveout5_access1;
uint32_t mc_generalized_carveout5_access2;
uint32_t mc_generalized_carveout5_access3;
uint32_t mc_generalized_carveout5_access4;
uint32_t mc_generalized_carveout5_force_internal_access0;
uint32_t mc_generalized_carveout5_force_internal_access1;
uint32_t mc_generalized_carveout5_force_internal_access2;
uint32_t mc_generalized_carveout5_force_internal_access3;
uint32_t mc_generalized_carveout5_force_internal_access4;
uint32_t mc_generalized_carveout5_cfg0;
/* Specifies enable for CA training */
uint32_t emc_ca_training_enable;
/* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */
uint32_t swizzle_rank_byte_encode;
/* Specifies enable and offset for patched boot rom write */
uint32_t boot_rom_patch_control;
/* Specifies data for patched boot rom write */
uint32_t boot_rom_patch_data;
/* Specifies the value for MC_MTS_CARVEOUT_BOM */
uint32_t mc_mts_carveout_bom;
/* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */
uint32_t mc_mts_carveout_adr_hi;
/* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */
uint32_t mc_mts_carveout_size_mb;
/* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */
uint32_t mc_mts_carveout_reg_ctrl;
} sdram_params_t;
#endif

964
fusee/fusee-primary/src/sdram_param_t210_lp0.h
View file

@ -1,964 +0,0 @@
/*
* Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved.
* Copyright 2014 Google Inc.
* Copyright (c) 2018 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
/**
* Defines the SDRAM parameter structure.
*
* Note that PLLM is used by EMC. The field names are in camel case to ease
* directly converting BCT config files (*.cfg) into C structure.
*/
#ifndef __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__
#define __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__
#include <stdint.h>
enum
{
/* Specifies the memory type to be undefined */
NvBootMemoryType_None = 0,
/* Specifies the memory type to be DDR SDRAM */
NvBootMemoryType_Ddr = 0,
/* Specifies the memory type to be LPDDR SDRAM */
NvBootMemoryType_LpDdr = 0,
/* Specifies the memory type to be DDR2 SDRAM */
NvBootMemoryType_Ddr2 = 0,
/* Specifies the memory type to be LPDDR2 SDRAM */
NvBootMemoryType_LpDdr2,
/* Specifies the memory type to be DDR3 SDRAM */
NvBootMemoryType_Ddr3,
/* Specifies the memory type to be LPDDR4 SDRAM */
NvBootMemoryType_LpDdr4,
NvBootMemoryType_Num,
/* Specifies an entry in the ram_code table that's not in use */
NvBootMemoryType_Unused = 0X7FFFFFF,
};
/**
* Defines the SDRAM parameter structure
*/
struct sdram_params
{
/* Specifies the type of memory device */
uint32_t MemoryType;
/* MC/EMC clock source configuration */
/* Specifies the M value for PllM */
uint32_t PllMInputDivider;
/* Specifies the N value for PllM */
uint32_t PllMFeedbackDivider;
/* Specifies the time to wait for PLLM to lock (in microseconds) */
uint32_t PllMStableTime;
/* Specifies misc. control bits */
uint32_t PllMSetupControl;
/* Specifies the P value for PLLM */
uint32_t PllMPostDivider;
/* Specifies value for Charge Pump Gain Control */
uint32_t PllMKCP;
/* Specifies VCO gain */
uint32_t PllMKVCO;
/* Spare BCT param */
uint32_t EmcBctSpare0;
/* Spare BCT param */
uint32_t EmcBctSpare1;
/* Spare BCT param */
uint32_t EmcBctSpare2;
/* Spare BCT param */
uint32_t EmcBctSpare3;
/* Spare BCT param */
uint32_t EmcBctSpare4;
/* Spare BCT param */
uint32_t EmcBctSpare5;
/* Spare BCT param */
uint32_t EmcBctSpare6;
/* Spare BCT param */
uint32_t EmcBctSpare7;
/* Spare BCT param */
uint32_t EmcBctSpare8;
/* Spare BCT param */
uint32_t EmcBctSpare9;
/* Spare BCT param */
uint32_t EmcBctSpare10;
/* Spare BCT param */
uint32_t EmcBctSpare11;
/* Spare BCT param */
uint32_t EmcBctSpare12;
/* Spare BCT param */
uint32_t EmcBctSpare13;
/* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */
uint32_t EmcClockSource;
uint32_t EmcClockSourceDll;
/* Defines possible override for PLLLM_MISC2 */
uint32_t ClkRstControllerPllmMisc2Override;
/* enables override for PLLLM_MISC2 */
uint32_t ClkRstControllerPllmMisc2OverrideEnable;
/* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */
uint32_t ClearClk2Mc1;
/* Auto-calibration of EMC pads */
/* Specifies the value for EMC_AUTO_CAL_INTERVAL */
uint32_t EmcAutoCalInterval;
/*
* Specifies the value for EMC_AUTO_CAL_CONFIG
* Note: Trigger bits are set by the SDRAM code.
*/
uint32_t EmcAutoCalConfig;
/* Specifies the value for EMC_AUTO_CAL_CONFIG2 */
uint32_t EmcAutoCalConfig2;
/* Specifies the value for EMC_AUTO_CAL_CONFIG3 */
uint32_t EmcAutoCalConfig3;
/* Specifies the values for EMC_AUTO_CAL_CONFIG4-8 */
uint32_t EmcAutoCalConfig4;
uint32_t EmcAutoCalConfig5;
uint32_t EmcAutoCalConfig6;
uint32_t EmcAutoCalConfig7;
uint32_t EmcAutoCalConfig8;
/* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */
uint32_t EmcAutoCalVrefSel0;
uint32_t EmcAutoCalVrefSel1;
/* Specifies the value for EMC_AUTO_CAL_CHANNEL */
uint32_t EmcAutoCalChannel;
/* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */
uint32_t EmcPmacroAutocalCfg0;
uint32_t EmcPmacroAutocalCfg1;
uint32_t EmcPmacroAutocalCfg2;
uint32_t EmcPmacroRxTerm;
uint32_t EmcPmacroDqTxDrv;
uint32_t EmcPmacroCaTxDrv;
uint32_t EmcPmacroCmdTxDrv;
uint32_t EmcPmacroAutocalCfgCommon;
uint32_t EmcPmacroZctrl;
/*
* Specifies the time for the calibration
* to stabilize (in microseconds)
*/
uint32_t EmcAutoCalWait;
uint32_t EmcXm2CompPadCtrl;
uint32_t EmcXm2CompPadCtrl2;
uint32_t EmcXm2CompPadCtrl3;
/*
* DRAM size information
* Specifies the value for EMC_ADR_CFG
*/
uint32_t EmcAdrCfg;
/*
* Specifies the time to wait after asserting pin
* CKE (in microseconds)
*/
uint32_t EmcPinProgramWait;
/* Specifies the extra delay before/after pin RESET/CKE command */
uint32_t EmcPinExtraWait;
uint32_t EmcPinGpioEn;
uint32_t EmcPinGpio;
/*
* Specifies the extra delay after the first writing
* of EMC_TIMING_CONTROL
*/
uint32_t EmcTimingControlWait;
/* Timing parameters required for the SDRAM */
/* Specifies the value for EMC_RC */
uint32_t EmcRc;
/* Specifies the value for EMC_RFC */
uint32_t EmcRfc;
/* Specifies the value for EMC_RFC_PB */
uint32_t EmcRfcPb;
/* Specifies the value for EMC_RFC_CTRL2 */
uint32_t EmcRefctrl2;
/* Specifies the value for EMC_RFC_SLR */
uint32_t EmcRfcSlr;
/* Specifies the value for EMC_RAS */
uint32_t EmcRas;
/* Specifies the value for EMC_RP */
uint32_t EmcRp;
/* Specifies the value for EMC_R2R */
uint32_t EmcR2r;
/* Specifies the value for EMC_W2W */
uint32_t EmcW2w;
/* Specifies the value for EMC_R2W */
uint32_t EmcR2w;
/* Specifies the value for EMC_W2R */
uint32_t EmcW2r;
/* Specifies the value for EMC_R2P */
uint32_t EmcR2p;
/* Specifies the value for EMC_W2P */
uint32_t EmcW2p;
uint32_t EmcTppd;
uint32_t EmcCcdmw;
/* Specifies the value for EMC_RD_RCD */
uint32_t EmcRdRcd;
/* Specifies the value for EMC_WR_RCD */
uint32_t EmcWrRcd;
/* Specifies the value for EMC_RRD */
uint32_t EmcRrd;
/* Specifies the value for EMC_REXT */
uint32_t EmcRext;
/* Specifies the value for EMC_WEXT */
uint32_t EmcWext;
/* Specifies the value for EMC_WDV */
uint32_t EmcWdv;
uint32_t EmcWdvChk;
uint32_t EmcWsv;
uint32_t EmcWev;
/* Specifies the value for EMC_WDV_MASK */
uint32_t EmcWdvMask;
uint32_t EmcWsDuration;
uint32_t EmcWeDuration;
/* Specifies the value for EMC_QUSE */
uint32_t EmcQUse;
/* Specifies the value for EMC_QUSE_WIDTH */
uint32_t EmcQuseWidth;
/* Specifies the value for EMC_IBDLY */
uint32_t EmcIbdly;
/* Specifies the value for EMC_OBDLY */
uint32_t EmcObdly;
/* Specifies the value for EMC_EINPUT */
uint32_t EmcEInput;
/* Specifies the value for EMC_EINPUT_DURATION */
uint32_t EmcEInputDuration;
/* Specifies the value for EMC_PUTERM_EXTRA */
uint32_t EmcPutermExtra;
/* Specifies the value for EMC_PUTERM_WIDTH */
uint32_t EmcPutermWidth;
/* Specifies the value for EMC_PUTERM_ADJ */
////uint32_t EmcPutermAdj;
/* Specifies the value for EMC_QRST */
uint32_t EmcQRst;
/* Specifies the value for EMC_QSAFE */
uint32_t EmcQSafe;
/* Specifies the value for EMC_RDV */
uint32_t EmcRdv;
/* Specifies the value for EMC_RDV_MASK */
uint32_t EmcRdvMask;
/* Specifies the value for EMC_RDV_EARLY */
uint32_t EmcRdvEarly;
/* Specifies the value for EMC_RDV_EARLY_MASK */
uint32_t EmcRdvEarlyMask;
/* Specifies the value for EMC_QPOP */
uint32_t EmcQpop;
/* Specifies the value for EMC_REFRESH */
uint32_t EmcRefresh;
/* Specifies the value for EMC_BURST_REFRESH_NUM */
uint32_t EmcBurstRefreshNum;
/* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */
uint32_t EmcPreRefreshReqCnt;
/* Specifies the value for EMC_PDEX2WR */
uint32_t EmcPdEx2Wr;
/* Specifies the value for EMC_PDEX2RD */
uint32_t EmcPdEx2Rd;
/* Specifies the value for EMC_PCHG2PDEN */
uint32_t EmcPChg2Pden;
/* Specifies the value for EMC_ACT2PDEN */
uint32_t EmcAct2Pden;
/* Specifies the value for EMC_AR2PDEN */
uint32_t EmcAr2Pden;
/* Specifies the value for EMC_RW2PDEN */
uint32_t EmcRw2Pden;
/* Specifies the value for EMC_CKE2PDEN */
uint32_t EmcCke2Pden;
/* Specifies the value for EMC_PDEX2CKE */
uint32_t EmcPdex2Cke;
/* Specifies the value for EMC_PDEX2MRR */
uint32_t EmcPdex2Mrr;
/* Specifies the value for EMC_TXSR */
uint32_t EmcTxsr;
/* Specifies the value for EMC_TXSRDLL */
uint32_t EmcTxsrDll;
/* Specifies the value for EMC_TCKE */
uint32_t EmcTcke;
/* Specifies the value for EMC_TCKESR */
uint32_t EmcTckesr;
/* Specifies the value for EMC_TPD */
uint32_t EmcTpd;
/* Specifies the value for EMC_TFAW */
uint32_t EmcTfaw;
/* Specifies the value for EMC_TRPAB */
uint32_t EmcTrpab;
/* Specifies the value for EMC_TCLKSTABLE */
uint32_t EmcTClkStable;
/* Specifies the value for EMC_TCLKSTOP */
uint32_t EmcTClkStop;
/* Specifies the value for EMC_TREFBW */
uint32_t EmcTRefBw;
/* FBIO configuration values */
/* Specifies the value for EMC_FBIO_CFG5 */
uint32_t EmcFbioCfg5;
/* Specifies the value for EMC_FBIO_CFG7 */
uint32_t EmcFbioCfg7;
/* Specifies the value for EMC_FBIO_CFG8 */
uint32_t EmcFbioCfg8;
/* Command mapping for CMD brick 0 */
uint32_t EmcCmdMappingCmd0_0;
uint32_t EmcCmdMappingCmd0_1;
uint32_t EmcCmdMappingCmd0_2;
uint32_t EmcCmdMappingCmd1_0;
uint32_t EmcCmdMappingCmd1_1;
uint32_t EmcCmdMappingCmd1_2;
uint32_t EmcCmdMappingCmd2_0;
uint32_t EmcCmdMappingCmd2_1;
uint32_t EmcCmdMappingCmd2_2;
uint32_t EmcCmdMappingCmd3_0;
uint32_t EmcCmdMappingCmd3_1;
uint32_t EmcCmdMappingCmd3_2;
uint32_t EmcCmdMappingByte;
/* Specifies the value for EMC_FBIO_SPARE */
uint32_t EmcFbioSpare;
/* Specifies the value for EMC_CFG_RSV */
uint32_t EmcCfgRsv;
/* MRS command values */
/* Specifies the value for EMC_MRS */
uint32_t EmcMrs;
/* Specifies the MP0 command to initialize mode registers */
uint32_t EmcEmrs;
/* Specifies the MP2 command to initialize mode registers */
uint32_t EmcEmrs2;
/* Specifies the MP3 command to initialize mode registers */
uint32_t EmcEmrs3;
/* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */
uint32_t EmcMrw1;
/* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */
uint32_t EmcMrw2;
/* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */
uint32_t EmcMrw3;
/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
uint32_t EmcMrw4;
/* Specifies the programming to LPDDR2 Mode Register 3? at cold boot */
uint32_t EmcMrw6;
/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
uint32_t EmcMrw8;
/* Specifies the programming to LPDDR2 Mode Register 11? at cold boot */
uint32_t EmcMrw9;
/* Specifies the programming to LPDDR2 Mode Register 12 at cold boot */
uint32_t EmcMrw10;
/* Specifies the programming to LPDDR2 Mode Register 14 at cold boot */
uint32_t EmcMrw12;
/* Specifies the programming to LPDDR2 Mode Register 14? at cold boot */
uint32_t EmcMrw13;
/* Specifies the programming to LPDDR2 Mode Register 22 at cold boot */
uint32_t EmcMrw14;
/*
* Specifies the programming to extra LPDDR2 Mode Register
* at cold boot
*/
uint32_t EmcMrwExtra;
/*
* Specifies the programming to extra LPDDR2 Mode Register
* at warm boot
*/
uint32_t EmcWarmBootMrwExtra;
/*
* Specify the enable of extra Mode Register programming at
* warm boot
*/
uint32_t EmcWarmBootExtraModeRegWriteEnable;
/*
* Specify the enable of extra Mode Register programming at
* cold boot
*/
uint32_t EmcExtraModeRegWriteEnable;
/* Specifies the EMC_MRW reset command value */
uint32_t EmcMrwResetCommand;
/* Specifies the EMC Reset wait time (in microseconds) */
uint32_t EmcMrwResetNInitWait;
/* Specifies the value for EMC_MRS_WAIT_CNT */
uint32_t EmcMrsWaitCnt;
/* Specifies the value for EMC_MRS_WAIT_CNT2 */
uint32_t EmcMrsWaitCnt2;
/* EMC miscellaneous configurations */
/* Specifies the value for EMC_CFG */
uint32_t EmcCfg;
/* Specifies the value for EMC_CFG_2 */
uint32_t EmcCfg2;
/* Specifies the pipe bypass controls */
uint32_t EmcCfgPipe;
uint32_t EmcCfgPipeClk;
uint32_t EmcFdpdCtrlCmdNoRamp;
uint32_t EmcCfgUpdate;
/* Specifies the value for EMC_DBG */
uint32_t EmcDbg;
uint32_t EmcDbgWriteMux;
/* Specifies the value for EMC_CMDQ */
uint32_t EmcCmdQ;
/* Specifies the value for EMC_MC2EMCQ */
uint32_t EmcMc2EmcQ;
/* Specifies the value for EMC_DYN_SELF_REF_CONTROL */
uint32_t EmcDynSelfRefControl;
/* Specifies the value for MEM_INIT_DONE */
uint32_t AhbArbitrationXbarCtrlMemInitDone;
/* Specifies the value for EMC_CFG_DIG_DLL */
uint32_t EmcCfgDigDll;
uint32_t EmcCfgDigDll_1;
/* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */
uint32_t EmcCfgDigDllPeriod;
/* Specifies the value of *DEV_SELECTN of various EMC registers */
uint32_t EmcDevSelect;
/* Specifies the value for EMC_SEL_DPD_CTRL */
uint32_t EmcSelDpdCtrl;
/* Pads trimmer delays */
uint32_t EmcFdpdCtrlDq;
uint32_t EmcFdpdCtrlCmd;
uint32_t EmcPmacroIbVrefDq_0;
uint32_t EmcPmacroIbVrefDq_1;
uint32_t EmcPmacroIbVrefDqs_0;
uint32_t EmcPmacroIbVrefDqs_1;
uint32_t EmcPmacroIbRxrt;
uint32_t EmcCfgPipe1;
uint32_t EmcCfgPipe2;
/* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */
uint32_t EmcPmacroQuseDdllRank0_0;
uint32_t EmcPmacroQuseDdllRank0_1;
uint32_t EmcPmacroQuseDdllRank0_2;
uint32_t EmcPmacroQuseDdllRank0_3;
uint32_t EmcPmacroQuseDdllRank0_4;
uint32_t EmcPmacroQuseDdllRank0_5;
uint32_t EmcPmacroQuseDdllRank1_0;
uint32_t EmcPmacroQuseDdllRank1_1;
uint32_t EmcPmacroQuseDdllRank1_2;
uint32_t EmcPmacroQuseDdllRank1_3;
uint32_t EmcPmacroQuseDdllRank1_4;
uint32_t EmcPmacroQuseDdllRank1_5;
uint32_t EmcPmacroObDdllLongDqRank0_0;
uint32_t EmcPmacroObDdllLongDqRank0_1;
uint32_t EmcPmacroObDdllLongDqRank0_2;
uint32_t EmcPmacroObDdllLongDqRank0_3;
uint32_t EmcPmacroObDdllLongDqRank0_4;
uint32_t EmcPmacroObDdllLongDqRank0_5;
uint32_t EmcPmacroObDdllLongDqRank1_0;
uint32_t EmcPmacroObDdllLongDqRank1_1;
uint32_t EmcPmacroObDdllLongDqRank1_2;
uint32_t EmcPmacroObDdllLongDqRank1_3;
uint32_t EmcPmacroObDdllLongDqRank1_4;
uint32_t EmcPmacroObDdllLongDqRank1_5;
uint32_t EmcPmacroObDdllLongDqsRank0_0;
uint32_t EmcPmacroObDdllLongDqsRank0_1;
uint32_t EmcPmacroObDdllLongDqsRank0_2;
uint32_t EmcPmacroObDdllLongDqsRank0_3;
uint32_t EmcPmacroObDdllLongDqsRank0_4;
uint32_t EmcPmacroObDdllLongDqsRank0_5;
uint32_t EmcPmacroObDdllLongDqsRank1_0;
uint32_t EmcPmacroObDdllLongDqsRank1_1;
uint32_t EmcPmacroObDdllLongDqsRank1_2;
uint32_t EmcPmacroObDdllLongDqsRank1_3;
uint32_t EmcPmacroObDdllLongDqsRank1_4;
uint32_t EmcPmacroObDdllLongDqsRank1_5;
uint32_t EmcPmacroIbDdllLongDqsRank0_0;
uint32_t EmcPmacroIbDdllLongDqsRank0_1;
uint32_t EmcPmacroIbDdllLongDqsRank0_2;
uint32_t EmcPmacroIbDdllLongDqsRank0_3;
uint32_t EmcPmacroIbDdllLongDqsRank1_0;
uint32_t EmcPmacroIbDdllLongDqsRank1_1;
uint32_t EmcPmacroIbDdllLongDqsRank1_2;
uint32_t EmcPmacroIbDdllLongDqsRank1_3;
uint32_t EmcPmacroDdllLongCmd_0;
uint32_t EmcPmacroDdllLongCmd_1;
uint32_t EmcPmacroDdllLongCmd_2;
uint32_t EmcPmacroDdllLongCmd_3;
uint32_t EmcPmacroDdllLongCmd_4;
uint32_t EmcPmacroDdllShortCmd_0;
uint32_t EmcPmacroDdllShortCmd_1;
uint32_t EmcPmacroDdllShortCmd_2;
/*
* Specifies the delay after asserting CKE pin during a WarmBoot0
* sequence (in microseconds)
*/
uint32_t WarmBootWait;
/* Specifies the value for EMC_ODT_WRITE */
uint32_t EmcOdtWrite;
/* Periodic ZQ calibration */
/*
* Specifies the value for EMC_ZCAL_INTERVAL
* Value 0 disables ZQ calibration
*/
uint32_t EmcZcalInterval;
/* Specifies the value for EMC_ZCAL_WAIT_CNT */
uint32_t EmcZcalWaitCnt;
/* Specifies the value for EMC_ZCAL_MRW_CMD */
uint32_t EmcZcalMrwCmd;
/* DRAM initialization sequence flow control */
/* Specifies the MRS command value for resetting DLL */
uint32_t EmcMrsResetDll;
/* Specifies the command for ZQ initialization of device 0 */
uint32_t EmcZcalInitDev0;
/* Specifies the command for ZQ initialization of device 1 */
uint32_t EmcZcalInitDev1;
/*
* Specifies the wait time after programming a ZQ initialization
* command (in microseconds)
*/
uint32_t EmcZcalInitWait;
/*
* Specifies the enable for ZQ calibration at cold boot [bit 0]
* and warm boot [bit 1]
*/
uint32_t EmcZcalWarmColdBootEnables;
/*
* Specifies the MRW command to LPDDR2 for ZQ calibration
* on warmboot
*/
/* Is issued to both devices separately */
uint32_t EmcMrwLpddr2ZcalWarmBoot;
/*
* Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
* Is issued to both devices separately
*/
uint32_t EmcZqCalDdr3WarmBoot;
uint32_t EmcZqCalLpDdr4WarmBoot;
/*
* Specifies the wait time for ZQ calibration on warmboot
* (in microseconds)
*/
uint32_t EmcZcalWarmBootWait;
/*
* Specifies the enable for DRAM Mode Register programming
* at warm boot
*/
uint32_t EmcMrsWarmBootEnable;
/*
* Specifies the wait time after sending an MRS DLL reset command
* in microseconds)
*/
uint32_t EmcMrsResetDllWait;
/* Specifies the extra MRS command to initialize mode registers */
uint32_t EmcMrsExtra;
/* Specifies the extra MRS command at warm boot */
uint32_t EmcWarmBootMrsExtra;
/* Specifies the EMRS command to enable the DDR2 DLL */
uint32_t EmcEmrsDdr2DllEnable;
/* Specifies the MRS command to reset the DDR2 DLL */
uint32_t EmcMrsDdr2DllReset;
/* Specifies the EMRS command to set OCD calibration */
uint32_t EmcEmrsDdr2OcdCalib;
/*
* Specifies the wait between initializing DDR and setting OCD
* calibration (in microseconds)
*/
uint32_t EmcDdr2Wait;
/* Specifies the value for EMC_CLKEN_OVERRIDE */
uint32_t EmcClkenOverride;
/*
* Specifies LOG2 of the extra refresh numbers after booting
* Program 0 to disable
*/
uint32_t EmcExtraRefreshNum;
/* Specifies the master override for all EMC clocks */
uint32_t EmcClkenOverrideAllWarmBoot;
/* Specifies the master override for all MC clocks */
uint32_t McClkenOverrideAllWarmBoot;
/* Specifies digital dll period, choosing between 4 to 64 ms */
uint32_t EmcCfgDigDllPeriodWarmBoot;
/* Pad controls */
/* Specifies the value for PMC_VDDP_SEL */
uint32_t PmcVddpSel;
/* Specifies the wait time after programming PMC_VDDP_SEL */
uint32_t PmcVddpSelWait;
/* Specifies the value for PMC_DDR_PWR */
uint32_t PmcDdrPwr;
/* Specifies the value for PMC_DDR_CFG */
uint32_t PmcDdrCfg;
/* Specifies the value for PMC_IO_DPD3_REQ */
uint32_t PmcIoDpd3Req;
/* Specifies the wait time after programming PMC_IO_DPD3_REQ */
uint32_t PmcIoDpd3ReqWait;
uint32_t PmcIoDpd4ReqWait;
/* Specifies the value for PMC_REG_SHORT */
uint32_t PmcRegShort;
/* Specifies the value for PMC_NO_IOPOWER */
uint32_t PmcNoIoPower;
uint32_t PmcDdrCntrlWait;
uint32_t PmcDdrCntrl;
/* Specifies the value for EMC_ACPD_CONTROL */
uint32_t EmcAcpdControl;
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */
////uint32_t EmcSwizzleRank0ByteCfg;
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */
uint32_t EmcSwizzleRank0Byte0;
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */
uint32_t EmcSwizzleRank0Byte1;
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */
uint32_t EmcSwizzleRank0Byte2;
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */
uint32_t EmcSwizzleRank0Byte3;
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */
////uint32_t EmcSwizzleRank1ByteCfg;
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */
uint32_t EmcSwizzleRank1Byte0;
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */
uint32_t EmcSwizzleRank1Byte1;
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */
uint32_t EmcSwizzleRank1Byte2;
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */
uint32_t EmcSwizzleRank1Byte3;
/* Specifies the value for EMC_TXDSRVTTGEN */
uint32_t EmcTxdsrvttgen;
/* Specifies the value for EMC_DATA_BRLSHFT_0 */
uint32_t EmcDataBrlshft0;
uint32_t EmcDataBrlshft1;
uint32_t EmcDqsBrlshft0;
uint32_t EmcDqsBrlshft1;
uint32_t EmcCmdBrlshft0;
uint32_t EmcCmdBrlshft1;
uint32_t EmcCmdBrlshft2;
uint32_t EmcCmdBrlshft3;
uint32_t EmcQuseBrlshft0;
uint32_t EmcQuseBrlshft1;
uint32_t EmcQuseBrlshft2;
uint32_t EmcQuseBrlshft3;
uint32_t EmcDllCfg0;
uint32_t EmcDllCfg1;
uint32_t EmcPmcScratch1;
uint32_t EmcPmcScratch2;
uint32_t EmcPmcScratch3;
uint32_t EmcPmacroPadCfgCtrl;
uint32_t EmcPmacroVttgenCtrl0;
uint32_t EmcPmacroVttgenCtrl1;
uint32_t EmcPmacroVttgenCtrl2;
uint32_t EmcPmacroBrickCtrlRfu1;
uint32_t EmcPmacroCmdBrickCtrlFdpd;
uint32_t EmcPmacroBrickCtrlRfu2;
uint32_t EmcPmacroDataBrickCtrlFdpd;
uint32_t EmcPmacroBgBiasCtrl0;
uint32_t EmcPmacroDataPadRxCtrl;
uint32_t EmcPmacroCmdPadRxCtrl;
uint32_t EmcPmacroDataRxTermMode;
uint32_t EmcPmacroCmdRxTermMode;
uint32_t EmcPmacroDataPadTxCtrl;
uint32_t EmcPmacroCommonPadTxCtrl;
uint32_t EmcPmacroCmdPadTxCtrl;
uint32_t EmcCfg3;
uint32_t EmcPmacroTxPwrd0;
uint32_t EmcPmacroTxPwrd1;
uint32_t EmcPmacroTxPwrd2;
uint32_t EmcPmacroTxPwrd3;
uint32_t EmcPmacroTxPwrd4;
uint32_t EmcPmacroTxPwrd5;
uint32_t EmcConfigSampleDelay;
uint32_t EmcPmacroBrickMapping0;
uint32_t EmcPmacroBrickMapping1;
uint32_t EmcPmacroBrickMapping2;
uint32_t EmcPmacroTxSelClkSrc0;
uint32_t EmcPmacroTxSelClkSrc1;
uint32_t EmcPmacroTxSelClkSrc2;
uint32_t EmcPmacroTxSelClkSrc3;
uint32_t EmcPmacroTxSelClkSrc4;
uint32_t EmcPmacroTxSelClkSrc5;
uint32_t EmcPmacroDdllBypass;
uint32_t EmcPmacroDdllPwrd0;
uint32_t EmcPmacroDdllPwrd1;
uint32_t EmcPmacroDdllPwrd2;
uint32_t EmcPmacroCmdCtrl0;
uint32_t EmcPmacroCmdCtrl1;
uint32_t EmcPmacroCmdCtrl2;
/* DRAM size information */
/* Specifies the value for MC_EMEM_ADR_CFG */
uint32_t McEmemAdrCfg;
/* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */
uint32_t McEmemAdrCfgDev0;
/* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */
uint32_t McEmemAdrCfgDev1;
uint32_t McEmemAdrCfgChannelMask;
/* Specifies the value for MC_EMEM_BANK_SWIZZLECfg0 */
uint32_t McEmemAdrCfgBankMask0;
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */
uint32_t McEmemAdrCfgBankMask1;
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */
uint32_t McEmemAdrCfgBankMask2;
/*
* Specifies the value for MC_EMEM_CFG which holds the external memory
* size (in KBytes)
*/
uint32_t McEmemCfg;
/* MC arbitration configuration */
/* Specifies the value for MC_EMEM_ARB_CFG */
uint32_t McEmemArbCfg;
/* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */
uint32_t McEmemArbOutstandingReq;
uint32_t McEmemArbRefpbHpCtrl;
uint32_t McEmemArbRefpbBankCtrl;
/* Specifies the value for MC_EMEM_ARB_TIMING_RCD */
uint32_t McEmemArbTimingRcd;
/* Specifies the value for MC_EMEM_ARB_TIMING_RP */
uint32_t McEmemArbTimingRp;
/* Specifies the value for MC_EMEM_ARB_TIMING_RC */
uint32_t McEmemArbTimingRc;
/* Specifies the value for MC_EMEM_ARB_TIMING_RAS */
uint32_t McEmemArbTimingRas;
/* Specifies the value for MC_EMEM_ARB_TIMING_FAW */
uint32_t McEmemArbTimingFaw;
/* Specifies the value for MC_EMEM_ARB_TIMING_RRD */
uint32_t McEmemArbTimingRrd;
/* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */
uint32_t McEmemArbTimingRap2Pre;
/* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */
uint32_t McEmemArbTimingWap2Pre;
/* Specifies the value for MC_EMEM_ARB_TIMING_R2R */
uint32_t McEmemArbTimingR2R;
/* Specifies the value for MC_EMEM_ARB_TIMING_W2W */
uint32_t McEmemArbTimingW2W;
/* Specifies the value for MC_EMEM_ARB_TIMING_R2W */
uint32_t McEmemArbTimingR2W;
/* Specifies the value for MC_EMEM_ARB_TIMING_W2R */
uint32_t McEmemArbTimingW2R;
uint32_t McEmemArbTimingRFCPB;
/* Specifies the value for MC_EMEM_ARB_DA_TURNS */
uint32_t McEmemArbDaTurns;
/* Specifies the value for MC_EMEM_ARB_DA_COVERS */
uint32_t McEmemArbDaCovers;
/* Specifies the value for MC_EMEM_ARB_MISC0 */
uint32_t McEmemArbMisc0;
/* Specifies the value for MC_EMEM_ARB_MISC1 */
uint32_t McEmemArbMisc1;
uint32_t McEmemArbMisc2;
/* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */
uint32_t McEmemArbRing1Throttle;
/* Specifies the value for MC_EMEM_ARB_OVERRIDE */
uint32_t McEmemArbOverride;
/* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */
uint32_t McEmemArbOverride1;
/* Specifies the value for MC_EMEM_ARB_RSV */
uint32_t McEmemArbRsv;
uint32_t McDaCfg0;
uint32_t McEmemArbTimingCcdmw;
/* Specifies the value for MC_CLKEN_OVERRIDE */
uint32_t McClkenOverride;
/* Specifies the value for MC_STAT_CONTROL */
uint32_t McStatControl;
/* Specifies the value for MC_VIDEO_PROTECT_BOM */
uint32_t McVideoProtectBom;
/* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */
uint32_t McVideoProtectBomAdrHi;
/* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */
uint32_t McVideoProtectSizeMb;
/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */
uint32_t McVideoProtectVprOverride;
/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */
uint32_t McVideoProtectVprOverride1;
/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */
uint32_t McVideoProtectGpuOverride0;
/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */
uint32_t McVideoProtectGpuOverride1;
/* Specifies the value for MC_SEC_CARVEOUT_BOM */
uint32_t McSecCarveoutBom;
/* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */
uint32_t McSecCarveoutAdrHi;
/* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */
uint32_t McSecCarveoutSizeMb;
/* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.
VIDEO_PROTECT_WRITEAccess */
uint32_t McVideoProtectWriteAccess;
/* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.
SEC_CARVEOUT_WRITEAccess */
uint32_t McSecCarveoutProtectWriteAccess;
/* Write-Protect Regions (WPR) */
uint32_t McGeneralizedCarveout1Bom;
uint32_t McGeneralizedCarveout1BomHi;
uint32_t McGeneralizedCarveout1Size128kb;
uint32_t McGeneralizedCarveout1Access0;
uint32_t McGeneralizedCarveout1Access1;
uint32_t McGeneralizedCarveout1Access2;
uint32_t McGeneralizedCarveout1Access3;
uint32_t McGeneralizedCarveout1Access4;
uint32_t McGeneralizedCarveout1ForceInternalAccess0;
uint32_t McGeneralizedCarveout1ForceInternalAccess1;
uint32_t McGeneralizedCarveout1ForceInternalAccess2;
uint32_t McGeneralizedCarveout1ForceInternalAccess3;
uint32_t McGeneralizedCarveout1ForceInternalAccess4;
uint32_t McGeneralizedCarveout1Cfg0;
uint32_t McGeneralizedCarveout2Bom;
uint32_t McGeneralizedCarveout2BomHi;
uint32_t McGeneralizedCarveout2Size128kb;
uint32_t McGeneralizedCarveout2Access0;
uint32_t McGeneralizedCarveout2Access1;
uint32_t McGeneralizedCarveout2Access2;
uint32_t McGeneralizedCarveout2Access3;
uint32_t McGeneralizedCarveout2Access4;
uint32_t McGeneralizedCarveout2ForceInternalAccess0;
uint32_t McGeneralizedCarveout2ForceInternalAccess1;
uint32_t McGeneralizedCarveout2ForceInternalAccess2;
uint32_t McGeneralizedCarveout2ForceInternalAccess3;
uint32_t McGeneralizedCarveout2ForceInternalAccess4;
uint32_t McGeneralizedCarveout2Cfg0;
uint32_t McGeneralizedCarveout3Bom;
uint32_t McGeneralizedCarveout3BomHi;
uint32_t McGeneralizedCarveout3Size128kb;
uint32_t McGeneralizedCarveout3Access0;
uint32_t McGeneralizedCarveout3Access1;
uint32_t McGeneralizedCarveout3Access2;
uint32_t McGeneralizedCarveout3Access3;
uint32_t McGeneralizedCarveout3Access4;
uint32_t McGeneralizedCarveout3ForceInternalAccess0;
uint32_t McGeneralizedCarveout3ForceInternalAccess1;
uint32_t McGeneralizedCarveout3ForceInternalAccess2;
uint32_t McGeneralizedCarveout3ForceInternalAccess3;
uint32_t McGeneralizedCarveout3ForceInternalAccess4;
uint32_t McGeneralizedCarveout3Cfg0;
uint32_t McGeneralizedCarveout4Bom;
uint32_t McGeneralizedCarveout4BomHi;
uint32_t McGeneralizedCarveout4Size128kb;
uint32_t McGeneralizedCarveout4Access0;
uint32_t McGeneralizedCarveout4Access1;
uint32_t McGeneralizedCarveout4Access2;
uint32_t McGeneralizedCarveout4Access3;
uint32_t McGeneralizedCarveout4Access4;
uint32_t McGeneralizedCarveout4ForceInternalAccess0;
uint32_t McGeneralizedCarveout4ForceInternalAccess1;
uint32_t McGeneralizedCarveout4ForceInternalAccess2;
uint32_t McGeneralizedCarveout4ForceInternalAccess3;
uint32_t McGeneralizedCarveout4ForceInternalAccess4;
uint32_t McGeneralizedCarveout4Cfg0;
uint32_t McGeneralizedCarveout5Bom;
uint32_t McGeneralizedCarveout5BomHi;
uint32_t McGeneralizedCarveout5Size128kb;
uint32_t McGeneralizedCarveout5Access0;
uint32_t McGeneralizedCarveout5Access1;
uint32_t McGeneralizedCarveout5Access2;
uint32_t McGeneralizedCarveout5Access3;
uint32_t McGeneralizedCarveout5Access4;
uint32_t McGeneralizedCarveout5ForceInternalAccess0;
uint32_t McGeneralizedCarveout5ForceInternalAccess1;
uint32_t McGeneralizedCarveout5ForceInternalAccess2;
uint32_t McGeneralizedCarveout5ForceInternalAccess3;
uint32_t McGeneralizedCarveout5ForceInternalAccess4;
uint32_t McGeneralizedCarveout5Cfg0;
/* Specifies enable for CA training */
uint32_t EmcCaTrainingEnable;
/* Set if bit 6 select is greater than bit 7 select; uses aremc.
spec packet SWIZZLE_BIT6_GT_BIT7 */
uint32_t SwizzleRankByteEncode;
/* Specifies enable and offset for patched boot ROM write */
uint32_t BootRomPatchControl;
/* Specifies data for patched boot ROM write */
uint32_t BootRomPatchData;
/* Specifies the value for MC_MTS_CARVEOUT_BOM */
uint32_t McMtsCarveoutBom;
/* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */
uint32_t McMtsCarveoutAdrHi;
/* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */
uint32_t McMtsCarveoutSizeMb;
/* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */
uint32_t McMtsCarveoutRegCtrl;
/* End */
};
#endif /* __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ */

1041
fusee/fusee-primary/src/sdram_params.h Normal file
View file

File diff suppressed because it is too large Load diff

40
fusee/fusee-secondary/src/emc.h
View file

@ -1086,4 +1086,44 @@
#define EMC_PMC_SCRATCH2 0x444 #define EMC_PMC_SCRATCH2 0x444
#define EMC_PMC_SCRATCH3 0x448 #define EMC_PMC_SCRATCH3 0x448
#define EMC_PMACRO_PERBIT_FGCG_CTRL_0 0xd40
#define EMC_PMACRO_PERBIT_FGCG_CTRL_1 0xd44
#define EMC_PMACRO_PERBIT_FGCG_CTRL_2 0xd48
#define EMC_PMACRO_PERBIT_FGCG_CTRL_3 0xd4c
#define EMC_PMACRO_PERBIT_FGCG_CTRL_4 0xd50
#define EMC_PMACRO_PERBIT_FGCG_CTRL_5 0xd54
#define EMC_PMACRO_PERBIT_RFU_CTRL_0 0xd60
#define EMC_PMACRO_PERBIT_RFU_CTRL_1 0xd64
#define EMC_PMACRO_PERBIT_RFU_CTRL_2 0xd68
#define EMC_PMACRO_PERBIT_RFU_CTRL_3 0xd6c
#define EMC_PMACRO_PERBIT_RFU_CTRL_4 0xd70
#define EMC_PMACRO_PERBIT_RFU_CTRL_5 0xd74
#define EMC_PMACRO_PERBIT_RFU1_CTRL_0 0xd80
#define EMC_PMACRO_PERBIT_RFU1_CTRL_1 0xd84
#define EMC_PMACRO_PERBIT_RFU1_CTRL_2 0xd88
#define EMC_PMACRO_PERBIT_RFU1_CTRL_3 0xd8c
#define EMC_PMACRO_PERBIT_RFU1_CTRL_4 0xd90
#define EMC_PMACRO_PERBIT_RFU1_CTRL_5 0xd94
#define EMC_PMACRO_PMU_OUT_EOFF1_0 0xda0
#define EMC_PMACRO_PMU_OUT_EOFF1_1 0xda4
#define EMC_PMACRO_PMU_OUT_EOFF1_2 0xda8
#define EMC_PMACRO_PMU_OUT_EOFF1_3 0xdac
#define EMC_PMACRO_PMU_OUT_EOFF1_4 0xdb0
#define EMC_PMACRO_PMU_OUT_EOFF1_5 0xdb4
#define EMC_PMACRO_COMP_PMU_OUT 0xdc0
#define EMC_PMACRO_DATA_PI_CTRL 0x110
#define EMC_PMACRO_CMD_PI_CTRL 0x114
#define EMC_AUTO_CAL_CONFIG9 0x42c
#define EMC_TRTM 0xbc
#define EMC_TWTM 0xf8
#define EMC_TRATM 0xfc
#define EMC_TWATM 0x108
#define EMC_TR2REF 0x10c
#define EMC_PMACRO_DSR_VTTGEN_CTRL_0 0xc6c
#endif #endif

2
fusee/fusee-secondary/src/fuse.c
View file

@ -187,7 +187,7 @@ uint32_t fuse_get_reserved_odm(uint32_t index) {
/* Get the DramId. */ /* Get the DramId. */
uint32_t fuse_get_dram_id(void) { uint32_t fuse_get_dram_id(void) {
return ((fuse_get_reserved_odm(4) >> 3) & 0x7); return ((fuse_get_reserved_odm(4) >> 3) & 0x1F);
} }
/* Derive the DeviceId. */ /* Derive the DeviceId. */

1
fusee/fusee-secondary/src/mc.h
View file

@ -497,6 +497,7 @@
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08 #define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08
#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0 #define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0
#define MC_DA_CONFIG0 0x9dc #define MC_DA_CONFIG0 0x9dc
#define MC_UNTRANSLATED_REGION_CHECK 0x948
/* Memory Controller clients */ /* Memory Controller clients */
#define CLIENT_ACCESS_NUM_CLIENTS 32 #define CLIENT_ACCESS_NUM_CLIENTS 32

2
sept/sept-primary/src/fuse.c
View file

@ -187,7 +187,7 @@ uint32_t fuse_get_reserved_odm(uint32_t index) {
/* Get the DramId. */ /* Get the DramId. */
uint32_t fuse_get_dram_id(void) { uint32_t fuse_get_dram_id(void) {
return ((fuse_get_reserved_odm(4) >> 3) & 0x7); return ((fuse_get_reserved_odm(4) >> 3) & 0x1F);
} }
/* Derive the DeviceId. */ /* Derive the DeviceId. */

1
sept/sept-primary/src/mc.h
View file

@ -497,6 +497,7 @@
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08 #define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08
#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0 #define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0
#define MC_DA_CONFIG0 0x9dc #define MC_DA_CONFIG0 0x9dc
#define MC_UNTRANSLATED_REGION_CHECK 0x948
/* Memory Controller clients */ /* Memory Controller clients */
#define CLIENT_ACCESS_NUM_CLIENTS 32 #define CLIENT_ACCESS_NUM_CLIENTS 32

40
sept/sept-secondary/src/emc.h
View file

@ -1086,4 +1086,44 @@
#define EMC_PMC_SCRATCH2 0x444 #define EMC_PMC_SCRATCH2 0x444
#define EMC_PMC_SCRATCH3 0x448 #define EMC_PMC_SCRATCH3 0x448
#define EMC_PMACRO_PERBIT_FGCG_CTRL_0 0xd40
#define EMC_PMACRO_PERBIT_FGCG_CTRL_1 0xd44
#define EMC_PMACRO_PERBIT_FGCG_CTRL_2 0xd48
#define EMC_PMACRO_PERBIT_FGCG_CTRL_3 0xd4c
#define EMC_PMACRO_PERBIT_FGCG_CTRL_4 0xd50
#define EMC_PMACRO_PERBIT_FGCG_CTRL_5 0xd54
#define EMC_PMACRO_PERBIT_RFU_CTRL_0 0xd60
#define EMC_PMACRO_PERBIT_RFU_CTRL_1 0xd64
#define EMC_PMACRO_PERBIT_RFU_CTRL_2 0xd68
#define EMC_PMACRO_PERBIT_RFU_CTRL_3 0xd6c
#define EMC_PMACRO_PERBIT_RFU_CTRL_4 0xd70
#define EMC_PMACRO_PERBIT_RFU_CTRL_5 0xd74
#define EMC_PMACRO_PERBIT_RFU1_CTRL_0 0xd80
#define EMC_PMACRO_PERBIT_RFU1_CTRL_1 0xd84
#define EMC_PMACRO_PERBIT_RFU1_CTRL_2 0xd88
#define EMC_PMACRO_PERBIT_RFU1_CTRL_3 0xd8c
#define EMC_PMACRO_PERBIT_RFU1_CTRL_4 0xd90
#define EMC_PMACRO_PERBIT_RFU1_CTRL_5 0xd94
#define EMC_PMACRO_PMU_OUT_EOFF1_0 0xda0
#define EMC_PMACRO_PMU_OUT_EOFF1_1 0xda4
#define EMC_PMACRO_PMU_OUT_EOFF1_2 0xda8
#define EMC_PMACRO_PMU_OUT_EOFF1_3 0xdac
#define EMC_PMACRO_PMU_OUT_EOFF1_4 0xdb0
#define EMC_PMACRO_PMU_OUT_EOFF1_5 0xdb4
#define EMC_PMACRO_COMP_PMU_OUT 0xdc0
#define EMC_PMACRO_DATA_PI_CTRL 0x110
#define EMC_PMACRO_CMD_PI_CTRL 0x114
#define EMC_AUTO_CAL_CONFIG9 0x42c
#define EMC_TRTM 0xbc
#define EMC_TWTM 0xf8
#define EMC_TRATM 0xfc
#define EMC_TWATM 0x108
#define EMC_TR2REF 0x10c
#define EMC_PMACRO_DSR_VTTGEN_CTRL_0 0xc6c
#endif #endif

2
sept/sept-secondary/src/fuse.c
View file

@ -187,7 +187,7 @@ uint32_t fuse_get_reserved_odm(uint32_t index) {
/* Get the DramId. */ /* Get the DramId. */
uint32_t fuse_get_dram_id(void) { uint32_t fuse_get_dram_id(void) {
return ((fuse_get_reserved_odm(4) >> 3) & 0x7); return ((fuse_get_reserved_odm(4) >> 3) & 0x1F);
} }
/* Derive the DeviceId. */ /* Derive the DeviceId. */

150
sept/sept-secondary/src/hwinit.c
View file

@ -34,8 +34,7 @@
#include "timers.h" #include "timers.h"
#include "uart.h" #include "uart.h"
void config_oscillators() static void config_oscillators(void) {
{
volatile tegra_car_t *car = car_get_regs(); volatile tegra_car_t *car = car_get_regs();
volatile tegra_pmc_t *pmc = pmc_get_regs(); volatile tegra_pmc_t *pmc = pmc_get_regs();
@ -57,8 +56,7 @@ void config_oscillators()
car->clk_sys_rate = 2; car->clk_sys_rate = 2;
} }
void config_gpios() static void config_gpios_erista(void) {
{
volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
pinmux->uart2_tx = 0; pinmux->uart2_tx = 0;
@ -79,15 +77,50 @@ void config_gpios()
i2c_config(I2C_5); i2c_config(I2C_5);
uart_config(UART_A); uart_config(UART_A);
/* Configure volume up/down as inputs. */ /* Configure volume up/down buttons as inputs. */
gpio_configure_mode(GPIO_BUTTON_VOL_UP, GPIO_MODE_GPIO); gpio_configure_mode(GPIO_BUTTON_VOL_UP, GPIO_MODE_GPIO);
gpio_configure_mode(GPIO_BUTTON_VOL_DOWN, GPIO_MODE_GPIO); gpio_configure_mode(GPIO_BUTTON_VOL_DOWN, GPIO_MODE_GPIO);
gpio_configure_direction(GPIO_BUTTON_VOL_UP, GPIO_DIRECTION_INPUT); gpio_configure_direction(GPIO_BUTTON_VOL_UP, GPIO_DIRECTION_INPUT);
gpio_configure_direction(GPIO_BUTTON_VOL_DOWN, GPIO_DIRECTION_INPUT); gpio_configure_direction(GPIO_BUTTON_VOL_DOWN, GPIO_DIRECTION_INPUT);
} }
void config_pmc_scratch() static void config_gpios_mariko(void) {
{ volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
uint32_t hardware_type = fuse_get_hardware_type();
/* Only for HardwareType_Iowa and HardwareType_Five. */
if ((hardware_type == 3) || (hardware_type == 5)) {
pinmux->uart2_tx = 0;
pinmux->uart3_tx = 0;
gpio_configure_mode(TEGRA_GPIO(G, 0), GPIO_MODE_GPIO);
gpio_configure_mode(TEGRA_GPIO(D, 1), GPIO_MODE_GPIO);
gpio_configure_direction(TEGRA_GPIO(G, 0), GPIO_DIRECTION_INPUT);
gpio_configure_direction(TEGRA_GPIO(D, 1), GPIO_DIRECTION_INPUT);
}
pinmux->pe6 = PINMUX_INPUT;
pinmux->ph6 = PINMUX_INPUT;
gpio_configure_mode(TEGRA_GPIO(E, 6), GPIO_MODE_GPIO);
gpio_configure_mode(TEGRA_GPIO(H, 6), GPIO_MODE_GPIO);
gpio_configure_direction(TEGRA_GPIO(E, 6), GPIO_DIRECTION_INPUT);
gpio_configure_direction(TEGRA_GPIO(H, 6), GPIO_DIRECTION_INPUT);
i2c_config(I2C_1);
i2c_config(I2C_5);
uart_config(UART_A);
/* Configure volume up/down buttons as inputs. */
gpio_configure_mode(GPIO_BUTTON_VOL_UP, GPIO_MODE_GPIO);
gpio_configure_mode(GPIO_BUTTON_VOL_DOWN, GPIO_MODE_GPIO);
gpio_configure_direction(GPIO_BUTTON_VOL_UP, GPIO_DIRECTION_INPUT);
gpio_configure_direction(GPIO_BUTTON_VOL_DOWN, GPIO_DIRECTION_INPUT);
/* Configure home button as input. */
gpio_configure_mode(TEGRA_GPIO(Y, 1), GPIO_MODE_GPIO);
gpio_configure_direction(TEGRA_GPIO(Y, 1), GPIO_DIRECTION_INPUT);
}
static void config_pmc_scratch(void) {
volatile tegra_pmc_t *pmc = pmc_get_regs(); volatile tegra_pmc_t *pmc = pmc_get_regs();
pmc->scratch20 &= 0xFFF3FFFF; pmc->scratch20 &= 0xFFF3FFFF;
@ -95,8 +128,7 @@ void config_pmc_scratch()
pmc->secure_scratch21 |= 0x10; pmc->secure_scratch21 |= 0x10;
} }
void mbist_workaround() static void mbist_workaround(void) {
{
volatile tegra_car_t *car = car_get_regs(); volatile tegra_car_t *car = car_get_regs();
car->clk_source_sor1 = ((car->clk_source_sor1 | 0x8000) & 0xFFFFBFFF); car->clk_source_sor1 = ((car->clk_source_sor1 | 0x8000) & 0xFFFFBFFF);
@ -151,8 +183,7 @@ void mbist_workaround()
car->clk_source_nvenc = ((car->clk_source_nvenc & 0x1FFFFFFF) | 0x80000000); car->clk_source_nvenc = ((car->clk_source_nvenc & 0x1FFFFFFF) | 0x80000000);
} }
void config_se_brom() static void config_se_brom(void) {
{
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
volatile tegra_se_t *se = se_get_regs(); volatile tegra_se_t *se = se_get_regs();
volatile tegra_pmc_t *pmc = pmc_get_regs(); volatile tegra_pmc_t *pmc = pmc_get_regs();
@ -178,8 +209,7 @@ void config_se_brom()
pmc->reset_status = 0; pmc->reset_status = 0;
} }
void nx_hwinit() void nx_hwinit_erista(bool enable_log) {
{
volatile tegra_pmc_t *pmc = pmc_get_regs(); volatile tegra_pmc_t *pmc = pmc_get_regs();
volatile tegra_car_t *car = car_get_regs(); volatile tegra_car_t *car = car_get_regs();
@ -210,13 +240,13 @@ void nx_hwinit()
/* Configure GPIOs. */ /* Configure GPIOs. */
/* NOTE: [3.0.0+] Part of the GPIO configuration is skipped if the unit is SDEV. */ /* NOTE: [3.0.0+] Part of the GPIO configuration is skipped if the unit is SDEV. */
/* NOTE: [6.0.0+] The GPIO configuration's order was changed a bit. */ /* NOTE: [6.0.0+] The GPIO configuration's order was changed a bit. */
config_gpios(); config_gpios_erista();
/* Uncomment for UART debugging. */ /* UART debugging. */
/* if (enable_log) {
clkrst_reboot(CARDEVICE_UARTC); clkrst_reboot(CARDEVICE_UARTA);
uart_init(UART_C, 115200); uart_init(UART_A, 115200);
*/ }
/* Reboot CL-DVFS. */ /* Reboot CL-DVFS. */
clkrst_reboot(CARDEVICE_CL_DVFS); clkrst_reboot(CARDEVICE_CL_DVFS);
@ -290,8 +320,84 @@ void nx_hwinit()
/* mc_config_carveout(); */ /* mc_config_carveout(); */
/* Initialize SDRAM. */ /* Initialize SDRAM. */
sdram_init(); sdram_init_erista();
/* Save SDRAM LP0 parameters. */ /* Save SDRAM parameters to scratch. */
sdram_lp0_save_params(sdram_get_params()); sdram_save_params_erista(sdram_get_params_erista(fuse_get_dram_id()));
}
void nx_hwinit_mariko(bool enable_log) {
volatile tegra_car_t *car = car_get_regs();
/* Enable SE clock. */
clkrst_reboot(CARDEVICE_SE);
/* Initialize the fuse driver. */
fuse_init();
/* Initialize the memory controller. */
mc_enable();
/* Configure oscillators. */
config_oscillators();
/* Disable pinmux tristate input clamping. */
APB_MISC_PP_PINMUX_GLOBAL_0 = 0;
/* Configure GPIOs. */
config_gpios_mariko();
/* UART debugging. */
if (enable_log) {
clkrst_reboot(CARDEVICE_UARTA);
uart_init(UART_A, 115200);
}
/* Enable CL-DVFS clock. */
clkrst_reboot(CARDEVICE_CL_DVFS);
/* Enable I2C1 clock. */
clkrst_reboot(CARDEVICE_I2C1);
/* Enable I2C5 clock. */
clkrst_reboot(CARDEVICE_I2C5);
/* Enable TZRAM clock. */
clkrst_reboot(CARDEVICE_TZRAM);
/* Initialize I2C5. */
i2c_init(I2C_5);
/* Configure the PMIC. */
uint8_t val = 0x40;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGBBC, &val, 1);
val = 0x78;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &val, 1);
/* Configure SD0 voltage. */
val = 0x24;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD0, &val, 1);
/* Enable LDO8 in HardwareType_Hoag only. */
if (fuse_get_hardware_type() == 2) {
val = 0xE8;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO8_CFG, &val, 1);
}
/* Initialize I2C1. */
i2c_init(I2C_1);
/* Set super clock burst policy. */
car->sclk_brst_pol = ((car->sclk_brst_pol & 0xFFFF8888) | 0x3333);
/* Mariko only PMC configuration. */
MAKE_PMC_REG(0xBE8) &= 0xFFFFFFFE;
MAKE_PMC_REG(0xBF0) = 0x3;
MAKE_PMC_REG(0xBEC) = 0x3;
/* Initialize SDRAM. */
sdram_init_mariko();
/* Save SDRAM parameters to scratch. */
sdram_save_params_mariko(sdram_get_params_mariko(fuse_get_dram_id()));
} }

5
sept/sept-secondary/src/hwinit.h
View file

@ -19,9 +19,12 @@
#ifndef FUSEE_HWINIT_H_ #ifndef FUSEE_HWINIT_H_
#define FUSEE_HWINIT_H_ #define FUSEE_HWINIT_H_
#include <stdbool.h>
#define I2S_BASE 0x702D1000 #define I2S_BASE 0x702D1000
#define MAKE_I2S_REG(n) MAKE_REG32(I2S_BASE + n) #define MAKE_I2S_REG(n) MAKE_REG32(I2S_BASE + n)
void nx_hwinit(); void nx_hwinit_erista(bool enable_log);
void nx_hwinit_mariko(bool enable_log);
#endif #endif

2
sept/sept-secondary/src/main.c
View file

@ -108,7 +108,7 @@ static void setup_env(void) {
g_framebuffer = (void *)0xC0000000; g_framebuffer = (void *)0xC0000000;
/* Initialize hardware. */ /* Initialize hardware. */
nx_hwinit(); nx_hwinit_erista(false);
/* Zero-fill the framebuffer and register it as printk provider. */ /* Zero-fill the framebuffer and register it as printk provider. */
video_init(g_framebuffer); video_init(g_framebuffer);

1
sept/sept-secondary/src/mc.h
View file

@ -497,6 +497,7 @@
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08 #define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08
#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0 #define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0
#define MC_DA_CONFIG0 0x9dc #define MC_DA_CONFIG0 0x9dc
#define MC_UNTRANSLATED_REGION_CHECK 0x948
/* Memory Controller clients */ /* Memory Controller clients */
#define CLIENT_ACCESS_NUM_CLIENTS 32 #define CLIENT_ACCESS_NUM_CLIENTS 32

2551
sept/sept-secondary/src/sdram.c
View file

File diff suppressed because it is too large Load diff

9
sept/sept-secondary/src/sdram.h
View file

@ -18,8 +18,11 @@
#ifndef FUSEE_SDRAM_H_ #ifndef FUSEE_SDRAM_H_
#define FUSEE_SDRAM_H_ #define FUSEE_SDRAM_H_
void sdram_init(); void sdram_init_erista(void);
const void *sdram_get_params(); void sdram_init_mariko(void);
void sdram_lp0_save_params(const void *params); const void *sdram_get_params_erista(uint32_t dram_id);
const void *sdram_get_params_mariko(uint32_t dram_id);
void sdram_save_params_erista(const void *save_params);
void sdram_save_params_mariko(const void *save_params);
#endif #endif

2256
sept/sept-secondary/src/sdram.inl
View file

File diff suppressed because it is too large Load diff

1125
sept/sept-secondary/src/sdram_lp0.c
View file

File diff suppressed because it is too large Load diff

212
sept/sept-secondary/src/sdram_lz.inl
View file

@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2018 naehrwert * Copyright (c) 2018 naehrwert
* Copyright (c) 2018-2020 Atmosphère-NX
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@ -14,7 +15,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>. * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
static const uint8_t _dram_cfg_lz[1262] = { static const uint8_t sdram_params_erista_lz[1262] = {
0x17, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x17, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00,
0x00, 0x2C, 0x17, 0x04, 0x09, 0x00, 0x17, 0x04, 0x04, 0x17, 0x08, 0x08, 0x00, 0x2C, 0x17, 0x04, 0x09, 0x00, 0x17, 0x04, 0x04, 0x17, 0x08, 0x08,
0x17, 0x10, 0x10, 0x00, 0x00, 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, 0x17, 0x10, 0x10, 0x00, 0x00, 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00,
@ -122,3 +123,212 @@ static const uint8_t _dram_cfg_lz[1262] = {
0xAC, 0x38, 0x07, 0x17, 0x0D, 0x8E, 0x68, 0xA3, 0x72, 0x17, 0x83, 0x10, 0xAC, 0x38, 0x07, 0x17, 0x0D, 0x8E, 0x68, 0xA3, 0x72, 0x17, 0x83, 0x10,
0x8E, 0x68 0x8E, 0x68
}; };
static const uint8_t sdram_params_mariko_lz[1727] = {
0x19, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00,
0x00, 0x2C, 0x19, 0x04, 0x09, 0x00, 0x19, 0x04, 0x04, 0x19, 0x08, 0x08,
0x19, 0x10, 0x10, 0x19, 0x20, 0x20, 0x19, 0x40, 0x40, 0x19, 0x2A, 0x2A,
0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x19, 0x04, 0x04, 0x19, 0x09,
0x14, 0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x19, 0x06, 0x0E,
0x88, 0x19, 0x04, 0x04, 0x00, 0x20, 0x12, 0x19, 0x0A, 0x0C, 0x19, 0x06,
0x08, 0x00, 0x00, 0xBC, 0xBC, 0xC5, 0xB3, 0x3C, 0x9E, 0x00, 0x00, 0x02,
0x03, 0xE0, 0xC1, 0x04, 0x04, 0x04, 0x04, 0x19, 0x04, 0x04, 0x19, 0x04,
0x04, 0x3F, 0x3F, 0x3F, 0x3F, 0x19, 0x04, 0x04, 0x19, 0x04, 0x04, 0x19,
0x04, 0x38, 0x04, 0x08, 0x00, 0x00, 0x50, 0x50, 0x50, 0x00, 0xA1, 0x01,
0x00, 0x00, 0x30, 0x19, 0x04, 0x39, 0x10, 0x00, 0x16, 0x00, 0x10, 0x90,
0x19, 0x06, 0x81, 0x00, 0x19, 0x07, 0x74, 0x03, 0x19, 0x04, 0x04, 0x00,
0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x3A, 0x00,
0x00, 0x00, 0x1D, 0x19, 0x0B, 0x81, 0x14, 0x09, 0x00, 0x00, 0x00, 0x04,
0x19, 0x0B, 0x10, 0x0B, 0x19, 0x07, 0x28, 0x08, 0x19, 0x07, 0x0C, 0x19,
0x04, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x15, 0x19, 0x07, 0x08, 0x1B, 0x19,
0x07, 0x28, 0x20, 0x00, 0x00, 0x00, 0x06, 0x19, 0x04, 0x04, 0x19, 0x07,
0x08, 0x19, 0x04, 0x64, 0x19, 0x04, 0x18, 0x19, 0x04, 0x30, 0x19, 0x04,
0x10, 0x19, 0x08, 0x81, 0x00, 0x19, 0x04, 0x10, 0x19, 0x04, 0x4C, 0x0E,
0x00, 0x00, 0x00, 0x05, 0x19, 0x07, 0x1C, 0x19, 0x09, 0x82, 0x24, 0x19,
0x07, 0x6C, 0x19, 0x07, 0x83, 0x57, 0x80, 0x19, 0x04, 0x0A, 0x12, 0x00,
0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x1A, 0x00, 0x00, 0x00, 0x16, 0x19,
0x07, 0x0C, 0x0A, 0x19, 0x04, 0x48, 0x19, 0x07, 0x61, 0xC1, 0x19, 0x07,
0x50, 0x19, 0x04, 0x04, 0x19, 0x04, 0x13, 0x19, 0x04, 0x1C, 0x19, 0x04,
0x08, 0x14, 0x19, 0x07, 0x60, 0x19, 0x08, 0x54, 0x3B, 0x19, 0x04, 0x04,
0x19, 0x07, 0x14, 0x19, 0x04, 0x04, 0x04, 0x19, 0x07, 0x81, 0x6C, 0x19,
0x0C, 0x0C, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91, 0x3F, 0x3A,
0x19, 0x04, 0x5A, 0xF3, 0x0C, 0x04, 0x05, 0x1B, 0x06, 0x02, 0x03, 0x07,
0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A, 0x24, 0x0B, 0x1E,
0x0D, 0x0C, 0x26, 0x26, 0x03, 0x02, 0x1B, 0x1C, 0x23, 0x03, 0x04, 0x07,
0x05, 0x06, 0x25, 0x25, 0x02, 0x0A, 0x0B, 0x1D, 0x0D, 0x08, 0x0C, 0x09,
0x1E, 0x24, 0x26, 0x26, 0x08, 0x24, 0x06, 0x07, 0x9A, 0x19, 0x05, 0x83,
0x3F, 0xFF, 0x00, 0xFF, 0x19, 0x10, 0x84, 0x00, 0x04, 0x00, 0x01, 0x88,
0x00, 0x00, 0x02, 0x88, 0x00, 0x00, 0x0D, 0x88, 0x00, 0x00, 0x00, 0xC0,
0x31, 0x31, 0x03, 0x88, 0x00, 0x00, 0x0B, 0x88, 0x5D, 0x5D, 0x0E, 0x8C,
0x5D, 0x5D, 0x0C, 0x88, 0x08, 0x08, 0x0D, 0x8C, 0x00, 0x00, 0x0D, 0x8C,
0x16, 0x16, 0x16, 0x88, 0x19, 0x06, 0x2C, 0x11, 0x08, 0x19, 0x10, 0x85,
0x5F, 0x10, 0x00, 0xCC, 0x00, 0x0A, 0x00, 0x33, 0x00, 0x00, 0x00, 0x20,
0xF3, 0x25, 0x08, 0x11, 0x19, 0x04, 0x69, 0x0F, 0x19, 0x04, 0x18, 0x19,
0x04, 0x28, 0x01, 0x03, 0x00, 0x70, 0x00, 0x0C, 0x00, 0x01, 0x19, 0x04,
0x0C, 0x08, 0x44, 0x00, 0x10, 0x04, 0x04, 0x00, 0x06, 0x13, 0x07, 0x19,
0x06, 0x1C, 0xA0, 0x00, 0x2C, 0x00, 0x01, 0x37, 0x0F, 0x19, 0x05, 0x82,
0x52, 0x02, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x04, 0x00, 0x1F, 0x22, 0x20,
0x80, 0x0F, 0xF4, 0x20, 0x02, 0x29, 0x29, 0x29, 0x29, 0x19, 0x04, 0x04,
0x19, 0x08, 0x08, 0x78, 0x19, 0x06, 0x85, 0x1A, 0x19, 0x05, 0x58, 0x19,
0x40, 0x85, 0x74, 0x22, 0x00, 0x0E, 0x00, 0x10, 0x19, 0x09, 0x84, 0x22,
0x19, 0x12, 0x18, 0x43, 0x00, 0x49, 0x00, 0x45, 0x00, 0x42, 0x00, 0x47,
0x00, 0x49, 0x00, 0x47, 0x00, 0x46, 0x19, 0x05, 0x83, 0x60, 0x00, 0x00,
0x10, 0x19, 0x18, 0x18, 0x00, 0x28, 0x00, 0x28, 0x19, 0x04, 0x04, 0x19,
0x08, 0x08, 0x19, 0x10, 0x10, 0x00, 0x22, 0x19, 0x05, 0x5A, 0x19, 0x04,
0x5C, 0x19, 0x04, 0x5E, 0x1B, 0x19, 0x05, 0x88, 0x24, 0x19, 0x10, 0x7C,
0x19, 0x09, 0x82, 0x54, 0x40, 0x06, 0x00, 0xCC, 0x00, 0x09, 0x00, 0x4F,
0x00, 0x51, 0x80, 0x19, 0x07, 0x18, 0x19, 0x08, 0x08, 0x19, 0x05, 0x84,
0x40, 0xAB, 0x00, 0x0A, 0x04, 0x11, 0x19, 0x08, 0x82, 0x5C, 0x19, 0x0C,
0x38, 0x19, 0x1C, 0x87, 0x64, 0x19, 0x0B, 0x0C, 0x19, 0x08, 0x89, 0x28,
0x19, 0x05, 0x14, 0x01, 0x22, 0x04, 0xFF, 0x9F, 0xAF, 0x4F, 0x19, 0x09,
0x10, 0x19, 0x0B, 0x28, 0x9F, 0xFF, 0x37, 0x19, 0x06, 0x81, 0x18, 0x32,
0x54, 0x76, 0x10, 0x47, 0x32, 0x65, 0x10, 0x34, 0x76, 0x25, 0x01, 0x34,
0x67, 0x25, 0x01, 0x75, 0x64, 0x32, 0x01, 0x72, 0x56, 0x34, 0x10, 0x23,
0x74, 0x56, 0x01, 0x45, 0x32, 0x67, 0x19, 0x04, 0x24, 0x49, 0x92, 0x24,
0x19, 0x04, 0x04, 0x19, 0x11, 0x78, 0x12, 0x19, 0x04, 0x04, 0x19, 0x13,
0x81, 0x10, 0x20, 0x41, 0x13, 0x1F, 0x14, 0x00, 0x01, 0x00, 0x19, 0x04,
0x7C, 0xFF, 0xFF, 0xFF, 0x7F, 0x1F, 0xD7, 0x36, 0x19, 0x07, 0x89, 0x00,
0x09, 0x00, 0x00, 0x34, 0x10, 0x19, 0x09, 0x87, 0x70, 0x19, 0x14, 0x81,
0x4C, 0x03, 0x00, 0x05, 0x19, 0x05, 0x86, 0x2B, 0x10, 0x02, 0x19, 0x06,
0x87, 0x5D, 0x21, 0x19, 0x07, 0x88, 0x15, 0x19, 0x07, 0x41, 0x19, 0x06,
0x3D, 0x19, 0x07, 0x2C, 0x80, 0x00, 0x40, 0x00, 0x04, 0x10, 0x80, 0x19,
0x05, 0x88, 0x04, 0x81, 0x10, 0x09, 0x28, 0x93, 0x32, 0xA5, 0x44, 0x5B,
0x8A, 0x67, 0x76, 0x19, 0x60, 0x8A, 0x54, 0x10, 0x10, 0x19, 0x04, 0x04,
0x00, 0x00, 0x00, 0xEF, 0x00, 0xEF, 0x19, 0x08, 0x14, 0x1C, 0x1C, 0x1C,
0x1C, 0x19, 0x11, 0x83, 0x18, 0x03, 0x08, 0x19, 0x04, 0x04, 0x00, 0x00,
0x24, 0xFF, 0xFF, 0x00, 0x44, 0x57, 0x6E, 0x00, 0x28, 0x72, 0x39, 0x00,
0x10, 0x9C, 0x4B, 0x00, 0x10, 0x19, 0x05, 0x83, 0x24, 0x08, 0x4C, 0x00,
0x00, 0x80, 0x20, 0x10, 0x0A, 0x00, 0x28, 0x10, 0x00, 0x80, 0x19, 0x08,
0x83, 0x68, 0x19, 0x0C, 0x83, 0x40, 0x19, 0x08, 0x08, 0x05, 0x19, 0x0B,
0x84, 0x0C, 0x04, 0x19, 0x07, 0x10, 0x07, 0x19, 0x06, 0x62, 0x02, 0x01,
0x02, 0x03, 0x00, 0x04, 0x05, 0xA3, 0x72, 0x0F, 0x0F, 0x00, 0x70, 0x19,
0x06, 0x42, 0x1F, 0x19, 0x0A, 0x82, 0x28, 0xFF, 0x00, 0xFF, 0x19, 0x05,
0x87, 0x18, 0x19, 0x07, 0x89, 0x56, 0x19, 0x06, 0x20, 0xF0, 0x19, 0x09,
0x88, 0x24, 0x43, 0xC3, 0xBA, 0xE4, 0xD3, 0x1E, 0x19, 0x0C, 0x8A, 0x0B,
0x19, 0x0A, 0x1C, 0x19, 0x10, 0x81, 0x4C, 0x19, 0x05, 0x44, 0x19, 0x09,
0x0E, 0x19, 0x05, 0x8B, 0x66, 0x19, 0x08, 0x8A, 0x6B, 0x19, 0x11, 0x2C,
0x76, 0x0C, 0x19, 0x0A, 0x8B, 0x4B, 0x19, 0x0F, 0x84, 0x78, 0x19, 0x06,
0x34, 0x19, 0x17, 0x3A, 0x7E, 0x16, 0x40, 0x19, 0x0C, 0x8C, 0x03, 0x19,
0x2A, 0x38, 0x1E, 0x19, 0x0A, 0x38, 0x19, 0x13, 0x81, 0x28, 0x00, 0xC0,
0x19, 0x17, 0x55, 0x46, 0x24, 0x19, 0x0A, 0x81, 0x28, 0x19, 0x14, 0x38,
0x19, 0x18, 0x81, 0x60, 0x46, 0x2C, 0x19, 0x06, 0x38, 0xEC, 0x19, 0x0D,
0x16, 0x19, 0x16, 0x82, 0x3C, 0x19, 0x87, 0x2C, 0x90, 0x38, 0x16, 0x00,
0x0D, 0x00, 0x0B, 0x19, 0x05, 0x84, 0x26, 0x19, 0x16, 0x18, 0x43, 0x00,
0x45, 0x00, 0x45, 0x00, 0x43, 0x00, 0x46, 0x00, 0x47, 0x00, 0x41, 0x00,
0x46, 0x00, 0x0C, 0x19, 0x05, 0x83, 0x3A, 0x0D, 0x19, 0x18, 0x18, 0x19,
0x21, 0x90, 0x38, 0x16, 0x19, 0x05, 0x5A, 0x19, 0x04, 0x5C, 0x19, 0x04,
0x5E, 0x17, 0x19, 0x07, 0x90, 0x70, 0x19, 0x89, 0x5C, 0x90, 0x38, 0x50,
0x05, 0x19, 0x1E, 0x90, 0x38, 0xAF, 0xC9, 0x19, 0x3C, 0x90, 0x38, 0x19,
0x0C, 0x89, 0x30, 0x19, 0x81, 0x0C, 0x90, 0x38, 0x19, 0x04, 0x18, 0x05,
0x19, 0x0F, 0x83, 0x5C, 0x0C, 0x19, 0x81, 0x5A, 0x90, 0x38, 0x08, 0x00,
0x00, 0x02, 0x08, 0x00, 0x00, 0x0D, 0x08, 0x19, 0x07, 0x90, 0x38, 0x08,
0x00, 0x00, 0x0B, 0x08, 0x5D, 0x5D, 0x0E, 0x0C, 0x5D, 0x5D, 0x0C, 0x08,
0x08, 0x08, 0x0D, 0x0C, 0x00, 0x00, 0x0D, 0x0C, 0x14, 0x14, 0x16, 0x08,
0x19, 0x06, 0x2C, 0x19, 0x56, 0x90, 0x38, 0x19, 0x04, 0x30, 0x19, 0x0C,
0x90, 0x38, 0x35, 0x35, 0x35, 0x35, 0x19, 0x04, 0x04, 0x19, 0x81, 0x24,
0x90, 0x38, 0x10, 0x19, 0x05, 0xA0, 0x4A, 0x19, 0x06, 0x06, 0x19, 0x0C,
0x0C, 0x19, 0x08, 0x08, 0x19, 0x37, 0x90, 0x38, 0x19, 0x08, 0x18, 0x80,
0x01, 0x00, 0x00, 0x40, 0x19, 0x82, 0x34, 0x90, 0x38, 0x19, 0x08, 0x12,
0x19, 0x81, 0x14, 0x90, 0x38, 0x19, 0x05, 0x82, 0x74, 0x19, 0x18, 0x90,
0x38, 0x20, 0x19, 0x32, 0x90, 0x38, 0x19, 0x08, 0x10, 0x19, 0x0C, 0x90,
0x38, 0x01, 0x19, 0x49, 0x90, 0x38, 0x80, 0x2A, 0x19, 0x06, 0x84, 0x20,
0x19, 0x95, 0x3E, 0xA0, 0x70, 0x19, 0x83, 0x2C, 0x90, 0x38, 0x14, 0x14,
0x19, 0x4D, 0x90, 0x38, 0x19, 0x05, 0x8A, 0x08, 0x19, 0x87, 0x2A, 0x90,
0x38, 0x19, 0x84, 0x30, 0xA0, 0x70, 0x19, 0x84, 0x7A, 0x90, 0x38, 0x32,
0x32, 0x32, 0x32, 0x19, 0x04, 0x04, 0x19, 0x54, 0x90, 0x38, 0x18, 0x00,
0x0F, 0x19, 0x15, 0x90, 0x38, 0x19, 0x08, 0x18, 0x48, 0x00, 0x44, 0x00,
0x45, 0x00, 0x44, 0x00, 0x47, 0x19, 0x07, 0x90, 0x20, 0x0D, 0x19, 0x05,
0x83, 0x0E, 0x0D, 0x19, 0x18, 0x18, 0x00, 0x78, 0x00, 0x78, 0x19, 0x04,
0x04, 0x19, 0x08, 0x08, 0x19, 0x10, 0x10, 0x00, 0x18, 0x19, 0x05, 0x5A,
0x19, 0x04, 0x5C, 0x19, 0x06, 0x90, 0x38, 0x18, 0x19, 0x8B, 0x57, 0x90,
0x38, 0x19, 0x81, 0x6F, 0xC1, 0x60, 0x19, 0x8D, 0x31, 0xA0, 0x70, 0x19,
0x82, 0x18, 0xD2, 0x18, 0x19, 0x04, 0x34, 0x19, 0x82, 0x00, 0xD2, 0x18,
0x19, 0x82, 0x03, 0x90, 0x38, 0x19, 0x84, 0x1D, 0xD2, 0x18, 0x19, 0x08,
0x83, 0x7C, 0x19, 0x85, 0x16, 0xD2, 0x18, 0x19, 0x82, 0x76, 0xB1, 0x28,
0x19, 0x6F, 0x90, 0x38, 0x19, 0x81, 0x71, 0xA0, 0x70, 0x19, 0x50, 0xB1,
0x28, 0x19, 0x20, 0x90, 0x38, 0x19, 0x84, 0x54, 0xB1, 0x28, 0x19, 0x10,
0x90, 0x38, 0x19, 0x87, 0x04, 0xA0, 0x70, 0x19, 0x81, 0x6F, 0x90, 0x38,
0x19, 0x81, 0x15, 0xA0, 0x70, 0x19, 0x81, 0x2C, 0xC1, 0x60, 0x19, 0x57,
0x90, 0x38, 0x19, 0x8C, 0x51, 0xA0, 0x70, 0x06, 0x1B, 0x04, 0x1C, 0x07,
0x03, 0x05, 0x02, 0x00, 0x25, 0x25, 0x03, 0x00, 0x1E, 0x1D, 0x08, 0x0D,
0x0A, 0x0C, 0x09, 0x0B, 0x26, 0x26, 0x05, 0x02, 0x04, 0x03, 0x05, 0x00,
0x06, 0x1C, 0x1B, 0x07, 0x25, 0x25, 0x07, 0x0A, 0x0B, 0x1D, 0x0C, 0x0D,
0x09, 0x00, 0x08, 0x1E, 0x26, 0x26, 0x09, 0x24, 0x06, 0x08, 0x2A, 0x19,
0x82, 0x0C, 0xA0, 0x70, 0x10, 0x00, 0x14, 0x00, 0x0B, 0x00, 0x13, 0x19,
0x18, 0x18, 0x00, 0x47, 0x00, 0x45, 0x00, 0x4F, 0x00, 0x4D, 0x00, 0x46,
0x00, 0x46, 0x00, 0x48, 0x00, 0x48, 0x00, 0x08, 0x00, 0x0C, 0x00, 0x0C,
0x00, 0x0B, 0x19, 0x18, 0x18, 0x19, 0x21, 0x90, 0x38, 0x10, 0x19, 0x05,
0x5A, 0x19, 0x04, 0x5C, 0x19, 0x04, 0x5E, 0x13, 0x19, 0x13, 0x8D, 0x5D,
0x19, 0x78, 0xA0, 0x70, 0x28, 0x40, 0xFF, 0x9F, 0x9F, 0x19, 0x1D, 0x90,
0x38, 0x57, 0x21, 0x03, 0x64, 0x67, 0x04, 0x32, 0x51, 0x21, 0x56, 0x73,
0x04, 0x12, 0x60, 0x35, 0x47, 0x73, 0x56, 0x04, 0x12, 0x10, 0x72, 0x65,
0x43, 0x37, 0x21, 0x40, 0x65, 0x64, 0x21, 0x30, 0x57, 0x19, 0x3E, 0x90,
0x38, 0x9F, 0x19, 0x06, 0x90, 0x38, 0xCF, 0x33, 0x19, 0x54, 0x90, 0x38,
0x10, 0x08, 0x01, 0x03, 0x00, 0x50, 0x00, 0x40, 0x01, 0x19, 0x06, 0x90,
0x38, 0x08, 0x29, 0x32, 0x93, 0xA5, 0x54, 0x4A, 0x6B, 0x76, 0x87, 0x19,
0x82, 0x29, 0xA0, 0x70, 0xCB, 0xFA, 0xE4, 0xD3, 0xFE, 0x19, 0x82, 0x3A,
0x90, 0x38, 0x9C, 0x19, 0x84, 0x6F, 0xD2, 0x18, 0x19, 0x82, 0x60, 0xB1,
0x28, 0x19, 0x85, 0x44, 0xD2, 0x18, 0x19, 0x83, 0x48, 0xB1, 0x28
};
static const uint32_t sdram_params_index_table_erista[28] = {
0,
1,
2,
3,
4,
5,
6,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
};
static const uint32_t sdram_params_index_table_mariko[28] = {
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0,
1,
2,
3,
4,
1,
2,
3,
4,
5,
6,
7,
6,
8,
9,
0xA,
7,
6,
0xB,
0xB,
0xB,
};

933
sept/sept-secondary/src/sdram_param_t210.h
View file

@ -1,933 +0,0 @@
/*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* See file CREDITS for list of people who contributed to this
* project.
*/
/**
* Defines the SDRAM parameter structure.
*
* Note that PLLM is used by EMC.
*/
#ifndef _SDRAM_PARAM_T210_H_
#define _SDRAM_PARAM_T210_H_
#include <stdint.h>
#define MEMORY_TYPE_NONE 0
#define MEMORY_TYPE_DDR 0
#define MEMORY_TYPE_LPDDR 0
#define MEMORY_TYPE_DDR2 0
#define MEMORY_TYPE_LPDDR2 1
#define MEMORY_TYPE_DDR3 2
#define MEMORY_TYPE_LPDDR4 3
/**
* Defines the SDRAM parameter structure
*/
typedef struct _sdram_params
{
/* Specifies the type of memory device */
uint32_t memory_type;
/* MC/EMC clock source configuration */
/* Specifies the M value for PllM */
uint32_t pllm_input_divider;
/* Specifies the N value for PllM */
uint32_t pllm_feedback_divider;
/* Specifies the time to wait for PLLM to lock (in microseconds) */
uint32_t pllm_stable_time;
/* Specifies misc. control bits */
uint32_t pllm_setup_control;
/* Specifies the P value for PLLM */
uint32_t pllm_post_divider;
/* Specifies value for Charge Pump Gain Control */
uint32_t pllm_kcp;
/* Specifies VCO gain */
uint32_t pllm_kvco;
/* Spare BCT param */
uint32_t emc_bct_spare0;
/* Spare BCT param */
uint32_t emc_bct_spare1;
/* Spare BCT param */
uint32_t emc_bct_spare2;
/* Spare BCT param */
uint32_t emc_bct_spare3;
/* Spare BCT param */
uint32_t emc_bct_spare4;
/* Spare BCT param */
uint32_t emc_bct_spare5;
/* Spare BCT param */
uint32_t emc_bct_spare6;
/* Spare BCT param */
uint32_t emc_bct_spare7;
/* Spare BCT param */
uint32_t emc_bct_spare8;
/* Spare BCT param */
uint32_t emc_bct_spare9;
/* Spare BCT param */
uint32_t emc_bct_spare10;
/* Spare BCT param */
uint32_t emc_bct_spare11;
/* Spare BCT param */
uint32_t emc_bct_spare12;
/* Spare BCT param */
uint32_t emc_bct_spare13;
/* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */
uint32_t emc_clock_source;
uint32_t emc_clock_source_dll;
/* Defines possible override for PLLLM_MISC2 */
uint32_t clk_rst_pllm_misc20_override;
/* enables override for PLLLM_MISC2 */
uint32_t clk_rst_pllm_misc20_override_enable;
/* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */
uint32_t clear_clock2_mc1;
/* Auto-calibration of EMC pads */
/* Specifies the value for EMC_AUTO_CAL_INTERVAL */
uint32_t emc_auto_cal_interval;
/*
* Specifies the value for EMC_AUTO_CAL_CONFIG
* Note: Trigger bits are set by the SDRAM code.
*/
uint32_t emc_auto_cal_config;
/* Specifies the value for EMC_AUTO_CAL_CONFIG2 */
uint32_t emc_auto_cal_config2;
/* Specifies the value for EMC_AUTO_CAL_CONFIG3 */
uint32_t emc_auto_cal_config3;
uint32_t emc_auto_cal_config4;
uint32_t emc_auto_cal_config5;
uint32_t emc_auto_cal_config6;
uint32_t emc_auto_cal_config7;
uint32_t emc_auto_cal_config8;
/* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */
uint32_t emc_auto_cal_vref_sel0;
uint32_t emc_auto_cal_vref_sel1;
/* Specifies the value for EMC_AUTO_CAL_CHANNEL */
uint32_t emc_auto_cal_channel;
/* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */
uint32_t emc_pmacro_auto_cal_cfg0;
uint32_t emc_pmacro_auto_cal_cfg1;
uint32_t emc_pmacro_auto_cal_cfg2;
uint32_t emc_pmacro_rx_term;
uint32_t emc_pmacro_dq_tx_drive;
uint32_t emc_pmacro_ca_tx_drive;
uint32_t emc_pmacro_cmd_tx_drive;
uint32_t emc_pmacro_auto_cal_common;
uint32_t emc_pmacro_zcrtl;
/*
* Specifies the time for the calibration
* to stabilize (in microseconds)
*/
uint32_t emc_auto_cal_wait;
uint32_t emc_xm2_comp_pad_ctrl;
uint32_t emc_xm2_comp_pad_ctrl2;
uint32_t emc_xm2_comp_pad_ctrl3;
/*
* DRAM size information
* Specifies the value for EMC_ADR_CFG
*/
uint32_t emc_adr_cfg;
/*
* Specifies the time to wait after asserting pin
* CKE (in microseconds)
*/
uint32_t emc_pin_program_wait;
/* Specifies the extra delay before/after pin RESET/CKE command */
uint32_t emc_pin_extra_wait;
uint32_t emc_pin_gpio_enable;
uint32_t emc_pin_gpio;
/*
* Specifies the extra delay after the first writing
* of EMC_TIMING_CONTROL
*/
uint32_t emc_timing_control_wait;
/* Timing parameters required for the SDRAM */
/* Specifies the value for EMC_RC */
uint32_t emc_rc;
/* Specifies the value for EMC_RFC */
uint32_t emc_rfc;
uint32_t emc_rfc_pb;
uint32_t emc_ref_ctrl2;
/* Specifies the value for EMC_RFC_SLR */
uint32_t emc_rfc_slr;
/* Specifies the value for EMC_RAS */
uint32_t emc_ras;
/* Specifies the value for EMC_RP */
uint32_t emc_rp;
/* Specifies the value for EMC_R2R */
uint32_t emc_r2r;
/* Specifies the value for EMC_W2W */
uint32_t emc_w2w;
/* Specifies the value for EMC_R2W */
uint32_t emc_r2w;
/* Specifies the value for EMC_W2R */
uint32_t emc_w2r;
/* Specifies the value for EMC_R2P */
uint32_t emc_r2p;
/* Specifies the value for EMC_W2P */
uint32_t emc_w2p;
/* Specifies the value for EMC_RD_RCD */
uint32_t emc_tppd;
uint32_t emc_ccdmw;
uint32_t emc_rd_rcd;
/* Specifies the value for EMC_WR_RCD */
uint32_t emc_wr_rcd;
/* Specifies the value for EMC_RRD */
uint32_t emc_rrd;
/* Specifies the value for EMC_REXT */
uint32_t emc_rext;
/* Specifies the value for EMC_WEXT */
uint32_t emc_wext;
/* Specifies the value for EMC_WDV */
uint32_t emc_wdv;
uint32_t emc_wdv_chk;
uint32_t emc_wsv;
uint32_t emc_wev;
/* Specifies the value for EMC_WDV_MASK */
uint32_t emc_wdv_mask;
uint32_t emc_ws_duration;
uint32_t emc_we_duration;
/* Specifies the value for EMC_QUSE */
uint32_t emc_quse;
/* Specifies the value for EMC_QUSE_WIDTH */
uint32_t emc_quse_width;
/* Specifies the value for EMC_IBDLY */
uint32_t emc_ibdly;
uint32_t emc_obdly;
/* Specifies the value for EMC_EINPUT */
uint32_t emc_einput;
/* Specifies the value for EMC_EINPUT_DURATION */
uint32_t emc_einput_duration;
/* Specifies the value for EMC_PUTERM_EXTRA */
uint32_t emc_puterm_extra;
/* Specifies the value for EMC_PUTERM_WIDTH */
uint32_t emc_puterm_width;
uint32_t emc_qrst;
uint32_t emc_qsafe;
uint32_t emc_rdv;
uint32_t emc_rdv_mask;
uint32_t emc_rdv_early;
uint32_t emc_rdv_early_mask;
/* Specifies the value for EMC_QPOP */
uint32_t emc_qpop;
/* Specifies the value for EMC_REFRESH */
uint32_t emc_refresh;
/* Specifies the value for EMC_BURST_REFRESH_NUM */
uint32_t emc_burst_refresh_num;
/* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */
uint32_t emc_prerefresh_req_cnt;
/* Specifies the value for EMC_PDEX2WR */
uint32_t emc_pdex2wr;
/* Specifies the value for EMC_PDEX2RD */
uint32_t emc_pdex2rd;
/* Specifies the value for EMC_PCHG2PDEN */
uint32_t emc_pchg2pden;
/* Specifies the value for EMC_ACT2PDEN */
uint32_t emc_act2pden;
/* Specifies the value for EMC_AR2PDEN */
uint32_t emc_ar2pden;
/* Specifies the value for EMC_RW2PDEN */
uint32_t emc_rw2pden;
uint32_t emc_cke2pden;
uint32_t emc_pdex2che;
uint32_t emc_pdex2mrr;
/* Specifies the value for EMC_TXSR */
uint32_t emc_txsr;
/* Specifies the value for EMC_TXSRDLL */
uint32_t emc_txsr_dll;
/* Specifies the value for EMC_TCKE */
uint32_t emc_tcke;
/* Specifies the value for EMC_TCKESR */
uint32_t emc_tckesr;
/* Specifies the value for EMC_TPD */
uint32_t emc_tpd;
/* Specifies the value for EMC_TFAW */
uint32_t emc_tfaw;
/* Specifies the value for EMC_TRPAB */
uint32_t emc_trpab;
/* Specifies the value for EMC_TCLKSTABLE */
uint32_t emc_tclkstable;
/* Specifies the value for EMC_TCLKSTOP */
uint32_t emc_tclkstop;
/* Specifies the value for EMC_TREFBW */
uint32_t emc_trefbw;
/* FBIO configuration values */
/* Specifies the value for EMC_FBIO_CFG5 */
uint32_t emc_fbio_cfg5;
/* Specifies the value for EMC_FBIO_CFG7 */
uint32_t emc_fbio_cfg7;
uint32_t emc_fbio_cfg8;
/* Command mapping for CMD brick 0 */
uint32_t emc_cmd_mapping_cmd0_0;
uint32_t emc_cmd_mapping_cmd0_1;
uint32_t emc_cmd_mapping_cmd0_2;
uint32_t emc_cmd_mapping_cmd1_0;
uint32_t emc_cmd_mapping_cmd1_1;
uint32_t emc_cmd_mapping_cmd1_2;
uint32_t emc_cmd_mapping_cmd2_0;
uint32_t emc_cmd_mapping_cmd2_1;
uint32_t emc_cmd_mapping_cmd2_2;
uint32_t emc_cmd_mapping_cmd3_0;
uint32_t emc_cmd_mapping_cmd3_1;
uint32_t emc_cmd_mapping_cmd3_2;
uint32_t emc_cmd_mapping_byte;
/* Specifies the value for EMC_FBIO_SPARE */
uint32_t emc_fbio_spare;
/* Specifies the value for EMC_CFG_RSV */
uint32_t emc_cfg_rsv;
/* MRS command values */
/* Specifies the value for EMC_MRS */
uint32_t emc_mrs;
/* Specifies the MP0 command to initialize mode registers */
uint32_t emc_emrs;
/* Specifies the MP2 command to initialize mode registers */
uint32_t emc_emrs2;
/* Specifies the MP3 command to initialize mode registers */
uint32_t emc_emrs3;
/* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */
uint32_t emc_mrw1;
/* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */
uint32_t emc_mrw2;
/* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */
uint32_t emc_mrw3;
/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
uint32_t emc_mrw4;
/* Specifies the programming to LPDDR4 Mode Register 3 at cold boot */
uint32_t emc_mrw6;
/* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */
uint32_t emc_mrw8;
/* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */
uint32_t emc_mrw9;
/* Specifies the programming to LPDDR4 Mode Register 12 at cold boot */
uint32_t emc_mrw10;
/* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */
uint32_t emc_mrw12;
/* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */
uint32_t emc_mrw13;
/* Specifies the programming to LPDDR4 Mode Register 22 at cold boot */
uint32_t emc_mrw14;
/*
* Specifies the programming to extra LPDDR2 Mode Register
* at cold boot
*/
uint32_t emc_mrw_extra;
/*
* Specifies the programming to extra LPDDR2 Mode Register
* at warm boot
*/
uint32_t emc_warm_boot_mrw_extra;
/*
* Specify the enable of extra Mode Register programming at
* warm boot
*/
uint32_t emc_warm_boot_extramode_reg_write_enable;
/*
* Specify the enable of extra Mode Register programming at
* cold boot
*/
uint32_t emc_extramode_reg_write_enable;
/* Specifies the EMC_MRW reset command value */
uint32_t emc_mrw_reset_command;
/* Specifies the EMC Reset wait time (in microseconds) */
uint32_t emc_mrw_reset_ninit_wait;
/* Specifies the value for EMC_MRS_WAIT_CNT */
uint32_t emc_mrs_wait_cnt;
/* Specifies the value for EMC_MRS_WAIT_CNT2 */
uint32_t emc_mrs_wait_cnt2;
/* EMC miscellaneous configurations */
/* Specifies the value for EMC_CFG */
uint32_t emc_cfg;
/* Specifies the value for EMC_CFG_2 */
uint32_t emc_cfg2;
/* Specifies the pipe bypass controls */
uint32_t emc_cfg_pipe;
uint32_t emc_cfg_pipe_clk;
uint32_t emc_fdpd_ctrl_cmd_no_ramp;
uint32_t emc_cfg_update;
/* Specifies the value for EMC_DBG */
uint32_t emc_dbg;
uint32_t emc_dbg_write_mux;
/* Specifies the value for EMC_CMDQ */
uint32_t emc_cmd_q;
/* Specifies the value for EMC_MC2EMCQ */
uint32_t emc_mc2emc_q;
/* Specifies the value for EMC_DYN_SELF_REF_CONTROL */
uint32_t emc_dyn_self_ref_control;
/* Specifies the value for MEM_INIT_DONE */
uint32_t ahb_arbitration_xbar_ctrl_meminit_done;
/* Specifies the value for EMC_CFG_DIG_DLL */
uint32_t emc_cfg_dig_dll;
uint32_t emc_cfg_dig_dll_1;
/* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */
uint32_t emc_cfg_dig_dll_period;
/* Specifies the value of *DEV_SELECTN of various EMC registers */
uint32_t emc_dev_select;
/* Specifies the value for EMC_SEL_DPD_CTRL */
uint32_t emc_sel_dpd_ctrl;
/* Pads trimmer delays */
uint32_t emc_fdpd_ctrl_dq;
uint32_t emc_fdpd_ctrl_cmd;
uint32_t emc_pmacro_ib_vref_dq_0;
uint32_t emc_pmacro_ib_vref_dq_1;
uint32_t emc_pmacro_ib_vref_dqs_0;
uint32_t emc_pmacro_ib_vref_dqs_1;
uint32_t emc_pmacro_ib_rxrt;
uint32_t emc_cfg_pipe1;
uint32_t emc_cfg_pipe2;
/* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */
uint32_t emc_pmacro_quse_ddll_rank0_0;
uint32_t emc_pmacro_quse_ddll_rank0_1;
uint32_t emc_pmacro_quse_ddll_rank0_2;
uint32_t emc_pmacro_quse_ddll_rank0_3;
uint32_t emc_pmacro_quse_ddll_rank0_4;
uint32_t emc_pmacro_quse_ddll_rank0_5;
uint32_t emc_pmacro_quse_ddll_rank1_0;
uint32_t emc_pmacro_quse_ddll_rank1_1;
uint32_t emc_pmacro_quse_ddll_rank1_2;
uint32_t emc_pmacro_quse_ddll_rank1_3;
uint32_t emc_pmacro_quse_ddll_rank1_4;
uint32_t emc_pmacro_quse_ddll_rank1_5;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_0;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_1;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_2;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_3;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_4;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_5;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_0;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_1;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_2;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_3;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_0;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_1;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_2;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_3;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_0;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_1;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_2;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_3;
uint32_t emc_pmacro_ddll_long_cmd_0;
uint32_t emc_pmacro_ddll_long_cmd_1;
uint32_t emc_pmacro_ddll_long_cmd_2;
uint32_t emc_pmacro_ddll_long_cmd_3;
uint32_t emc_pmacro_ddll_long_cmd_4;
uint32_t emc_pmacro_ddll_short_cmd_0;
uint32_t emc_pmacro_ddll_short_cmd_1;
uint32_t emc_pmacro_ddll_short_cmd_2;
/*
* Specifies the delay after asserting CKE pin during a WarmBoot0
* sequence (in microseconds)
*/
uint32_t warm_boot_wait;
/* Specifies the value for EMC_ODT_WRITE */
uint32_t emc_odt_write;
/* Periodic ZQ calibration */
/*
* Specifies the value for EMC_ZCAL_INTERVAL
* Value 0 disables ZQ calibration
*/
uint32_t emc_zcal_interval;
/* Specifies the value for EMC_ZCAL_WAIT_CNT */
uint32_t emc_zcal_wait_cnt;
/* Specifies the value for EMC_ZCAL_MRW_CMD */
uint32_t emc_zcal_mrw_cmd;
/* DRAM initialization sequence flow control */
/* Specifies the MRS command value for resetting DLL */
uint32_t emc_mrs_reset_dll;
/* Specifies the command for ZQ initialization of device 0 */
uint32_t emc_zcal_init_dev0;
/* Specifies the command for ZQ initialization of device 1 */
uint32_t emc_zcal_init_dev1;
/*
* Specifies the wait time after programming a ZQ initialization
* command (in microseconds)
*/
uint32_t emc_zcal_init_wait;
/*
* Specifies the enable for ZQ calibration at cold boot [bit 0]
* and warm boot [bit 1]
*/
uint32_t emc_zcal_warm_cold_boot_enables;
/*
* Specifies the MRW command to LPDDR2 for ZQ calibration
* on warmboot
*/
/* Is issued to both devices separately */
uint32_t emc_mrw_lpddr2zcal_warm_boot;
/*
* Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
* Is issued to both devices separately
*/
uint32_t emc_zqcal_ddr3_warm_boot;
uint32_t emc_zqcal_lpddr4_warm_boot;
/*
* Specifies the wait time for ZQ calibration on warmboot
* (in microseconds)
*/
uint32_t emc_zcal_warm_boot_wait;
/*
* Specifies the enable for DRAM Mode Register programming
* at warm boot
*/
uint32_t emc_mrs_warm_boot_enable;
/*
* Specifies the wait time after sending an MRS DLL reset command
* in microseconds)
*/
uint32_t emc_mrs_reset_dll_wait;
/* Specifies the extra MRS command to initialize mode registers */
uint32_t emc_mrs_extra;
/* Specifies the extra MRS command at warm boot */
uint32_t emc_warm_boot_mrs_extra;
/* Specifies the EMRS command to enable the DDR2 DLL */
uint32_t emc_emrs_ddr2_dll_enable;
/* Specifies the MRS command to reset the DDR2 DLL */
uint32_t emc_mrs_ddr2_dll_reset;
/* Specifies the EMRS command to set OCD calibration */
uint32_t emc_emrs_ddr2_ocd_calib;
/*
* Specifies the wait between initializing DDR and setting OCD
* calibration (in microseconds)
*/
uint32_t emc_ddr2_wait;
/* Specifies the value for EMC_CLKEN_OVERRIDE */
uint32_t emc_clken_override;
/*
* Specifies LOG2 of the extra refresh numbers after booting
* Program 0 to disable
*/
uint32_t emc_extra_refresh_num;
/* Specifies the master override for all EMC clocks */
uint32_t emc_clken_override_allwarm_boot;
/* Specifies the master override for all MC clocks */
uint32_t mc_clken_override_allwarm_boot;
/* Specifies digital dll period, choosing between 4 to 64 ms */
uint32_t emc_cfg_dig_dll_period_warm_boot;
/* Pad controls */
/* Specifies the value for PMC_VDDP_SEL */
uint32_t pmc_vddp_sel;
/* Specifies the wait time after programming PMC_VDDP_SEL */
uint32_t pmc_vddp_sel_wait;
/* Specifies the value for PMC_DDR_PWR */
uint32_t pmc_ddr_pwr;
/* Specifies the value for PMC_DDR_CFG */
uint32_t pmc_ddr_cfg;
/* Specifies the value for PMC_IO_DPD3_REQ */
uint32_t pmc_io_dpd3_req;
/* Specifies the wait time after programming PMC_IO_DPD3_REQ */
uint32_t pmc_io_dpd3_req_wait;
uint32_t pmc_io_dpd4_req_wait;
/* Specifies the value for PMC_REG_SHORT */
uint32_t pmc_reg_short;
/* Specifies the value for PMC_NO_IOPOWER */
uint32_t pmc_no_io_power;
uint32_t pmc_ddr_ctrl_wait;
uint32_t pmc_ddr_ctrl;
/* Specifies the value for EMC_ACPD_CONTROL */
uint32_t emc_acpd_control;
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */
uint32_t emc_swizzle_rank0_byte0;
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */
uint32_t emc_swizzle_rank0_byte1;
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */
uint32_t emc_swizzle_rank0_byte2;
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */
uint32_t emc_swizzle_rank0_byte3;
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */
uint32_t emc_swizzle_rank1_byte0;
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */
uint32_t emc_swizzle_rank1_byte1;
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */
uint32_t emc_swizzle_rank1_byte2;
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */
uint32_t emc_swizzle_rank1_byte3;
/* Specifies the value for EMC_TXDSRVTTGEN */
uint32_t emc_txdsrvttgen;
/* Specifies the value for EMC_DATA_BRLSHFT_0 */
uint32_t emc_data_brlshft0;
uint32_t emc_data_brlshft1;
uint32_t emc_dqs_brlshft0;
uint32_t emc_dqs_brlshft1;
uint32_t emc_cmd_brlshft0;
uint32_t emc_cmd_brlshft1;
uint32_t emc_cmd_brlshft2;
uint32_t emc_cmd_brlshft3;
uint32_t emc_quse_brlshft0;
uint32_t emc_quse_brlshft1;
uint32_t emc_quse_brlshft2;
uint32_t emc_quse_brlshft3;
uint32_t emc_dll_cfg0;
uint32_t emc_dll_cfg1;
uint32_t emc_pmc_scratch1;
uint32_t emc_pmc_scratch2;
uint32_t emc_pmc_scratch3;
uint32_t emc_pmacro_pad_cfg_ctrl;
uint32_t emc_pmacro_vttgen_ctrl0;
uint32_t emc_pmacro_vttgen_ctrl1;
uint32_t emc_pmacro_vttgen_ctrl2;
uint32_t emc_pmacro_brick_ctrl_rfu1;
uint32_t emc_pmacro_cmd_brick_ctrl_fdpd;
uint32_t emc_pmacro_brick_ctrl_rfu2;
uint32_t emc_pmacro_data_brick_ctrl_fdpd;
uint32_t emc_pmacro_bg_bias_ctrl0;
uint32_t emc_pmacro_data_pad_rx_ctrl;
uint32_t emc_pmacro_cmd_pad_rx_ctrl;
uint32_t emc_pmacro_data_rx_term_mode;
uint32_t emc_pmacro_cmd_rx_term_mode;
uint32_t emc_pmacro_data_pad_tx_ctrl;
uint32_t emc_pmacro_common_pad_tx_ctrl;
uint32_t emc_pmacro_cmd_pad_tx_ctrl;
uint32_t emc_cfg3;
uint32_t emc_pmacro_tx_pwrd0;
uint32_t emc_pmacro_tx_pwrd1;
uint32_t emc_pmacro_tx_pwrd2;
uint32_t emc_pmacro_tx_pwrd3;
uint32_t emc_pmacro_tx_pwrd4;
uint32_t emc_pmacro_tx_pwrd5;
uint32_t emc_config_sample_delay;
uint32_t emc_pmacro_brick_mapping0;
uint32_t emc_pmacro_brick_mapping1;
uint32_t emc_pmacro_brick_mapping2;
uint32_t emc_pmacro_tx_sel_clk_src0;
uint32_t emc_pmacro_tx_sel_clk_src1;
uint32_t emc_pmacro_tx_sel_clk_src2;
uint32_t emc_pmacro_tx_sel_clk_src3;
uint32_t emc_pmacro_tx_sel_clk_src4;
uint32_t emc_pmacro_tx_sel_clk_src5;
uint32_t emc_pmacro_ddll_bypass;
uint32_t emc_pmacro_ddll_pwrd0;
uint32_t emc_pmacro_ddll_pwrd1;
uint32_t emc_pmacro_ddll_pwrd2;
uint32_t emc_pmacro_cmd_ctrl0;
uint32_t emc_pmacro_cmd_ctrl1;
uint32_t emc_pmacro_cmd_ctrl2;
/* DRAM size information */
/* Specifies the value for MC_EMEM_ADR_CFG */
uint32_t mc_emem_adr_cfg;
/* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */
uint32_t mc_emem_adr_cfg_dev0;
/* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */
uint32_t mc_emem_adr_cfg_dev1;
uint32_t mc_emem_adr_cfg_channel_mask;
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */
uint32_t mc_emem_adr_cfg_bank_mask0;
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */
uint32_t mc_emem_adr_cfg_bank_mask1;
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */
uint32_t mc_emem_adr_cfg_bank_mask2;
/*
* Specifies the value for MC_EMEM_CFG which holds the external memory
* size (in KBytes)
*/
uint32_t mc_emem_cfg;
/* MC arbitration configuration */
/* Specifies the value for MC_EMEM_ARB_CFG */
uint32_t mc_emem_arb_cfg;
/* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */
uint32_t mc_emem_arb_outstanding_req;
uint32_t emc_emem_arb_refpb_hp_ctrl;
uint32_t emc_emem_arb_refpb_bank_ctrl;
/* Specifies the value for MC_EMEM_ARB_TIMING_RCD */
uint32_t mc_emem_arb_timing_rcd;
/* Specifies the value for MC_EMEM_ARB_TIMING_RP */
uint32_t mc_emem_arb_timing_rp;
/* Specifies the value for MC_EMEM_ARB_TIMING_RC */
uint32_t mc_emem_arb_timing_rc;
/* Specifies the value for MC_EMEM_ARB_TIMING_RAS */
uint32_t mc_emem_arb_timing_ras;
/* Specifies the value for MC_EMEM_ARB_TIMING_FAW */
uint32_t mc_emem_arb_timing_faw;
/* Specifies the value for MC_EMEM_ARB_TIMING_RRD */
uint32_t mc_emem_arb_timing_rrd;
/* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */
uint32_t mc_emem_arb_timing_rap2pre;
/* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */
uint32_t mc_emem_arb_timing_wap2pre;
/* Specifies the value for MC_EMEM_ARB_TIMING_R2R */
uint32_t mc_emem_arb_timing_r2r;
/* Specifies the value for MC_EMEM_ARB_TIMING_W2W */
uint32_t mc_emem_arb_timing_w2w;
/* Specifies the value for MC_EMEM_ARB_TIMING_R2W */
uint32_t mc_emem_arb_timing_r2w;
/* Specifies the value for MC_EMEM_ARB_TIMING_W2R */
uint32_t mc_emem_arb_timing_w2r;
uint32_t mc_emem_arb_timing_rfcpb;
/* Specifies the value for MC_EMEM_ARB_DA_TURNS */
uint32_t mc_emem_arb_da_turns;
/* Specifies the value for MC_EMEM_ARB_DA_COVERS */
uint32_t mc_emem_arb_da_covers;
/* Specifies the value for MC_EMEM_ARB_MISC0 */
uint32_t mc_emem_arb_misc0;
/* Specifies the value for MC_EMEM_ARB_MISC1 */
uint32_t mc_emem_arb_misc1;
uint32_t mc_emem_arb_misc2;
/* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */
uint32_t mc_emem_arb_ring1_throttle;
/* Specifies the value for MC_EMEM_ARB_OVERRIDE */
uint32_t mc_emem_arb_override;
/* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */
uint32_t mc_emem_arb_override1;
/* Specifies the value for MC_EMEM_ARB_RSV */
uint32_t mc_emem_arb_rsv;
uint32_t mc_da_cfg0;
uint32_t mc_emem_arb_timing_ccdmw;
/* Specifies the value for MC_CLKEN_OVERRIDE */
uint32_t mc_clken_override;
/* Specifies the value for MC_STAT_CONTROL */
uint32_t mc_stat_control;
/* Specifies the value for MC_VIDEO_PROTECT_BOM */
uint32_t mc_video_protect_bom;
/* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */
uint32_t mc_video_protect_bom_adr_hi;
/* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */
uint32_t mc_video_protect_size_mb;
/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */
uint32_t mc_video_protect_vpr_override;
/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */
uint32_t mc_video_protect_vpr_override1;
/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */
uint32_t mc_video_protect_gpu_override0;
/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */
uint32_t mc_video_protect_gpu_override1;
/* Specifies the value for MC_SEC_CARVEOUT_BOM */
uint32_t mc_sec_carveout_bom;
/* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */
uint32_t mc_sec_carveout_adr_hi;
/* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */
uint32_t mc_sec_carveout_size_mb;
/* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */
uint32_t mc_video_protect_write_access;
/* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */
uint32_t mc_sec_carveout_protect_write_access;
uint32_t mc_generalized_carveout1_bom;
uint32_t mc_generalized_carveout1_bom_hi;
uint32_t mc_generalized_carveout1_size_128kb;
uint32_t mc_generalized_carveout1_access0;
uint32_t mc_generalized_carveout1_access1;
uint32_t mc_generalized_carveout1_access2;
uint32_t mc_generalized_carveout1_access3;
uint32_t mc_generalized_carveout1_access4;
uint32_t mc_generalized_carveout1_force_internal_access0;
uint32_t mc_generalized_carveout1_force_internal_access1;
uint32_t mc_generalized_carveout1_force_internal_access2;
uint32_t mc_generalized_carveout1_force_internal_access3;
uint32_t mc_generalized_carveout1_force_internal_access4;
uint32_t mc_generalized_carveout1_cfg0;
uint32_t mc_generalized_carveout2_bom;
uint32_t mc_generalized_carveout2_bom_hi;
uint32_t mc_generalized_carveout2_size_128kb;
uint32_t mc_generalized_carveout2_access0;
uint32_t mc_generalized_carveout2_access1;
uint32_t mc_generalized_carveout2_access2;
uint32_t mc_generalized_carveout2_access3;
uint32_t mc_generalized_carveout2_access4;
uint32_t mc_generalized_carveout2_force_internal_access0;
uint32_t mc_generalized_carveout2_force_internal_access1;
uint32_t mc_generalized_carveout2_force_internal_access2;
uint32_t mc_generalized_carveout2_force_internal_access3;
uint32_t mc_generalized_carveout2_force_internal_access4;
uint32_t mc_generalized_carveout2_cfg0;
uint32_t mc_generalized_carveout3_bom;
uint32_t mc_generalized_carveout3_bom_hi;
uint32_t mc_generalized_carveout3_size_128kb;
uint32_t mc_generalized_carveout3_access0;
uint32_t mc_generalized_carveout3_access1;
uint32_t mc_generalized_carveout3_access2;
uint32_t mc_generalized_carveout3_access3;
uint32_t mc_generalized_carveout3_access4;
uint32_t mc_generalized_carveout3_force_internal_access0;
uint32_t mc_generalized_carveout3_force_internal_access1;
uint32_t mc_generalized_carveout3_force_internal_access2;
uint32_t mc_generalized_carveout3_force_internal_access3;
uint32_t mc_generalized_carveout3_force_internal_access4;
uint32_t mc_generalized_carveout3_cfg0;
uint32_t mc_generalized_carveout4_bom;
uint32_t mc_generalized_carveout4_bom_hi;
uint32_t mc_generalized_carveout4_size_128kb;
uint32_t mc_generalized_carveout4_access0;
uint32_t mc_generalized_carveout4_access1;
uint32_t mc_generalized_carveout4_access2;
uint32_t mc_generalized_carveout4_access3;
uint32_t mc_generalized_carveout4_access4;
uint32_t mc_generalized_carveout4_force_internal_access0;
uint32_t mc_generalized_carveout4_force_internal_access1;
uint32_t mc_generalized_carveout4_force_internal_access2;
uint32_t mc_generalized_carveout4_force_internal_access3;
uint32_t mc_generalized_carveout4_force_internal_access4;
uint32_t mc_generalized_carveout4_cfg0;
uint32_t mc_generalized_carveout5_bom;
uint32_t mc_generalized_carveout5_bom_hi;
uint32_t mc_generalized_carveout5_size_128kb;
uint32_t mc_generalized_carveout5_access0;
uint32_t mc_generalized_carveout5_access1;
uint32_t mc_generalized_carveout5_access2;
uint32_t mc_generalized_carveout5_access3;
uint32_t mc_generalized_carveout5_access4;
uint32_t mc_generalized_carveout5_force_internal_access0;
uint32_t mc_generalized_carveout5_force_internal_access1;
uint32_t mc_generalized_carveout5_force_internal_access2;
uint32_t mc_generalized_carveout5_force_internal_access3;
uint32_t mc_generalized_carveout5_force_internal_access4;
uint32_t mc_generalized_carveout5_cfg0;
/* Specifies enable for CA training */
uint32_t emc_ca_training_enable;
/* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */
uint32_t swizzle_rank_byte_encode;
/* Specifies enable and offset for patched boot rom write */
uint32_t boot_rom_patch_control;
/* Specifies data for patched boot rom write */
uint32_t boot_rom_patch_data;
/* Specifies the value for MC_MTS_CARVEOUT_BOM */
uint32_t mc_mts_carveout_bom;
/* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */
uint32_t mc_mts_carveout_adr_hi;
/* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */
uint32_t mc_mts_carveout_size_mb;
/* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */
uint32_t mc_mts_carveout_reg_ctrl;
} sdram_params_t;
#endif

964
sept/sept-secondary/src/sdram_param_t210_lp0.h
View file

@ -1,964 +0,0 @@
/*
* Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved.
* Copyright 2014 Google Inc.
* Copyright (c) 2018 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
/**
* Defines the SDRAM parameter structure.
*
* Note that PLLM is used by EMC. The field names are in camel case to ease
* directly converting BCT config files (*.cfg) into C structure.
*/
#ifndef __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__
#define __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__
#include <stdint.h>
enum
{
/* Specifies the memory type to be undefined */
NvBootMemoryType_None = 0,
/* Specifies the memory type to be DDR SDRAM */
NvBootMemoryType_Ddr = 0,
/* Specifies the memory type to be LPDDR SDRAM */
NvBootMemoryType_LpDdr = 0,
/* Specifies the memory type to be DDR2 SDRAM */
NvBootMemoryType_Ddr2 = 0,
/* Specifies the memory type to be LPDDR2 SDRAM */
NvBootMemoryType_LpDdr2,
/* Specifies the memory type to be DDR3 SDRAM */
NvBootMemoryType_Ddr3,
/* Specifies the memory type to be LPDDR4 SDRAM */
NvBootMemoryType_LpDdr4,
NvBootMemoryType_Num,
/* Specifies an entry in the ram_code table that's not in use */
NvBootMemoryType_Unused = 0X7FFFFFF,
};
/**
* Defines the SDRAM parameter structure
*/
struct sdram_params
{
/* Specifies the type of memory device */
uint32_t MemoryType;
/* MC/EMC clock source configuration */
/* Specifies the M value for PllM */
uint32_t PllMInputDivider;
/* Specifies the N value for PllM */
uint32_t PllMFeedbackDivider;
/* Specifies the time to wait for PLLM to lock (in microseconds) */
uint32_t PllMStableTime;
/* Specifies misc. control bits */
uint32_t PllMSetupControl;
/* Specifies the P value for PLLM */
uint32_t PllMPostDivider;
/* Specifies value for Charge Pump Gain Control */
uint32_t PllMKCP;
/* Specifies VCO gain */
uint32_t PllMKVCO;
/* Spare BCT param */
uint32_t EmcBctSpare0;
/* Spare BCT param */
uint32_t EmcBctSpare1;
/* Spare BCT param */
uint32_t EmcBctSpare2;
/* Spare BCT param */
uint32_t EmcBctSpare3;
/* Spare BCT param */
uint32_t EmcBctSpare4;
/* Spare BCT param */
uint32_t EmcBctSpare5;
/* Spare BCT param */
uint32_t EmcBctSpare6;
/* Spare BCT param */
uint32_t EmcBctSpare7;
/* Spare BCT param */
uint32_t EmcBctSpare8;
/* Spare BCT param */
uint32_t EmcBctSpare9;
/* Spare BCT param */
uint32_t EmcBctSpare10;
/* Spare BCT param */
uint32_t EmcBctSpare11;
/* Spare BCT param */
uint32_t EmcBctSpare12;
/* Spare BCT param */
uint32_t EmcBctSpare13;
/* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */
uint32_t EmcClockSource;
uint32_t EmcClockSourceDll;
/* Defines possible override for PLLLM_MISC2 */
uint32_t ClkRstControllerPllmMisc2Override;
/* enables override for PLLLM_MISC2 */
uint32_t ClkRstControllerPllmMisc2OverrideEnable;
/* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */
uint32_t ClearClk2Mc1;
/* Auto-calibration of EMC pads */
/* Specifies the value for EMC_AUTO_CAL_INTERVAL */
uint32_t EmcAutoCalInterval;
/*
* Specifies the value for EMC_AUTO_CAL_CONFIG
* Note: Trigger bits are set by the SDRAM code.
*/
uint32_t EmcAutoCalConfig;
/* Specifies the value for EMC_AUTO_CAL_CONFIG2 */
uint32_t EmcAutoCalConfig2;
/* Specifies the value for EMC_AUTO_CAL_CONFIG3 */
uint32_t EmcAutoCalConfig3;
/* Specifies the values for EMC_AUTO_CAL_CONFIG4-8 */
uint32_t EmcAutoCalConfig4;
uint32_t EmcAutoCalConfig5;
uint32_t EmcAutoCalConfig6;
uint32_t EmcAutoCalConfig7;
uint32_t EmcAutoCalConfig8;
/* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */
uint32_t EmcAutoCalVrefSel0;
uint32_t EmcAutoCalVrefSel1;
/* Specifies the value for EMC_AUTO_CAL_CHANNEL */
uint32_t EmcAutoCalChannel;
/* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */
uint32_t EmcPmacroAutocalCfg0;
uint32_t EmcPmacroAutocalCfg1;
uint32_t EmcPmacroAutocalCfg2;
uint32_t EmcPmacroRxTerm;
uint32_t EmcPmacroDqTxDrv;
uint32_t EmcPmacroCaTxDrv;
uint32_t EmcPmacroCmdTxDrv;
uint32_t EmcPmacroAutocalCfgCommon;
uint32_t EmcPmacroZctrl;
/*
* Specifies the time for the calibration
* to stabilize (in microseconds)
*/
uint32_t EmcAutoCalWait;
uint32_t EmcXm2CompPadCtrl;
uint32_t EmcXm2CompPadCtrl2;
uint32_t EmcXm2CompPadCtrl3;
/*
* DRAM size information
* Specifies the value for EMC_ADR_CFG
*/
uint32_t EmcAdrCfg;
/*
* Specifies the time to wait after asserting pin
* CKE (in microseconds)
*/
uint32_t EmcPinProgramWait;
/* Specifies the extra delay before/after pin RESET/CKE command */
uint32_t EmcPinExtraWait;
uint32_t EmcPinGpioEn;
uint32_t EmcPinGpio;
/*
* Specifies the extra delay after the first writing
* of EMC_TIMING_CONTROL
*/
uint32_t EmcTimingControlWait;
/* Timing parameters required for the SDRAM */
/* Specifies the value for EMC_RC */
uint32_t EmcRc;
/* Specifies the value for EMC_RFC */
uint32_t EmcRfc;
/* Specifies the value for EMC_RFC_PB */
uint32_t EmcRfcPb;
/* Specifies the value for EMC_RFC_CTRL2 */
uint32_t EmcRefctrl2;
/* Specifies the value for EMC_RFC_SLR */
uint32_t EmcRfcSlr;
/* Specifies the value for EMC_RAS */
uint32_t EmcRas;
/* Specifies the value for EMC_RP */
uint32_t EmcRp;
/* Specifies the value for EMC_R2R */
uint32_t EmcR2r;
/* Specifies the value for EMC_W2W */
uint32_t EmcW2w;
/* Specifies the value for EMC_R2W */
uint32_t EmcR2w;
/* Specifies the value for EMC_W2R */
uint32_t EmcW2r;
/* Specifies the value for EMC_R2P */
uint32_t EmcR2p;
/* Specifies the value for EMC_W2P */
uint32_t EmcW2p;
uint32_t EmcTppd;
uint32_t EmcCcdmw;
/* Specifies the value for EMC_RD_RCD */
uint32_t EmcRdRcd;
/* Specifies the value for EMC_WR_RCD */
uint32_t EmcWrRcd;
/* Specifies the value for EMC_RRD */
uint32_t EmcRrd;
/* Specifies the value for EMC_REXT */
uint32_t EmcRext;
/* Specifies the value for EMC_WEXT */
uint32_t EmcWext;
/* Specifies the value for EMC_WDV */
uint32_t EmcWdv;
uint32_t EmcWdvChk;
uint32_t EmcWsv;
uint32_t EmcWev;
/* Specifies the value for EMC_WDV_MASK */
uint32_t EmcWdvMask;
uint32_t EmcWsDuration;
uint32_t EmcWeDuration;
/* Specifies the value for EMC_QUSE */
uint32_t EmcQUse;
/* Specifies the value for EMC_QUSE_WIDTH */
uint32_t EmcQuseWidth;
/* Specifies the value for EMC_IBDLY */
uint32_t EmcIbdly;
/* Specifies the value for EMC_OBDLY */
uint32_t EmcObdly;
/* Specifies the value for EMC_EINPUT */
uint32_t EmcEInput;
/* Specifies the value for EMC_EINPUT_DURATION */
uint32_t EmcEInputDuration;
/* Specifies the value for EMC_PUTERM_EXTRA */
uint32_t EmcPutermExtra;
/* Specifies the value for EMC_PUTERM_WIDTH */
uint32_t EmcPutermWidth;
/* Specifies the value for EMC_PUTERM_ADJ */
////uint32_t EmcPutermAdj;
/* Specifies the value for EMC_QRST */
uint32_t EmcQRst;
/* Specifies the value for EMC_QSAFE */
uint32_t EmcQSafe;
/* Specifies the value for EMC_RDV */
uint32_t EmcRdv;
/* Specifies the value for EMC_RDV_MASK */
uint32_t EmcRdvMask;
/* Specifies the value for EMC_RDV_EARLY */
uint32_t EmcRdvEarly;
/* Specifies the value for EMC_RDV_EARLY_MASK */
uint32_t EmcRdvEarlyMask;
/* Specifies the value for EMC_QPOP */
uint32_t EmcQpop;
/* Specifies the value for EMC_REFRESH */
uint32_t EmcRefresh;
/* Specifies the value for EMC_BURST_REFRESH_NUM */
uint32_t EmcBurstRefreshNum;
/* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */
uint32_t EmcPreRefreshReqCnt;
/* Specifies the value for EMC_PDEX2WR */
uint32_t EmcPdEx2Wr;
/* Specifies the value for EMC_PDEX2RD */
uint32_t EmcPdEx2Rd;
/* Specifies the value for EMC_PCHG2PDEN */
uint32_t EmcPChg2Pden;
/* Specifies the value for EMC_ACT2PDEN */
uint32_t EmcAct2Pden;
/* Specifies the value for EMC_AR2PDEN */
uint32_t EmcAr2Pden;
/* Specifies the value for EMC_RW2PDEN */
uint32_t EmcRw2Pden;
/* Specifies the value for EMC_CKE2PDEN */
uint32_t EmcCke2Pden;
/* Specifies the value for EMC_PDEX2CKE */
uint32_t EmcPdex2Cke;
/* Specifies the value for EMC_PDEX2MRR */
uint32_t EmcPdex2Mrr;
/* Specifies the value for EMC_TXSR */
uint32_t EmcTxsr;
/* Specifies the value for EMC_TXSRDLL */
uint32_t EmcTxsrDll;
/* Specifies the value for EMC_TCKE */
uint32_t EmcTcke;
/* Specifies the value for EMC_TCKESR */
uint32_t EmcTckesr;
/* Specifies the value for EMC_TPD */
uint32_t EmcTpd;
/* Specifies the value for EMC_TFAW */
uint32_t EmcTfaw;
/* Specifies the value for EMC_TRPAB */
uint32_t EmcTrpab;
/* Specifies the value for EMC_TCLKSTABLE */
uint32_t EmcTClkStable;
/* Specifies the value for EMC_TCLKSTOP */
uint32_t EmcTClkStop;
/* Specifies the value for EMC_TREFBW */
uint32_t EmcTRefBw;
/* FBIO configuration values */
/* Specifies the value for EMC_FBIO_CFG5 */
uint32_t EmcFbioCfg5;
/* Specifies the value for EMC_FBIO_CFG7 */
uint32_t EmcFbioCfg7;
/* Specifies the value for EMC_FBIO_CFG8 */
uint32_t EmcFbioCfg8;
/* Command mapping for CMD brick 0 */
uint32_t EmcCmdMappingCmd0_0;
uint32_t EmcCmdMappingCmd0_1;
uint32_t EmcCmdMappingCmd0_2;
uint32_t EmcCmdMappingCmd1_0;
uint32_t EmcCmdMappingCmd1_1;
uint32_t EmcCmdMappingCmd1_2;
uint32_t EmcCmdMappingCmd2_0;
uint32_t EmcCmdMappingCmd2_1;
uint32_t EmcCmdMappingCmd2_2;
uint32_t EmcCmdMappingCmd3_0;
uint32_t EmcCmdMappingCmd3_1;
uint32_t EmcCmdMappingCmd3_2;
uint32_t EmcCmdMappingByte;
/* Specifies the value for EMC_FBIO_SPARE */
uint32_t EmcFbioSpare;
/* Specifies the value for EMC_CFG_RSV */
uint32_t EmcCfgRsv;
/* MRS command values */
/* Specifies the value for EMC_MRS */
uint32_t EmcMrs;
/* Specifies the MP0 command to initialize mode registers */
uint32_t EmcEmrs;
/* Specifies the MP2 command to initialize mode registers */
uint32_t EmcEmrs2;
/* Specifies the MP3 command to initialize mode registers */
uint32_t EmcEmrs3;
/* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */
uint32_t EmcMrw1;
/* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */
uint32_t EmcMrw2;
/* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */
uint32_t EmcMrw3;
/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
uint32_t EmcMrw4;
/* Specifies the programming to LPDDR2 Mode Register 3? at cold boot */
uint32_t EmcMrw6;
/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
uint32_t EmcMrw8;
/* Specifies the programming to LPDDR2 Mode Register 11? at cold boot */
uint32_t EmcMrw9;
/* Specifies the programming to LPDDR2 Mode Register 12 at cold boot */
uint32_t EmcMrw10;
/* Specifies the programming to LPDDR2 Mode Register 14 at cold boot */
uint32_t EmcMrw12;
/* Specifies the programming to LPDDR2 Mode Register 14? at cold boot */
uint32_t EmcMrw13;
/* Specifies the programming to LPDDR2 Mode Register 22 at cold boot */
uint32_t EmcMrw14;
/*
* Specifies the programming to extra LPDDR2 Mode Register
* at cold boot
*/
uint32_t EmcMrwExtra;
/*
* Specifies the programming to extra LPDDR2 Mode Register
* at warm boot
*/
uint32_t EmcWarmBootMrwExtra;
/*
* Specify the enable of extra Mode Register programming at
* warm boot
*/
uint32_t EmcWarmBootExtraModeRegWriteEnable;
/*
* Specify the enable of extra Mode Register programming at
* cold boot
*/
uint32_t EmcExtraModeRegWriteEnable;
/* Specifies the EMC_MRW reset command value */
uint32_t EmcMrwResetCommand;
/* Specifies the EMC Reset wait time (in microseconds) */
uint32_t EmcMrwResetNInitWait;
/* Specifies the value for EMC_MRS_WAIT_CNT */
uint32_t EmcMrsWaitCnt;
/* Specifies the value for EMC_MRS_WAIT_CNT2 */
uint32_t EmcMrsWaitCnt2;
/* EMC miscellaneous configurations */
/* Specifies the value for EMC_CFG */
uint32_t EmcCfg;
/* Specifies the value for EMC_CFG_2 */
uint32_t EmcCfg2;
/* Specifies the pipe bypass controls */
uint32_t EmcCfgPipe;
uint32_t EmcCfgPipeClk;
uint32_t EmcFdpdCtrlCmdNoRamp;
uint32_t EmcCfgUpdate;
/* Specifies the value for EMC_DBG */
uint32_t EmcDbg;
uint32_t EmcDbgWriteMux;
/* Specifies the value for EMC_CMDQ */
uint32_t EmcCmdQ;
/* Specifies the value for EMC_MC2EMCQ */
uint32_t EmcMc2EmcQ;
/* Specifies the value for EMC_DYN_SELF_REF_CONTROL */
uint32_t EmcDynSelfRefControl;
/* Specifies the value for MEM_INIT_DONE */
uint32_t AhbArbitrationXbarCtrlMemInitDone;
/* Specifies the value for EMC_CFG_DIG_DLL */
uint32_t EmcCfgDigDll;
uint32_t EmcCfgDigDll_1;
/* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */
uint32_t EmcCfgDigDllPeriod;
/* Specifies the value of *DEV_SELECTN of various EMC registers */
uint32_t EmcDevSelect;
/* Specifies the value for EMC_SEL_DPD_CTRL */
uint32_t EmcSelDpdCtrl;
/* Pads trimmer delays */
uint32_t EmcFdpdCtrlDq;
uint32_t EmcFdpdCtrlCmd;
uint32_t EmcPmacroIbVrefDq_0;
uint32_t EmcPmacroIbVrefDq_1;
uint32_t EmcPmacroIbVrefDqs_0;
uint32_t EmcPmacroIbVrefDqs_1;
uint32_t EmcPmacroIbRxrt;
uint32_t EmcCfgPipe1;
uint32_t EmcCfgPipe2;
/* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */
uint32_t EmcPmacroQuseDdllRank0_0;
uint32_t EmcPmacroQuseDdllRank0_1;
uint32_t EmcPmacroQuseDdllRank0_2;
uint32_t EmcPmacroQuseDdllRank0_3;
uint32_t EmcPmacroQuseDdllRank0_4;
uint32_t EmcPmacroQuseDdllRank0_5;
uint32_t EmcPmacroQuseDdllRank1_0;
uint32_t EmcPmacroQuseDdllRank1_1;
uint32_t EmcPmacroQuseDdllRank1_2;
uint32_t EmcPmacroQuseDdllRank1_3;
uint32_t EmcPmacroQuseDdllRank1_4;
uint32_t EmcPmacroQuseDdllRank1_5;
uint32_t EmcPmacroObDdllLongDqRank0_0;
uint32_t EmcPmacroObDdllLongDqRank0_1;
uint32_t EmcPmacroObDdllLongDqRank0_2;
uint32_t EmcPmacroObDdllLongDqRank0_3;
uint32_t EmcPmacroObDdllLongDqRank0_4;
uint32_t EmcPmacroObDdllLongDqRank0_5;
uint32_t EmcPmacroObDdllLongDqRank1_0;
uint32_t EmcPmacroObDdllLongDqRank1_1;
uint32_t EmcPmacroObDdllLongDqRank1_2;
uint32_t EmcPmacroObDdllLongDqRank1_3;
uint32_t EmcPmacroObDdllLongDqRank1_4;
uint32_t EmcPmacroObDdllLongDqRank1_5;
uint32_t EmcPmacroObDdllLongDqsRank0_0;
uint32_t EmcPmacroObDdllLongDqsRank0_1;
uint32_t EmcPmacroObDdllLongDqsRank0_2;
uint32_t EmcPmacroObDdllLongDqsRank0_3;
uint32_t EmcPmacroObDdllLongDqsRank0_4;
uint32_t EmcPmacroObDdllLongDqsRank0_5;
uint32_t EmcPmacroObDdllLongDqsRank1_0;
uint32_t EmcPmacroObDdllLongDqsRank1_1;
uint32_t EmcPmacroObDdllLongDqsRank1_2;
uint32_t EmcPmacroObDdllLongDqsRank1_3;
uint32_t EmcPmacroObDdllLongDqsRank1_4;
uint32_t EmcPmacroObDdllLongDqsRank1_5;
uint32_t EmcPmacroIbDdllLongDqsRank0_0;
uint32_t EmcPmacroIbDdllLongDqsRank0_1;
uint32_t EmcPmacroIbDdllLongDqsRank0_2;
uint32_t EmcPmacroIbDdllLongDqsRank0_3;
uint32_t EmcPmacroIbDdllLongDqsRank1_0;
uint32_t EmcPmacroIbDdllLongDqsRank1_1;
uint32_t EmcPmacroIbDdllLongDqsRank1_2;
uint32_t EmcPmacroIbDdllLongDqsRank1_3;
uint32_t EmcPmacroDdllLongCmd_0;
uint32_t EmcPmacroDdllLongCmd_1;
uint32_t EmcPmacroDdllLongCmd_2;
uint32_t EmcPmacroDdllLongCmd_3;
uint32_t EmcPmacroDdllLongCmd_4;
uint32_t EmcPmacroDdllShortCmd_0;
uint32_t EmcPmacroDdllShortCmd_1;
uint32_t EmcPmacroDdllShortCmd_2;
/*
* Specifies the delay after asserting CKE pin during a WarmBoot0
* sequence (in microseconds)
*/
uint32_t WarmBootWait;
/* Specifies the value for EMC_ODT_WRITE */
uint32_t EmcOdtWrite;
/* Periodic ZQ calibration */
/*
* Specifies the value for EMC_ZCAL_INTERVAL
* Value 0 disables ZQ calibration
*/
uint32_t EmcZcalInterval;
/* Specifies the value for EMC_ZCAL_WAIT_CNT */
uint32_t EmcZcalWaitCnt;
/* Specifies the value for EMC_ZCAL_MRW_CMD */
uint32_t EmcZcalMrwCmd;
/* DRAM initialization sequence flow control */
/* Specifies the MRS command value for resetting DLL */
uint32_t EmcMrsResetDll;
/* Specifies the command for ZQ initialization of device 0 */
uint32_t EmcZcalInitDev0;
/* Specifies the command for ZQ initialization of device 1 */
uint32_t EmcZcalInitDev1;
/*
* Specifies the wait time after programming a ZQ initialization
* command (in microseconds)
*/
uint32_t EmcZcalInitWait;
/*
* Specifies the enable for ZQ calibration at cold boot [bit 0]
* and warm boot [bit 1]
*/
uint32_t EmcZcalWarmColdBootEnables;
/*
* Specifies the MRW command to LPDDR2 for ZQ calibration
* on warmboot
*/
/* Is issued to both devices separately */
uint32_t EmcMrwLpddr2ZcalWarmBoot;
/*
* Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
* Is issued to both devices separately
*/
uint32_t EmcZqCalDdr3WarmBoot;
uint32_t EmcZqCalLpDdr4WarmBoot;
/*
* Specifies the wait time for ZQ calibration on warmboot
* (in microseconds)
*/
uint32_t EmcZcalWarmBootWait;
/*
* Specifies the enable for DRAM Mode Register programming
* at warm boot
*/
uint32_t EmcMrsWarmBootEnable;
/*
* Specifies the wait time after sending an MRS DLL reset command
* in microseconds)
*/
uint32_t EmcMrsResetDllWait;
/* Specifies the extra MRS command to initialize mode registers */
uint32_t EmcMrsExtra;
/* Specifies the extra MRS command at warm boot */
uint32_t EmcWarmBootMrsExtra;
/* Specifies the EMRS command to enable the DDR2 DLL */
uint32_t EmcEmrsDdr2DllEnable;
/* Specifies the MRS command to reset the DDR2 DLL */
uint32_t EmcMrsDdr2DllReset;
/* Specifies the EMRS command to set OCD calibration */
uint32_t EmcEmrsDdr2OcdCalib;
/*
* Specifies the wait between initializing DDR and setting OCD
* calibration (in microseconds)
*/
uint32_t EmcDdr2Wait;
/* Specifies the value for EMC_CLKEN_OVERRIDE */
uint32_t EmcClkenOverride;
/*
* Specifies LOG2 of the extra refresh numbers after booting
* Program 0 to disable
*/
uint32_t EmcExtraRefreshNum;
/* Specifies the master override for all EMC clocks */
uint32_t EmcClkenOverrideAllWarmBoot;
/* Specifies the master override for all MC clocks */
uint32_t McClkenOverrideAllWarmBoot;
/* Specifies digital dll period, choosing between 4 to 64 ms */
uint32_t EmcCfgDigDllPeriodWarmBoot;
/* Pad controls */
/* Specifies the value for PMC_VDDP_SEL */
uint32_t PmcVddpSel;
/* Specifies the wait time after programming PMC_VDDP_SEL */
uint32_t PmcVddpSelWait;
/* Specifies the value for PMC_DDR_PWR */
uint32_t PmcDdrPwr;
/* Specifies the value for PMC_DDR_CFG */
uint32_t PmcDdrCfg;
/* Specifies the value for PMC_IO_DPD3_REQ */
uint32_t PmcIoDpd3Req;
/* Specifies the wait time after programming PMC_IO_DPD3_REQ */
uint32_t PmcIoDpd3ReqWait;
uint32_t PmcIoDpd4ReqWait;
/* Specifies the value for PMC_REG_SHORT */
uint32_t PmcRegShort;
/* Specifies the value for PMC_NO_IOPOWER */
uint32_t PmcNoIoPower;
uint32_t PmcDdrCntrlWait;
uint32_t PmcDdrCntrl;
/* Specifies the value for EMC_ACPD_CONTROL */
uint32_t EmcAcpdControl;
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */
////uint32_t EmcSwizzleRank0ByteCfg;
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */
uint32_t EmcSwizzleRank0Byte0;
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */
uint32_t EmcSwizzleRank0Byte1;
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */
uint32_t EmcSwizzleRank0Byte2;
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */
uint32_t EmcSwizzleRank0Byte3;
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */
////uint32_t EmcSwizzleRank1ByteCfg;
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */
uint32_t EmcSwizzleRank1Byte0;
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */
uint32_t EmcSwizzleRank1Byte1;
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */
uint32_t EmcSwizzleRank1Byte2;
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */
uint32_t EmcSwizzleRank1Byte3;
/* Specifies the value for EMC_TXDSRVTTGEN */
uint32_t EmcTxdsrvttgen;
/* Specifies the value for EMC_DATA_BRLSHFT_0 */
uint32_t EmcDataBrlshft0;
uint32_t EmcDataBrlshft1;
uint32_t EmcDqsBrlshft0;
uint32_t EmcDqsBrlshft1;
uint32_t EmcCmdBrlshft0;
uint32_t EmcCmdBrlshft1;
uint32_t EmcCmdBrlshft2;
uint32_t EmcCmdBrlshft3;
uint32_t EmcQuseBrlshft0;
uint32_t EmcQuseBrlshft1;
uint32_t EmcQuseBrlshft2;
uint32_t EmcQuseBrlshft3;
uint32_t EmcDllCfg0;
uint32_t EmcDllCfg1;
uint32_t EmcPmcScratch1;
uint32_t EmcPmcScratch2;
uint32_t EmcPmcScratch3;
uint32_t EmcPmacroPadCfgCtrl;
uint32_t EmcPmacroVttgenCtrl0;
uint32_t EmcPmacroVttgenCtrl1;
uint32_t EmcPmacroVttgenCtrl2;
uint32_t EmcPmacroBrickCtrlRfu1;
uint32_t EmcPmacroCmdBrickCtrlFdpd;
uint32_t EmcPmacroBrickCtrlRfu2;
uint32_t EmcPmacroDataBrickCtrlFdpd;
uint32_t EmcPmacroBgBiasCtrl0;
uint32_t EmcPmacroDataPadRxCtrl;
uint32_t EmcPmacroCmdPadRxCtrl;
uint32_t EmcPmacroDataRxTermMode;
uint32_t EmcPmacroCmdRxTermMode;
uint32_t EmcPmacroDataPadTxCtrl;
uint32_t EmcPmacroCommonPadTxCtrl;
uint32_t EmcPmacroCmdPadTxCtrl;
uint32_t EmcCfg3;
uint32_t EmcPmacroTxPwrd0;
uint32_t EmcPmacroTxPwrd1;
uint32_t EmcPmacroTxPwrd2;
uint32_t EmcPmacroTxPwrd3;
uint32_t EmcPmacroTxPwrd4;
uint32_t EmcPmacroTxPwrd5;
uint32_t EmcConfigSampleDelay;
uint32_t EmcPmacroBrickMapping0;
uint32_t EmcPmacroBrickMapping1;
uint32_t EmcPmacroBrickMapping2;
uint32_t EmcPmacroTxSelClkSrc0;
uint32_t EmcPmacroTxSelClkSrc1;
uint32_t EmcPmacroTxSelClkSrc2;
uint32_t EmcPmacroTxSelClkSrc3;
uint32_t EmcPmacroTxSelClkSrc4;
uint32_t EmcPmacroTxSelClkSrc5;
uint32_t EmcPmacroDdllBypass;
uint32_t EmcPmacroDdllPwrd0;
uint32_t EmcPmacroDdllPwrd1;
uint32_t EmcPmacroDdllPwrd2;
uint32_t EmcPmacroCmdCtrl0;
uint32_t EmcPmacroCmdCtrl1;
uint32_t EmcPmacroCmdCtrl2;
/* DRAM size information */
/* Specifies the value for MC_EMEM_ADR_CFG */
uint32_t McEmemAdrCfg;
/* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */
uint32_t McEmemAdrCfgDev0;
/* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */
uint32_t McEmemAdrCfgDev1;
uint32_t McEmemAdrCfgChannelMask;
/* Specifies the value for MC_EMEM_BANK_SWIZZLECfg0 */
uint32_t McEmemAdrCfgBankMask0;
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */
uint32_t McEmemAdrCfgBankMask1;
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */
uint32_t McEmemAdrCfgBankMask2;
/*
* Specifies the value for MC_EMEM_CFG which holds the external memory
* size (in KBytes)
*/
uint32_t McEmemCfg;
/* MC arbitration configuration */
/* Specifies the value for MC_EMEM_ARB_CFG */
uint32_t McEmemArbCfg;
/* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */
uint32_t McEmemArbOutstandingReq;
uint32_t McEmemArbRefpbHpCtrl;
uint32_t McEmemArbRefpbBankCtrl;
/* Specifies the value for MC_EMEM_ARB_TIMING_RCD */
uint32_t McEmemArbTimingRcd;
/* Specifies the value for MC_EMEM_ARB_TIMING_RP */
uint32_t McEmemArbTimingRp;
/* Specifies the value for MC_EMEM_ARB_TIMING_RC */
uint32_t McEmemArbTimingRc;
/* Specifies the value for MC_EMEM_ARB_TIMING_RAS */
uint32_t McEmemArbTimingRas;
/* Specifies the value for MC_EMEM_ARB_TIMING_FAW */
uint32_t McEmemArbTimingFaw;
/* Specifies the value for MC_EMEM_ARB_TIMING_RRD */
uint32_t McEmemArbTimingRrd;
/* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */
uint32_t McEmemArbTimingRap2Pre;
/* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */
uint32_t McEmemArbTimingWap2Pre;
/* Specifies the value for MC_EMEM_ARB_TIMING_R2R */
uint32_t McEmemArbTimingR2R;
/* Specifies the value for MC_EMEM_ARB_TIMING_W2W */
uint32_t McEmemArbTimingW2W;
/* Specifies the value for MC_EMEM_ARB_TIMING_R2W */
uint32_t McEmemArbTimingR2W;
/* Specifies the value for MC_EMEM_ARB_TIMING_W2R */
uint32_t McEmemArbTimingW2R;
uint32_t McEmemArbTimingRFCPB;
/* Specifies the value for MC_EMEM_ARB_DA_TURNS */
uint32_t McEmemArbDaTurns;
/* Specifies the value for MC_EMEM_ARB_DA_COVERS */
uint32_t McEmemArbDaCovers;
/* Specifies the value for MC_EMEM_ARB_MISC0 */
uint32_t McEmemArbMisc0;
/* Specifies the value for MC_EMEM_ARB_MISC1 */
uint32_t McEmemArbMisc1;
uint32_t McEmemArbMisc2;
/* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */
uint32_t McEmemArbRing1Throttle;
/* Specifies the value for MC_EMEM_ARB_OVERRIDE */
uint32_t McEmemArbOverride;
/* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */
uint32_t McEmemArbOverride1;
/* Specifies the value for MC_EMEM_ARB_RSV */
uint32_t McEmemArbRsv;
uint32_t McDaCfg0;
uint32_t McEmemArbTimingCcdmw;
/* Specifies the value for MC_CLKEN_OVERRIDE */
uint32_t McClkenOverride;
/* Specifies the value for MC_STAT_CONTROL */
uint32_t McStatControl;
/* Specifies the value for MC_VIDEO_PROTECT_BOM */
uint32_t McVideoProtectBom;
/* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */
uint32_t McVideoProtectBomAdrHi;
/* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */
uint32_t McVideoProtectSizeMb;
/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */
uint32_t McVideoProtectVprOverride;
/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */
uint32_t McVideoProtectVprOverride1;
/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */
uint32_t McVideoProtectGpuOverride0;
/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */
uint32_t McVideoProtectGpuOverride1;
/* Specifies the value for MC_SEC_CARVEOUT_BOM */
uint32_t McSecCarveoutBom;
/* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */
uint32_t McSecCarveoutAdrHi;
/* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */
uint32_t McSecCarveoutSizeMb;
/* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.
VIDEO_PROTECT_WRITEAccess */
uint32_t McVideoProtectWriteAccess;
/* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.
SEC_CARVEOUT_WRITEAccess */
uint32_t McSecCarveoutProtectWriteAccess;
/* Write-Protect Regions (WPR) */
uint32_t McGeneralizedCarveout1Bom;
uint32_t McGeneralizedCarveout1BomHi;
uint32_t McGeneralizedCarveout1Size128kb;
uint32_t McGeneralizedCarveout1Access0;
uint32_t McGeneralizedCarveout1Access1;
uint32_t McGeneralizedCarveout1Access2;
uint32_t McGeneralizedCarveout1Access3;
uint32_t McGeneralizedCarveout1Access4;
uint32_t McGeneralizedCarveout1ForceInternalAccess0;
uint32_t McGeneralizedCarveout1ForceInternalAccess1;
uint32_t McGeneralizedCarveout1ForceInternalAccess2;
uint32_t McGeneralizedCarveout1ForceInternalAccess3;
uint32_t McGeneralizedCarveout1ForceInternalAccess4;
uint32_t McGeneralizedCarveout1Cfg0;
uint32_t McGeneralizedCarveout2Bom;
uint32_t McGeneralizedCarveout2BomHi;
uint32_t McGeneralizedCarveout2Size128kb;
uint32_t McGeneralizedCarveout2Access0;
uint32_t McGeneralizedCarveout2Access1;
uint32_t McGeneralizedCarveout2Access2;
uint32_t McGeneralizedCarveout2Access3;
uint32_t McGeneralizedCarveout2Access4;
uint32_t McGeneralizedCarveout2ForceInternalAccess0;
uint32_t McGeneralizedCarveout2ForceInternalAccess1;
uint32_t McGeneralizedCarveout2ForceInternalAccess2;
uint32_t McGeneralizedCarveout2ForceInternalAccess3;
uint32_t McGeneralizedCarveout2ForceInternalAccess4;
uint32_t McGeneralizedCarveout2Cfg0;
uint32_t McGeneralizedCarveout3Bom;
uint32_t McGeneralizedCarveout3BomHi;
uint32_t McGeneralizedCarveout3Size128kb;
uint32_t McGeneralizedCarveout3Access0;
uint32_t McGeneralizedCarveout3Access1;
uint32_t McGeneralizedCarveout3Access2;
uint32_t McGeneralizedCarveout3Access3;
uint32_t McGeneralizedCarveout3Access4;
uint32_t McGeneralizedCarveout3ForceInternalAccess0;
uint32_t McGeneralizedCarveout3ForceInternalAccess1;
uint32_t McGeneralizedCarveout3ForceInternalAccess2;
uint32_t McGeneralizedCarveout3ForceInternalAccess3;
uint32_t McGeneralizedCarveout3ForceInternalAccess4;
uint32_t McGeneralizedCarveout3Cfg0;
uint32_t McGeneralizedCarveout4Bom;
uint32_t McGeneralizedCarveout4BomHi;
uint32_t McGeneralizedCarveout4Size128kb;
uint32_t McGeneralizedCarveout4Access0;
uint32_t McGeneralizedCarveout4Access1;
uint32_t McGeneralizedCarveout4Access2;
uint32_t McGeneralizedCarveout4Access3;
uint32_t McGeneralizedCarveout4Access4;
uint32_t McGeneralizedCarveout4ForceInternalAccess0;
uint32_t McGeneralizedCarveout4ForceInternalAccess1;
uint32_t McGeneralizedCarveout4ForceInternalAccess2;
uint32_t McGeneralizedCarveout4ForceInternalAccess3;
uint32_t McGeneralizedCarveout4ForceInternalAccess4;
uint32_t McGeneralizedCarveout4Cfg0;
uint32_t McGeneralizedCarveout5Bom;
uint32_t McGeneralizedCarveout5BomHi;
uint32_t McGeneralizedCarveout5Size128kb;
uint32_t McGeneralizedCarveout5Access0;
uint32_t McGeneralizedCarveout5Access1;
uint32_t McGeneralizedCarveout5Access2;
uint32_t McGeneralizedCarveout5Access3;
uint32_t McGeneralizedCarveout5Access4;
uint32_t McGeneralizedCarveout5ForceInternalAccess0;
uint32_t McGeneralizedCarveout5ForceInternalAccess1;
uint32_t McGeneralizedCarveout5ForceInternalAccess2;
uint32_t McGeneralizedCarveout5ForceInternalAccess3;
uint32_t McGeneralizedCarveout5ForceInternalAccess4;
uint32_t McGeneralizedCarveout5Cfg0;
/* Specifies enable for CA training */
uint32_t EmcCaTrainingEnable;
/* Set if bit 6 select is greater than bit 7 select; uses aremc.
spec packet SWIZZLE_BIT6_GT_BIT7 */
uint32_t SwizzleRankByteEncode;
/* Specifies enable and offset for patched boot ROM write */
uint32_t BootRomPatchControl;
/* Specifies data for patched boot ROM write */
uint32_t BootRomPatchData;
/* Specifies the value for MC_MTS_CARVEOUT_BOM */
uint32_t McMtsCarveoutBom;
/* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */
uint32_t McMtsCarveoutAdrHi;
/* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */
uint32_t McMtsCarveoutSizeMb;
/* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */
uint32_t McMtsCarveoutRegCtrl;
/* End */
};
#endif /* __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ */

1041
sept/sept-secondary/src/sdram_params.h Normal file
View file

File diff suppressed because it is too large Load diff