diff --git a/fusee/fusee-mtc/src/emc.h b/fusee/fusee-mtc/src/emc.h index 17161b407..274d8213f 100644 --- a/fusee/fusee-mtc/src/emc.h +++ b/fusee/fusee-mtc/src/emc.h @@ -1086,4 +1086,44 @@ #define EMC_PMC_SCRATCH2 0x444 #define EMC_PMC_SCRATCH3 0x448 +#define EMC_PMACRO_PERBIT_FGCG_CTRL_0 0xd40 +#define EMC_PMACRO_PERBIT_FGCG_CTRL_1 0xd44 +#define EMC_PMACRO_PERBIT_FGCG_CTRL_2 0xd48 +#define EMC_PMACRO_PERBIT_FGCG_CTRL_3 0xd4c +#define EMC_PMACRO_PERBIT_FGCG_CTRL_4 0xd50 +#define EMC_PMACRO_PERBIT_FGCG_CTRL_5 0xd54 +#define EMC_PMACRO_PERBIT_RFU_CTRL_0 0xd60 +#define EMC_PMACRO_PERBIT_RFU_CTRL_1 0xd64 +#define EMC_PMACRO_PERBIT_RFU_CTRL_2 0xd68 +#define EMC_PMACRO_PERBIT_RFU_CTRL_3 0xd6c +#define EMC_PMACRO_PERBIT_RFU_CTRL_4 0xd70 +#define EMC_PMACRO_PERBIT_RFU_CTRL_5 0xd74 +#define EMC_PMACRO_PERBIT_RFU1_CTRL_0 0xd80 +#define EMC_PMACRO_PERBIT_RFU1_CTRL_1 0xd84 +#define EMC_PMACRO_PERBIT_RFU1_CTRL_2 0xd88 +#define EMC_PMACRO_PERBIT_RFU1_CTRL_3 0xd8c +#define EMC_PMACRO_PERBIT_RFU1_CTRL_4 0xd90 +#define EMC_PMACRO_PERBIT_RFU1_CTRL_5 0xd94 + +#define EMC_PMACRO_PMU_OUT_EOFF1_0 0xda0 +#define EMC_PMACRO_PMU_OUT_EOFF1_1 0xda4 +#define EMC_PMACRO_PMU_OUT_EOFF1_2 0xda8 +#define EMC_PMACRO_PMU_OUT_EOFF1_3 0xdac +#define EMC_PMACRO_PMU_OUT_EOFF1_4 0xdb0 +#define EMC_PMACRO_PMU_OUT_EOFF1_5 0xdb4 + +#define EMC_PMACRO_COMP_PMU_OUT 0xdc0 +#define EMC_PMACRO_DATA_PI_CTRL 0x110 +#define EMC_PMACRO_CMD_PI_CTRL 0x114 + +#define EMC_AUTO_CAL_CONFIG9 0x42c + +#define EMC_TRTM 0xbc +#define EMC_TWTM 0xf8 +#define EMC_TRATM 0xfc +#define EMC_TWATM 0x108 +#define EMC_TR2REF 0x10c + +#define EMC_PMACRO_DSR_VTTGEN_CTRL_0 0xc6c + #endif diff --git a/fusee/fusee-mtc/src/fuse.c b/fusee/fusee-mtc/src/fuse.c index e53cda3b3..14f12e69b 100644 --- a/fusee/fusee-mtc/src/fuse.c +++ b/fusee/fusee-mtc/src/fuse.c @@ -187,7 +187,7 @@ uint32_t fuse_get_reserved_odm(uint32_t index) { /* Get the DramId. */ uint32_t fuse_get_dram_id(void) { - return ((fuse_get_reserved_odm(4) >> 3) & 0x7); + return ((fuse_get_reserved_odm(4) >> 3) & 0x1F); } /* Derive the DeviceId. */ diff --git a/fusee/fusee-mtc/src/mc.h b/fusee/fusee-mtc/src/mc.h index 63a263a59..c414f907a 100644 --- a/fusee/fusee-mtc/src/mc.h +++ b/fusee/fusee-mtc/src/mc.h @@ -497,6 +497,7 @@ #define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08 #define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0 #define MC_DA_CONFIG0 0x9dc +#define MC_UNTRANSLATED_REGION_CHECK 0x948 /* Memory Controller clients */ #define CLIENT_ACCESS_NUM_CLIENTS 32 diff --git a/fusee/fusee-primary/src/emc.h b/fusee/fusee-primary/src/emc.h index 17161b407..274d8213f 100644 --- a/fusee/fusee-primary/src/emc.h +++ b/fusee/fusee-primary/src/emc.h @@ -1086,4 +1086,44 @@ #define EMC_PMC_SCRATCH2 0x444 #define EMC_PMC_SCRATCH3 0x448 +#define EMC_PMACRO_PERBIT_FGCG_CTRL_0 0xd40 +#define EMC_PMACRO_PERBIT_FGCG_CTRL_1 0xd44 +#define EMC_PMACRO_PERBIT_FGCG_CTRL_2 0xd48 +#define EMC_PMACRO_PERBIT_FGCG_CTRL_3 0xd4c +#define EMC_PMACRO_PERBIT_FGCG_CTRL_4 0xd50 +#define EMC_PMACRO_PERBIT_FGCG_CTRL_5 0xd54 +#define EMC_PMACRO_PERBIT_RFU_CTRL_0 0xd60 +#define EMC_PMACRO_PERBIT_RFU_CTRL_1 0xd64 +#define EMC_PMACRO_PERBIT_RFU_CTRL_2 0xd68 +#define EMC_PMACRO_PERBIT_RFU_CTRL_3 0xd6c +#define EMC_PMACRO_PERBIT_RFU_CTRL_4 0xd70 +#define EMC_PMACRO_PERBIT_RFU_CTRL_5 0xd74 +#define EMC_PMACRO_PERBIT_RFU1_CTRL_0 0xd80 +#define EMC_PMACRO_PERBIT_RFU1_CTRL_1 0xd84 +#define EMC_PMACRO_PERBIT_RFU1_CTRL_2 0xd88 +#define EMC_PMACRO_PERBIT_RFU1_CTRL_3 0xd8c +#define EMC_PMACRO_PERBIT_RFU1_CTRL_4 0xd90 +#define EMC_PMACRO_PERBIT_RFU1_CTRL_5 0xd94 + +#define EMC_PMACRO_PMU_OUT_EOFF1_0 0xda0 +#define EMC_PMACRO_PMU_OUT_EOFF1_1 0xda4 +#define EMC_PMACRO_PMU_OUT_EOFF1_2 0xda8 +#define EMC_PMACRO_PMU_OUT_EOFF1_3 0xdac +#define EMC_PMACRO_PMU_OUT_EOFF1_4 0xdb0 +#define EMC_PMACRO_PMU_OUT_EOFF1_5 0xdb4 + +#define EMC_PMACRO_COMP_PMU_OUT 0xdc0 +#define EMC_PMACRO_DATA_PI_CTRL 0x110 +#define EMC_PMACRO_CMD_PI_CTRL 0x114 + +#define EMC_AUTO_CAL_CONFIG9 0x42c + +#define EMC_TRTM 0xbc +#define EMC_TWTM 0xf8 +#define EMC_TRATM 0xfc +#define EMC_TWATM 0x108 +#define EMC_TR2REF 0x10c + +#define EMC_PMACRO_DSR_VTTGEN_CTRL_0 0xc6c + #endif diff --git a/fusee/fusee-primary/src/fuse.c b/fusee/fusee-primary/src/fuse.c index e53cda3b3..14f12e69b 100644 --- a/fusee/fusee-primary/src/fuse.c +++ b/fusee/fusee-primary/src/fuse.c @@ -187,7 +187,7 @@ uint32_t fuse_get_reserved_odm(uint32_t index) { /* Get the DramId. */ uint32_t fuse_get_dram_id(void) { - return ((fuse_get_reserved_odm(4) >> 3) & 0x7); + return ((fuse_get_reserved_odm(4) >> 3) & 0x1F); } /* Derive the DeviceId. */ diff --git a/fusee/fusee-primary/src/hwinit.c b/fusee/fusee-primary/src/hwinit.c index ea156cc02..dc343e70e 100644 --- a/fusee/fusee-primary/src/hwinit.c +++ b/fusee/fusee-primary/src/hwinit.c @@ -320,10 +320,10 @@ void nx_hwinit_erista(bool enable_log) { /* mc_config_carveout(); */ /* Initialize SDRAM. */ - sdram_init(); + sdram_init_erista(); - /* Save SDRAM LP0 parameters. */ - sdram_lp0_save_params(sdram_get_params()); + /* Save SDRAM parameters to scratch. */ + sdram_save_params_erista(sdram_get_params_erista(fuse_get_dram_id())); } void nx_hwinit_mariko(bool enable_log) { @@ -394,4 +394,10 @@ void nx_hwinit_mariko(bool enable_log) { MAKE_PMC_REG(0xBE8) &= 0xFFFFFFFE; MAKE_PMC_REG(0xBF0) = 0x3; MAKE_PMC_REG(0xBEC) = 0x3; + + /* Initialize SDRAM. */ + sdram_init_mariko(); + + /* Save SDRAM parameters to scratch. */ + sdram_save_params_mariko(sdram_get_params_mariko(fuse_get_dram_id())); } \ No newline at end of file diff --git a/fusee/fusee-primary/src/hwinit.h b/fusee/fusee-primary/src/hwinit.h index f14638eb0..7388813cd 100644 --- a/fusee/fusee-primary/src/hwinit.h +++ b/fusee/fusee-primary/src/hwinit.h @@ -24,7 +24,7 @@ #define I2S_BASE 0x702D1000 #define MAKE_I2S_REG(n) MAKE_REG32(I2S_BASE + n) -void nx_hwinit_mariko(bool enable_log); void nx_hwinit_erista(bool enable_log); +void nx_hwinit_mariko(bool enable_log); #endif diff --git a/fusee/fusee-primary/src/mc.h b/fusee/fusee-primary/src/mc.h index 63a263a59..c414f907a 100644 --- a/fusee/fusee-primary/src/mc.h +++ b/fusee/fusee-primary/src/mc.h @@ -497,6 +497,7 @@ #define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08 #define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0 #define MC_DA_CONFIG0 0x9dc +#define MC_UNTRANSLATED_REGION_CHECK 0x948 /* Memory Controller clients */ #define CLIENT_ACCESS_NUM_CLIENTS 32 diff --git a/fusee/fusee-primary/src/sdram.c b/fusee/fusee-primary/src/sdram.c index 55a2f6af8..6198c2ceb 100644 --- a/fusee/fusee-primary/src/sdram.c +++ b/fusee/fusee-primary/src/sdram.c @@ -23,50 +23,40 @@ #include "sysreg.h" #include "fuse.h" #include "max77620.h" -#include "sdram_param_t210.h" +#include "sdram_params.h" #include "car.h" -#define CONFIG_SDRAM_COMPRESS_CFG +#define CONFIG_SDRAM_COMPRESS -#ifdef CONFIG_SDRAM_COMPRESS_CFG +#ifdef CONFIG_SDRAM_COMPRESS #include "../../../fusee/common/lz.h" #include "sdram_lz.inl" #else #include "sdram.inl" #endif -static uint32_t _get_sdram_id() -{ - return ((fuse_get_reserved_odm(4) & 0x38) >> 3); -} - -static void _sdram_config(const sdram_params_t *params) -{ +static void sdram_config_erista(const sdram_params_erista_t *params) { volatile tegra_car_t *car = car_get_regs(); volatile tegra_pmc_t *pmc = pmc_get_regs(); - pmc->io_dpd3_req = (((4 * params->emc_pmc_scratch1 >> 2) + 0x80000000) ^ 0xFFFF) & 0xC000FFFF; - udelay(params->pmc_io_dpd3_req_wait); - - uint32_t req = (4 * params->emc_pmc_scratch2 >> 2) + 0x80000000; + pmc->io_dpd3_req = (((4 * params->EmcPmcScratch1 >> 2) + 0x80000000) ^ 0xFFFF) & 0xC000FFFF; + udelay(params->PmcIoDpd3ReqWait); + uint32_t req = (4 * params->EmcPmcScratch2 >> 2) + 0x80000000; pmc->io_dpd4_req = (req >> 16 << 16) ^ 0x3FFF0000; - - udelay(params->pmc_io_dpd4_req_wait); + udelay(params->PmcIoDpd4ReqWait); pmc->io_dpd4_req = (req ^ 0xFFFF) & 0xC000FFFF; - udelay(params->pmc_io_dpd4_req_wait); - + udelay(params->PmcIoDpd4ReqWait); pmc->weak_bias = 0; udelay(1); - car->pllm_misc1 = params->pllm_setup_control; + car->pllm_misc1 = params->PllMSetupControl; car->pllm_misc2 = 0; - car->pllm_base = ((params->pllm_feedback_divider << 8) | params->pllm_input_divider | 0x40000000 | ((params->pllm_post_divider & 0xFFFF) << 20)); + car->pllm_base = ((params->PllMFeedbackDivider << 8) | params->PllMInputDivider | 0x40000000 | ((params->PllMPostDivider & 0xFFFF) << 20)); bool timeout = false; uint32_t wait_end = get_time_us() + 300; - while (!(car->pllm_base & 0x8000000) && !timeout) - { + while (!(car->pllm_base & 0x8000000) && !timeout) { if (get_time_us() >= wait_end) timeout = true; } @@ -75,504 +65,2159 @@ static void _sdram_config(const sdram_params_t *params) udelay(10); } - car->clk_source_emc = (((params->mc_emem_arb_misc0 >> 11) & 0x10000) | (params->emc_clock_source & 0xFFFEFFFF)); + car->clk_source_emc = (((params->McEmemArbMisc0 >> 11) & 0x10000) | (params->EmcClockSource & 0xFFFEFFFF)); - if (params->emc_clock_source_dll) - car->clk_source_emc_dll = params->emc_clock_source_dll; - - if (params->clear_clock2_mc1) + if (params->EmcClockSourceDll) { + car->clk_source_emc_dll = params->EmcClockSourceDll; + } + if (params->ClearClk2Mc1) { car->clk_enb_w_clr = 0x40000000; + } car->clk_enb_h_set = 0x2000001; car->clk_enb_x_set = 0x4000; car->rst_dev_h_clr = 0x2000001; - MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_0) = params->emc_pmacro_vttgen_ctrl0; - MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_1) = params->emc_pmacro_vttgen_ctrl1; - MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_2) = params->emc_pmacro_vttgen_ctrl2; + MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_0) = params->EmcPmacroVttgenCtrl0; + MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_1) = params->EmcPmacroVttgenCtrl1; + MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_2) = params->EmcPmacroVttgenCtrl2; MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; udelay(1); - MAKE_EMC_REG(EMC_DBG) = (params->emc_dbg_write_mux << 1) | params->emc_dbg; + MAKE_EMC_REG(EMC_DBG) = (params->EmcDbgWriteMux << 1) | params->EmcDbg; - if (params->emc_bct_spare2) - *(volatile uint32_t *)params->emc_bct_spare2 = params->emc_bct_spare3; + if (params->EmcBctSpare2) { + *(volatile uint32_t *)params->EmcBctSpare2 = params->EmcBctSpare3; + } - MAKE_EMC_REG(EMC_FBIO_CFG7) = params->emc_fbio_cfg7; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_0) = params->emc_cmd_mapping_cmd0_0; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_1) = params->emc_cmd_mapping_cmd0_1; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_2) = params->emc_cmd_mapping_cmd0_2; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_0) = params->emc_cmd_mapping_cmd1_0; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_1) = params->emc_cmd_mapping_cmd1_1; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_2) = params->emc_cmd_mapping_cmd1_2; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_0) = params->emc_cmd_mapping_cmd2_0; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_1) = params->emc_cmd_mapping_cmd2_1; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_2) = params->emc_cmd_mapping_cmd2_2; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_0) = params->emc_cmd_mapping_cmd3_0; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_1) = params->emc_cmd_mapping_cmd3_1; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_2) = params->emc_cmd_mapping_cmd3_2; - MAKE_EMC_REG(EMC_CMD_MAPPING_BYTE) = params->emc_cmd_mapping_byte; - MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_0) = params->emc_pmacro_brick_mapping0; - MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_1) = params->emc_pmacro_brick_mapping1; - MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_2) = params->emc_pmacro_brick_mapping2; - MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = ((params->emc_pmacro_brick_ctrl_rfu1 & 0x1120112) | 0x1EED1EED); - MAKE_EMC_REG(EMC_CONFIG_SAMPLE_DELAY) = params->emc_config_sample_delay; - MAKE_EMC_REG(EMC_FBIO_CFG8) = params->emc_fbio_cfg8; - MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE0) = params->emc_swizzle_rank0_byte0; - MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE1) = params->emc_swizzle_rank0_byte1; - MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE2) = params->emc_swizzle_rank0_byte2; - MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE3) = params->emc_swizzle_rank0_byte3; - MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE0) = params->emc_swizzle_rank1_byte0; - MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE1) = params->emc_swizzle_rank1_byte1; - MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE2) = params->emc_swizzle_rank1_byte2; - MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE3) = params->emc_swizzle_rank1_byte3; + MAKE_EMC_REG(EMC_FBIO_CFG7) = params->EmcFbioCfg7; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_0) = params->EmcCmdMappingCmd0_0; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_1) = params->EmcCmdMappingCmd0_1; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_2) = params->EmcCmdMappingCmd0_2; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_0) = params->EmcCmdMappingCmd1_0; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_1) = params->EmcCmdMappingCmd1_1; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_2) = params->EmcCmdMappingCmd1_2; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_0) = params->EmcCmdMappingCmd2_0; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_1) = params->EmcCmdMappingCmd2_1; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_2) = params->EmcCmdMappingCmd2_2; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_0) = params->EmcCmdMappingCmd3_0; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_1) = params->EmcCmdMappingCmd3_1; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_2) = params->EmcCmdMappingCmd3_2; + MAKE_EMC_REG(EMC_CMD_MAPPING_BYTE) = params->EmcCmdMappingByte; + MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_0) = params->EmcPmacroBrickMapping0; + MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_1) = params->EmcPmacroBrickMapping1; + MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_2) = params->EmcPmacroBrickMapping2; + MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = ((params->EmcPmacroBrickCtrlRfu1 & 0x1120112) | 0x1EED1EED); + MAKE_EMC_REG(EMC_CONFIG_SAMPLE_DELAY) = params->EmcConfigSampleDelay; + MAKE_EMC_REG(EMC_FBIO_CFG8) = params->EmcFbioCfg8; + MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE0) = params->EmcSwizzleRank0Byte0; + MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE1) = params->EmcSwizzleRank0Byte1; + MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE2) = params->EmcSwizzleRank0Byte2; + MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE3) = params->EmcSwizzleRank0Byte3; + MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE0) = params->EmcSwizzleRank1Byte0; + MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE1) = params->EmcSwizzleRank1Byte1; + MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE2) = params->EmcSwizzleRank1Byte2; + MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE3) = params->EmcSwizzleRank1Byte3; - if (params->emc_bct_spare6) - *(volatile uint32_t *)params->emc_bct_spare6 = params->emc_bct_spare7; + if (params->EmcBctSpare6) { + *(volatile uint32_t *)params->EmcBctSpare6 = params->EmcBctSpare7; + } - MAKE_EMC_REG(EMC_XM2COMPPADCTRL) = params->emc_xm2_comp_pad_ctrl; - MAKE_EMC_REG(EMC_XM2COMPPADCTRL2) = params->emc_xm2_comp_pad_ctrl2; - MAKE_EMC_REG(EMC_XM2COMPPADCTRL3) = params->emc_xm2_comp_pad_ctrl3; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG2) = params->emc_auto_cal_config2; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG3) = params->emc_auto_cal_config3; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG4) = params->emc_auto_cal_config4; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG5) = params->emc_auto_cal_config5; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG6) = params->emc_auto_cal_config6; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG7) = params->emc_auto_cal_config7; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG8) = params->emc_auto_cal_config8; - MAKE_EMC_REG(EMC_PMACRO_RX_TERM) = params->emc_pmacro_rx_term; - MAKE_EMC_REG(EMC_PMACRO_DQ_TX_DRV) = params->emc_pmacro_dq_tx_drive; - MAKE_EMC_REG(EMC_PMACRO_CA_TX_DRV) = params->emc_pmacro_ca_tx_drive; - MAKE_EMC_REG(EMC_PMACRO_CMD_TX_DRV) = params->emc_pmacro_cmd_tx_drive; - MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_COMMON) = params->emc_pmacro_auto_cal_common; - MAKE_EMC_REG(EMC_AUTO_CAL_CHANNEL) = params->emc_auto_cal_channel; - MAKE_EMC_REG(EMC_PMACRO_ZCTRL) = params->emc_pmacro_zcrtl; - MAKE_EMC_REG(EMC_DLL_CFG_0) = params->emc_dll_cfg0; - MAKE_EMC_REG(EMC_DLL_CFG_1) = params->emc_dll_cfg1; - MAKE_EMC_REG(EMC_CFG_DIG_DLL_1) = params->emc_cfg_dig_dll_1; - MAKE_EMC_REG(EMC_DATA_BRLSHFT_0) = params->emc_data_brlshft0; - MAKE_EMC_REG(EMC_DATA_BRLSHFT_1) = params->emc_data_brlshft1; - MAKE_EMC_REG(EMC_DQS_BRLSHFT_0) = params->emc_dqs_brlshft0; - MAKE_EMC_REG(EMC_DQS_BRLSHFT_1) = params->emc_dqs_brlshft1; - MAKE_EMC_REG(EMC_CMD_BRLSHFT_0) = params->emc_cmd_brlshft0; - MAKE_EMC_REG(EMC_CMD_BRLSHFT_1) = params->emc_cmd_brlshft1; - MAKE_EMC_REG(EMC_CMD_BRLSHFT_2) = params->emc_cmd_brlshft2; - MAKE_EMC_REG(EMC_CMD_BRLSHFT_3) = params->emc_cmd_brlshft3; - MAKE_EMC_REG(EMC_QUSE_BRLSHFT_0) = params->emc_quse_brlshft0; - MAKE_EMC_REG(EMC_QUSE_BRLSHFT_1) = params->emc_quse_brlshft1; - MAKE_EMC_REG(EMC_QUSE_BRLSHFT_2) = params->emc_quse_brlshft2; - MAKE_EMC_REG(EMC_QUSE_BRLSHFT_3) = params->emc_quse_brlshft3; - MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = ((params->emc_pmacro_brick_ctrl_rfu1 & 0x1BF01BF) | 0x1E401E40); - MAKE_EMC_REG(EMC_PMACRO_PAD_CFG_CTRL) = params->emc_pmacro_pad_cfg_ctrl; - MAKE_EMC_REG(EMC_PMACRO_CMD_BRICK_CTRL_FDPD) = params->emc_pmacro_cmd_brick_ctrl_fdpd; - MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU2) = (params->emc_pmacro_brick_ctrl_rfu2 & 0xFF7FFF7F); - MAKE_EMC_REG(EMC_PMACRO_DATA_BRICK_CTRL_FDPD) = params->emc_pmacro_data_brick_ctrl_fdpd; - MAKE_EMC_REG(EMC_PMACRO_BG_BIAS_CTRL_0) = params->emc_pmacro_bg_bias_ctrl0; - MAKE_EMC_REG(EMC_PMACRO_DATA_PAD_RX_CTRL) = params->emc_pmacro_data_pad_rx_ctrl; - MAKE_EMC_REG(EMC_PMACRO_CMD_PAD_RX_CTRL) = params->emc_pmacro_cmd_pad_rx_ctrl; - MAKE_EMC_REG(EMC_PMACRO_DATA_PAD_TX_CTRL) = params->emc_pmacro_data_pad_tx_ctrl; - MAKE_EMC_REG(EMC_PMACRO_DATA_RX_TERM_MODE) = params->emc_pmacro_data_rx_term_mode; - MAKE_EMC_REG(EMC_PMACRO_CMD_RX_TERM_MODE) = params->emc_pmacro_cmd_rx_term_mode; - MAKE_EMC_REG(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->emc_pmacro_cmd_pad_tx_ctrl; - MAKE_EMC_REG(EMC_CFG_3) = params->emc_cfg3; - MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_0) = params->emc_pmacro_tx_pwrd0; - MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_1) = params->emc_pmacro_tx_pwrd1; - MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_2) = params->emc_pmacro_tx_pwrd2; - MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_3) = params->emc_pmacro_tx_pwrd3; - MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_4) = params->emc_pmacro_tx_pwrd4; - MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_5) = params->emc_pmacro_tx_pwrd5; - MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_0) = params->emc_pmacro_tx_sel_clk_src0; - MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_1) = params->emc_pmacro_tx_sel_clk_src1; - MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_2) = params->emc_pmacro_tx_sel_clk_src2; - MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_3) = params->emc_pmacro_tx_sel_clk_src3; - MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_4) = params->emc_pmacro_tx_sel_clk_src4; - MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_5) = params->emc_pmacro_tx_sel_clk_src5; - MAKE_EMC_REG(EMC_PMACRO_DDLL_BYPASS) = params->emc_pmacro_ddll_bypass; - MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_0) = params->emc_pmacro_ddll_pwrd0; - MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_1) = params->emc_pmacro_ddll_pwrd1; - MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_2) = params->emc_pmacro_ddll_pwrd2; - MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_0) = params->emc_pmacro_cmd_ctrl0; - MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_1) = params->emc_pmacro_cmd_ctrl1; - MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_2) = params->emc_pmacro_cmd_ctrl2; - MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQ_0) = params->emc_pmacro_ib_vref_dq_0; - MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQ_1) = params->emc_pmacro_ib_vref_dq_1; - MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQS_0) = params->emc_pmacro_ib_vref_dqs_0; - MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQS_1) = params->emc_pmacro_ib_vref_dqs_1; - MAKE_EMC_REG(EMC_PMACRO_IB_RXRT) = params->emc_pmacro_ib_rxrt; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_0) = params->emc_pmacro_quse_ddll_rank0_0; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_1) = params->emc_pmacro_quse_ddll_rank0_1; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_2) = params->emc_pmacro_quse_ddll_rank0_2; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_3) = params->emc_pmacro_quse_ddll_rank0_3; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_4) = params->emc_pmacro_quse_ddll_rank0_4; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_5) = params->emc_pmacro_quse_ddll_rank0_5; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_0) = params->emc_pmacro_quse_ddll_rank1_0; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_1) = params->emc_pmacro_quse_ddll_rank1_1; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_2) = params->emc_pmacro_quse_ddll_rank1_2; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_3) = params->emc_pmacro_quse_ddll_rank1_3; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_4) = params->emc_pmacro_quse_ddll_rank1_4; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_5) = params->emc_pmacro_quse_ddll_rank1_5; - MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = params->emc_pmacro_brick_ctrl_rfu1; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0) = params->emc_pmacro_ob_ddll_long_dq_rank0_0; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1) = params->emc_pmacro_ob_ddll_long_dq_rank0_1; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2) = params->emc_pmacro_ob_ddll_long_dq_rank0_2; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3) = params->emc_pmacro_ob_ddll_long_dq_rank0_3; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4) = params->emc_pmacro_ob_ddll_long_dq_rank0_4; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5) = params->emc_pmacro_ob_ddll_long_dq_rank0_5; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0) = params->emc_pmacro_ob_ddll_long_dq_rank1_0; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1) = params->emc_pmacro_ob_ddll_long_dq_rank1_1; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2) = params->emc_pmacro_ob_ddll_long_dq_rank1_2; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3) = params->emc_pmacro_ob_ddll_long_dq_rank1_3; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4) = params->emc_pmacro_ob_ddll_long_dq_rank1_4; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5) = params->emc_pmacro_ob_ddll_long_dq_rank1_5; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0) = params->emc_pmacro_ob_ddll_long_dqs_rank0_0; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1) = params->emc_pmacro_ob_ddll_long_dqs_rank0_1; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2) = params->emc_pmacro_ob_ddll_long_dqs_rank0_2; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3) = params->emc_pmacro_ob_ddll_long_dqs_rank0_3; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4) = params->emc_pmacro_ob_ddll_long_dqs_rank0_4; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5) = params->emc_pmacro_ob_ddll_long_dqs_rank0_5; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0) = params->emc_pmacro_ob_ddll_long_dqs_rank1_0; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1) = params->emc_pmacro_ob_ddll_long_dqs_rank1_1; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2) = params->emc_pmacro_ob_ddll_long_dqs_rank1_2; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3) = params->emc_pmacro_ob_ddll_long_dqs_rank1_3; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4) = params->emc_pmacro_ob_ddll_long_dqs_rank1_4; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5) = params->emc_pmacro_ob_ddll_long_dqs_rank1_5; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0) = params->emc_pmacro_ib_ddll_long_dqs_rank0_0; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1) = params->emc_pmacro_ib_ddll_long_dqs_rank0_1; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2) = params->emc_pmacro_ib_ddll_long_dqs_rank0_2; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3) = params->emc_pmacro_ib_ddll_long_dqs_rank0_3; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0) = params->emc_pmacro_ib_ddll_long_dqs_rank1_0; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1) = params->emc_pmacro_ib_ddll_long_dqs_rank1_1; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2) = params->emc_pmacro_ib_ddll_long_dqs_rank1_2; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3) = params->emc_pmacro_ib_ddll_long_dqs_rank1_3; - MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_0) = params->emc_pmacro_ddll_long_cmd_0; - MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_1) = params->emc_pmacro_ddll_long_cmd_1; - MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_2) = params->emc_pmacro_ddll_long_cmd_2; - MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_3) = params->emc_pmacro_ddll_long_cmd_3; - MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_4) = params->emc_pmacro_ddll_long_cmd_4; - MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_0) = params->emc_pmacro_ddll_short_cmd_0; - MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_1) = params->emc_pmacro_ddll_short_cmd_1; - MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_2) = params->emc_pmacro_ddll_short_cmd_2; - MAKE_EMC_REG(EMC_PMACRO_COMMON_PAD_TX_CTRL) = ((params->emc_pmacro_common_pad_tx_ctrl & 1) | 0xE); + MAKE_EMC_REG(EMC_XM2COMPPADCTRL) = params->EmcXm2CompPadCtrl; + MAKE_EMC_REG(EMC_XM2COMPPADCTRL2) = params->EmcXm2CompPadCtrl2; + MAKE_EMC_REG(EMC_XM2COMPPADCTRL3) = params->EmcXm2CompPadCtrl3; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG2) = params->EmcAutoCalConfig2; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG3) = params->EmcAutoCalConfig3; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG4) = params->EmcAutoCalConfig4; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG5) = params->EmcAutoCalConfig5; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG6) = params->EmcAutoCalConfig6; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG7) = params->EmcAutoCalConfig7; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG8) = params->EmcAutoCalConfig8; + MAKE_EMC_REG(EMC_PMACRO_RX_TERM) = params->EmcPmacroRxTerm; + MAKE_EMC_REG(EMC_PMACRO_DQ_TX_DRV) = params->EmcPmacroDqTxDrv; + MAKE_EMC_REG(EMC_PMACRO_CA_TX_DRV) = params->EmcPmacroCaTxDrv; + MAKE_EMC_REG(EMC_PMACRO_CMD_TX_DRV) = params->EmcPmacroCmdTxDrv; + MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_COMMON) = params->EmcPmacroAutocalCfgCommon; + MAKE_EMC_REG(EMC_AUTO_CAL_CHANNEL) = params->EmcAutoCalChannel; + MAKE_EMC_REG(EMC_PMACRO_ZCTRL) = params->EmcPmacroZctrl; + MAKE_EMC_REG(EMC_DLL_CFG_0) = params->EmcDllCfg0; + MAKE_EMC_REG(EMC_DLL_CFG_1) = params->EmcDllCfg1; + MAKE_EMC_REG(EMC_CFG_DIG_DLL_1) = params->EmcCfgDigDll_1; + MAKE_EMC_REG(EMC_DATA_BRLSHFT_0) = params->EmcDataBrlshft0; + MAKE_EMC_REG(EMC_DATA_BRLSHFT_1) = params->EmcDataBrlshft1; + MAKE_EMC_REG(EMC_DQS_BRLSHFT_0) = params->EmcDqsBrlshft0; + MAKE_EMC_REG(EMC_DQS_BRLSHFT_1) = params->EmcDqsBrlshft1; + MAKE_EMC_REG(EMC_CMD_BRLSHFT_0) = params->EmcCmdBrlshft0; + MAKE_EMC_REG(EMC_CMD_BRLSHFT_1) = params->EmcCmdBrlshft1; + MAKE_EMC_REG(EMC_CMD_BRLSHFT_2) = params->EmcCmdBrlshft2; + MAKE_EMC_REG(EMC_CMD_BRLSHFT_3) = params->EmcCmdBrlshft3; + MAKE_EMC_REG(EMC_QUSE_BRLSHFT_0) = params->EmcQuseBrlshft0; + MAKE_EMC_REG(EMC_QUSE_BRLSHFT_1) = params->EmcQuseBrlshft1; + MAKE_EMC_REG(EMC_QUSE_BRLSHFT_2) = params->EmcQuseBrlshft2; + MAKE_EMC_REG(EMC_QUSE_BRLSHFT_3) = params->EmcQuseBrlshft3; + MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = ((params->EmcPmacroBrickCtrlRfu1 & 0x1BF01BF) | 0x1E401E40); + MAKE_EMC_REG(EMC_PMACRO_PAD_CFG_CTRL) = params->EmcPmacroPadCfgCtrl; + MAKE_EMC_REG(EMC_PMACRO_CMD_BRICK_CTRL_FDPD) = params->EmcPmacroCmdBrickCtrlFdpd; + MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU2) = (params->EmcPmacroBrickCtrlRfu2 & 0xFF7FFF7F); + MAKE_EMC_REG(EMC_PMACRO_DATA_BRICK_CTRL_FDPD) = params->EmcPmacroDataBrickCtrlFdpd; + MAKE_EMC_REG(EMC_PMACRO_BG_BIAS_CTRL_0) = params->EmcPmacroBgBiasCtrl0; + MAKE_EMC_REG(EMC_PMACRO_DATA_PAD_RX_CTRL) = params->EmcPmacroDataPadRxCtrl; + MAKE_EMC_REG(EMC_PMACRO_CMD_PAD_RX_CTRL) = params->EmcPmacroCmdPadRxCtrl; + MAKE_EMC_REG(EMC_PMACRO_DATA_PAD_TX_CTRL) = params->EmcPmacroDataPadTxCtrl; + MAKE_EMC_REG(EMC_PMACRO_DATA_RX_TERM_MODE) = params->EmcPmacroDataRxTermMode; + MAKE_EMC_REG(EMC_PMACRO_CMD_RX_TERM_MODE) = params->EmcPmacroCmdRxTermMode; + MAKE_EMC_REG(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->EmcPmacroCmdPadTxCtrl; + MAKE_EMC_REG(EMC_CFG_3) = params->EmcCfg3; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_0) = params->EmcPmacroTxPwrd0; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_1) = params->EmcPmacroTxPwrd1; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_2) = params->EmcPmacroTxPwrd2; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_3) = params->EmcPmacroTxPwrd3; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_4) = params->EmcPmacroTxPwrd4; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_5) = params->EmcPmacroTxPwrd5; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_0) = params->EmcPmacroTxSelClkSrc0; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_1) = params->EmcPmacroTxSelClkSrc1; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_2) = params->EmcPmacroTxSelClkSrc2; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_3) = params->EmcPmacroTxSelClkSrc3; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_4) = params->EmcPmacroTxSelClkSrc4; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_5) = params->EmcPmacroTxSelClkSrc5; + MAKE_EMC_REG(EMC_PMACRO_DDLL_BYPASS) = params->EmcPmacroDdllBypass; + MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_0) = params->EmcPmacroDdllPwrd0; + MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_1) = params->EmcPmacroDdllPwrd1; + MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_2) = params->EmcPmacroDdllPwrd2; + MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_0) = params->EmcPmacroCmdCtrl0; + MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_1) = params->EmcPmacroCmdCtrl1; + MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_2) = params->EmcPmacroCmdCtrl2; + MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQ_0) = params->EmcPmacroIbVrefDq_0; + MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQ_1) = params->EmcPmacroIbVrefDq_1; + MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQS_0) = params->EmcPmacroIbVrefDqs_0; + MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQS_1) = params->EmcPmacroIbVrefDqs_1; + MAKE_EMC_REG(EMC_PMACRO_IB_RXRT) = params->EmcPmacroIbRxrt; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_0) = params->EmcPmacroQuseDdllRank0_0; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_1) = params->EmcPmacroQuseDdllRank0_1; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_2) = params->EmcPmacroQuseDdllRank0_2; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_3) = params->EmcPmacroQuseDdllRank0_3; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_4) = params->EmcPmacroQuseDdllRank0_4; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_5) = params->EmcPmacroQuseDdllRank0_5; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_0) = params->EmcPmacroQuseDdllRank1_0; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_1) = params->EmcPmacroQuseDdllRank1_1; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_2) = params->EmcPmacroQuseDdllRank1_2; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_3) = params->EmcPmacroQuseDdllRank1_3; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_4) = params->EmcPmacroQuseDdllRank1_4; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_5) = params->EmcPmacroQuseDdllRank1_5; + MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = params->EmcPmacroBrickCtrlRfu1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0) = params->EmcPmacroObDdllLongDqRank0_0; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1) = params->EmcPmacroObDdllLongDqRank0_1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2) = params->EmcPmacroObDdllLongDqRank0_2; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3) = params->EmcPmacroObDdllLongDqRank0_3; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4) = params->EmcPmacroObDdllLongDqRank0_4; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5) = params->EmcPmacroObDdllLongDqRank0_5; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0) = params->EmcPmacroObDdllLongDqRank1_0; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1) = params->EmcPmacroObDdllLongDqRank1_1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2) = params->EmcPmacroObDdllLongDqRank1_2; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3) = params->EmcPmacroObDdllLongDqRank1_3; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4) = params->EmcPmacroObDdllLongDqRank1_4; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5) = params->EmcPmacroObDdllLongDqRank1_5; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0) = params->EmcPmacroObDdllLongDqsRank0_0; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1) = params->EmcPmacroObDdllLongDqsRank0_1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2) = params->EmcPmacroObDdllLongDqsRank0_2; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3) = params->EmcPmacroObDdllLongDqsRank0_3; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4) = params->EmcPmacroObDdllLongDqsRank0_4; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5) = params->EmcPmacroObDdllLongDqsRank0_5; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0) = params->EmcPmacroObDdllLongDqsRank1_0; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1) = params->EmcPmacroObDdllLongDqsRank1_1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2) = params->EmcPmacroObDdllLongDqsRank1_2; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3) = params->EmcPmacroObDdllLongDqsRank1_3; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4) = params->EmcPmacroObDdllLongDqsRank1_4; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5) = params->EmcPmacroObDdllLongDqsRank1_5; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0) = params->EmcPmacroIbDdllLongDqsRank0_0; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1) = params->EmcPmacroIbDdllLongDqsRank0_1; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2) = params->EmcPmacroIbDdllLongDqsRank0_2; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3) = params->EmcPmacroIbDdllLongDqsRank0_3; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0) = params->EmcPmacroIbDdllLongDqsRank1_0; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1) = params->EmcPmacroIbDdllLongDqsRank1_1; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2) = params->EmcPmacroIbDdllLongDqsRank1_2; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3) = params->EmcPmacroIbDdllLongDqsRank1_3; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_0) = params->EmcPmacroDdllLongCmd_0; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_1) = params->EmcPmacroDdllLongCmd_1; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_2) = params->EmcPmacroDdllLongCmd_2; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_3) = params->EmcPmacroDdllLongCmd_3; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_4) = params->EmcPmacroDdllLongCmd_4; + MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_0) = params->EmcPmacroDdllShortCmd_0; + MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_1) = params->EmcPmacroDdllShortCmd_1; + MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_2) = params->EmcPmacroDdllShortCmd_2; + MAKE_EMC_REG(EMC_PMACRO_COMMON_PAD_TX_CTRL) = ((params->EmcPmacroCommonPadTxCtrl & 1) | 0xE); - if (params->emc_bct_spare4) - *(volatile uint32_t *)params->emc_bct_spare4 = params->emc_bct_spare5; + if (params->EmcBctSpare4) { + *(volatile uint32_t *)params->EmcBctSpare4 = params->EmcBctSpare5; + } MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; - MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = params->mc_video_protect_bom; - MAKE_MC_REG(MC_VIDEO_PROTECT_BOM_ADR_HI) = params->mc_video_protect_bom_adr_hi; - MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = params->mc_video_protect_size_mb; - MAKE_MC_REG(MC_VIDEO_PROTECT_VPR_OVERRIDE) = params->mc_video_protect_vpr_override; - MAKE_MC_REG(MC_VIDEO_PROTECT_VPR_OVERRIDE1) = params->mc_video_protect_vpr_override1; - MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = params->mc_video_protect_gpu_override0; - MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = params->mc_video_protect_gpu_override1; - MAKE_MC_REG(MC_EMEM_ADR_CFG) = params->mc_emem_adr_cfg; - MAKE_MC_REG(MC_EMEM_ADR_CFG_DEV0) = params->mc_emem_adr_cfg_dev0; - MAKE_MC_REG(MC_EMEM_ADR_CFG_DEV1) = params->mc_emem_adr_cfg_dev1; - MAKE_MC_REG(MC_EMEM_ADR_CFG_CHANNEL_MASK) = params->mc_emem_adr_cfg_channel_mask; - MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_0) = params->mc_emem_adr_cfg_bank_mask0; - MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_1) = params->mc_emem_adr_cfg_bank_mask1; - MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_2) = params->mc_emem_adr_cfg_bank_mask2; - MAKE_MC_REG(MC_EMEM_CFG) = params->mc_emem_cfg; - MAKE_MC_REG(MC_SEC_CARVEOUT_BOM) = params->mc_sec_carveout_bom; - MAKE_MC_REG(MC_SEC_CARVEOUT_ADR_HI) = params->mc_sec_carveout_adr_hi; - MAKE_MC_REG(MC_SEC_CARVEOUT_SIZE_MB) = params->mc_sec_carveout_size_mb; - MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = params->mc_mts_carveout_bom; - MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = params->mc_mts_carveout_adr_hi; - MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = params->mc_mts_carveout_size_mb; - MAKE_MC_REG(MC_EMEM_ARB_CFG) = params->mc_emem_arb_cfg; - MAKE_MC_REG(MC_EMEM_ARB_OUTSTANDING_REQ) = params->mc_emem_arb_outstanding_req; - MAKE_MC_REG(MC_EMEM_ARB_REFPB_HP_CTRL) = params->emc_emem_arb_refpb_hp_ctrl; - MAKE_MC_REG(MC_EMEM_ARB_REFPB_BANK_CTRL) = params->emc_emem_arb_refpb_bank_ctrl; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RCD) = params->mc_emem_arb_timing_rcd; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RP) = params->mc_emem_arb_timing_rp; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RC) = params->mc_emem_arb_timing_rc; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RAS) = params->mc_emem_arb_timing_ras; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_FAW) = params->mc_emem_arb_timing_faw; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RRD) = params->mc_emem_arb_timing_rrd; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RAP2PRE) = params->mc_emem_arb_timing_rap2pre; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_WAP2PRE) = params->mc_emem_arb_timing_wap2pre; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_R2R) = params->mc_emem_arb_timing_r2r; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_W2W) = params->mc_emem_arb_timing_w2w; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_CCDMW) = params->mc_emem_arb_timing_ccdmw; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_R2W) = params->mc_emem_arb_timing_r2w; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_W2R) = params->mc_emem_arb_timing_w2r; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RFCPB) = params->mc_emem_arb_timing_rfcpb; - MAKE_MC_REG(MC_EMEM_ARB_DA_TURNS) = params->mc_emem_arb_da_turns; - MAKE_MC_REG(MC_EMEM_ARB_DA_COVERS) = params->mc_emem_arb_da_covers; - MAKE_MC_REG(MC_EMEM_ARB_MISC0) = params->mc_emem_arb_misc0; - MAKE_MC_REG(MC_EMEM_ARB_MISC1) = params->mc_emem_arb_misc1; - MAKE_MC_REG(MC_EMEM_ARB_MISC2) = params->mc_emem_arb_misc2; - MAKE_MC_REG(MC_EMEM_ARB_RING1_THROTTLE) = params->mc_emem_arb_ring1_throttle; - MAKE_MC_REG(MC_EMEM_ARB_OVERRIDE) = params->mc_emem_arb_override; - MAKE_MC_REG(MC_EMEM_ARB_OVERRIDE_1) = params->mc_emem_arb_override1; - MAKE_MC_REG(MC_EMEM_ARB_RSV) = params->mc_emem_arb_rsv; - MAKE_MC_REG(MC_DA_CONFIG0) = params->mc_da_cfg0; + MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = params->McVideoProtectBom; + MAKE_MC_REG(MC_VIDEO_PROTECT_BOM_ADR_HI) = params->McVideoProtectBomAdrHi; + MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = params->McVideoProtectSizeMb; + MAKE_MC_REG(MC_VIDEO_PROTECT_VPR_OVERRIDE) = params->McVideoProtectVprOverride; + MAKE_MC_REG(MC_VIDEO_PROTECT_VPR_OVERRIDE1) = params->McVideoProtectVprOverride1; + MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = params->McVideoProtectGpuOverride0; + MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = params->McVideoProtectGpuOverride1; + MAKE_MC_REG(MC_EMEM_ADR_CFG) = params->McEmemAdrCfg; + MAKE_MC_REG(MC_EMEM_ADR_CFG_DEV0) = params->McEmemAdrCfgDev0; + MAKE_MC_REG(MC_EMEM_ADR_CFG_DEV1) = params->McEmemAdrCfgDev1; + MAKE_MC_REG(MC_EMEM_ADR_CFG_CHANNEL_MASK) = params->McEmemAdrCfgChannelMask; + MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_0) = params->McEmemAdrCfgBankMask0; + MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_1) = params->McEmemAdrCfgBankMask1; + MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_2) = params->McEmemAdrCfgBankMask2; + MAKE_MC_REG(MC_EMEM_CFG) = params->McEmemCfg; + MAKE_MC_REG(MC_SEC_CARVEOUT_BOM) = params->McSecCarveoutBom; + MAKE_MC_REG(MC_SEC_CARVEOUT_ADR_HI) = params->McSecCarveoutAdrHi; + MAKE_MC_REG(MC_SEC_CARVEOUT_SIZE_MB) = params->McSecCarveoutSizeMb; + MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = params->McMtsCarveoutBom; + MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = params->McMtsCarveoutAdrHi; + MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = params->McMtsCarveoutSizeMb; + MAKE_MC_REG(MC_EMEM_ARB_CFG) = params->McEmemArbCfg; + MAKE_MC_REG(MC_EMEM_ARB_OUTSTANDING_REQ) = params->McEmemArbOutstandingReq; + MAKE_MC_REG(MC_EMEM_ARB_REFPB_HP_CTRL) = params->McEmemArbRefpbHpCtrl; + MAKE_MC_REG(MC_EMEM_ARB_REFPB_BANK_CTRL) = params->McEmemArbRefpbBankCtrl; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RCD) = params->McEmemArbTimingRcd; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RP) = params->McEmemArbTimingRp; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RC) = params->McEmemArbTimingRc; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RAS) = params->McEmemArbTimingRas; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_FAW) = params->McEmemArbTimingFaw; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RRD) = params->McEmemArbTimingRrd; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RAP2PRE) = params->McEmemArbTimingRap2Pre; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_WAP2PRE) = params->McEmemArbTimingWap2Pre; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_R2R) = params->McEmemArbTimingR2R; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_W2W) = params->McEmemArbTimingW2W; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_CCDMW) = params->McEmemArbTimingCcdmw; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_R2W) = params->McEmemArbTimingR2W; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_W2R) = params->McEmemArbTimingW2R; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RFCPB) = params->McEmemArbTimingRFCPB; + MAKE_MC_REG(MC_EMEM_ARB_DA_TURNS) = params->McEmemArbDaTurns; + MAKE_MC_REG(MC_EMEM_ARB_DA_COVERS) = params->McEmemArbDaCovers; + MAKE_MC_REG(MC_EMEM_ARB_MISC0) = params->McEmemArbMisc0; + MAKE_MC_REG(MC_EMEM_ARB_MISC1) = params->McEmemArbMisc1; + MAKE_MC_REG(MC_EMEM_ARB_MISC2) = params->McEmemArbMisc2; + MAKE_MC_REG(MC_EMEM_ARB_RING1_THROTTLE) = params->McEmemArbRing1Throttle; + MAKE_MC_REG(MC_EMEM_ARB_OVERRIDE) = params->McEmemArbOverride; + MAKE_MC_REG(MC_EMEM_ARB_OVERRIDE_1) = params->McEmemArbOverride1; + MAKE_MC_REG(MC_EMEM_ARB_RSV) = params->McEmemArbRsv; + MAKE_MC_REG(MC_DA_CONFIG0) = params->McDaCfg0; MAKE_MC_REG(MC_TIMING_CONTROL) = 1; - MAKE_MC_REG(MC_CLKEN_OVERRIDE) = params->mc_clken_override; - MAKE_MC_REG(MC_STAT_CONTROL) = params->mc_stat_control; + MAKE_MC_REG(MC_CLKEN_OVERRIDE) = params->McClkenOverride; + MAKE_MC_REG(MC_STAT_CONTROL) = params->McStatControl; - MAKE_EMC_REG(EMC_ADR_CFG) = params->emc_adr_cfg; - MAKE_EMC_REG(EMC_CLKEN_OVERRIDE) = params->emc_clken_override; - MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_0) = params->emc_pmacro_auto_cal_cfg0; - MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_1) = params->emc_pmacro_auto_cal_cfg1; - MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_2) = params->emc_pmacro_auto_cal_cfg2; - MAKE_EMC_REG(EMC_AUTO_CAL_VREF_SEL_0) = params->emc_auto_cal_vref_sel0; - MAKE_EMC_REG(EMC_AUTO_CAL_VREF_SEL_1) = params->emc_auto_cal_vref_sel1; - MAKE_EMC_REG(EMC_AUTO_CAL_INTERVAL) = params->emc_auto_cal_interval; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config; - udelay(params->emc_auto_cal_wait); + MAKE_EMC_REG(EMC_ADR_CFG) = params->EmcAdrCfg; + MAKE_EMC_REG(EMC_CLKEN_OVERRIDE) = params->EmcClkenOverride; + MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_0) = params->EmcPmacroAutocalCfg0; + MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_1) = params->EmcPmacroAutocalCfg1; + MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_2) = params->EmcPmacroAutocalCfg2; + MAKE_EMC_REG(EMC_AUTO_CAL_VREF_SEL_0) = params->EmcAutoCalVrefSel0; + MAKE_EMC_REG(EMC_AUTO_CAL_VREF_SEL_1) = params->EmcAutoCalVrefSel1; + MAKE_EMC_REG(EMC_AUTO_CAL_INTERVAL) = params->EmcAutoCalInterval; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG) = params->EmcAutoCalConfig; + udelay(params->EmcAutoCalWait); - if (params->emc_bct_spare8) - *(volatile uint32_t *)params->emc_bct_spare8 = params->emc_bct_spare9; + if (params->EmcBctSpare8) { + *(volatile uint32_t *)params->EmcBctSpare8 = params->EmcBctSpare9; + } - MAKE_EMC_REG(EMC_CFG_2) = params->emc_cfg2; - MAKE_EMC_REG(EMC_CFG_PIPE) = params->emc_cfg_pipe; - MAKE_EMC_REG(EMC_CFG_PIPE_1) = params->emc_cfg_pipe1; - MAKE_EMC_REG(EMC_CFG_PIPE_2) = params->emc_cfg_pipe2; - MAKE_EMC_REG(EMC_CMDQ) = params->emc_cmd_q; - MAKE_EMC_REG(EMC_MC2EMCQ) = params->emc_mc2emc_q; - MAKE_EMC_REG(EMC_MRS_WAIT_CNT) = params->emc_mrs_wait_cnt; - MAKE_EMC_REG(EMC_MRS_WAIT_CNT2) = params->emc_mrs_wait_cnt2; - MAKE_EMC_REG(EMC_FBIO_CFG5) = params->emc_fbio_cfg5; - MAKE_EMC_REG(EMC_RC) = params->emc_rc; - MAKE_EMC_REG(EMC_RFC) = params->emc_rfc; - MAKE_EMC_REG(EMC_RFCPB) = params->emc_rfc_pb; - MAKE_EMC_REG(EMC_REFCTRL2) = params->emc_ref_ctrl2; - MAKE_EMC_REG(EMC_RFC_SLR) = params->emc_rfc_slr; - MAKE_EMC_REG(EMC_RAS) = params->emc_ras; - MAKE_EMC_REG(EMC_RP) = params->emc_rp; - MAKE_EMC_REG(EMC_TPPD) = params->emc_tppd; - MAKE_EMC_REG(EMC_R2R) = params->emc_r2r; - MAKE_EMC_REG(EMC_W2W) = params->emc_w2w; - MAKE_EMC_REG(EMC_R2W) = params->emc_r2w; - MAKE_EMC_REG(EMC_W2R) = params->emc_w2r; - MAKE_EMC_REG(EMC_R2P) = params->emc_r2p; - MAKE_EMC_REG(EMC_W2P) = params->emc_w2p; - MAKE_EMC_REG(EMC_CCDMW) = params->emc_ccdmw; - MAKE_EMC_REG(EMC_RD_RCD) = params->emc_rd_rcd; - MAKE_EMC_REG(EMC_WR_RCD) = params->emc_wr_rcd; - MAKE_EMC_REG(EMC_RRD) = params->emc_rrd; - MAKE_EMC_REG(EMC_REXT) = params->emc_rext; - MAKE_EMC_REG(EMC_WEXT) = params->emc_wext; - MAKE_EMC_REG(EMC_WDV) = params->emc_wdv; - MAKE_EMC_REG(EMC_WDV_CHK) = params->emc_wdv_chk; - MAKE_EMC_REG(EMC_WSV) = params->emc_wsv; - MAKE_EMC_REG(EMC_WEV) = params->emc_wev; - MAKE_EMC_REG(EMC_WDV_MASK) = params->emc_wdv_mask; - MAKE_EMC_REG(EMC_WS_DURATION) = params->emc_ws_duration; - MAKE_EMC_REG(EMC_WE_DURATION) = params->emc_we_duration; - MAKE_EMC_REG(EMC_QUSE) = params->emc_quse; - MAKE_EMC_REG(EMC_QUSE_WIDTH) = params->emc_quse_width; - MAKE_EMC_REG(EMC_IBDLY) = params->emc_ibdly; - MAKE_EMC_REG(EMC_OBDLY) = params->emc_obdly; - MAKE_EMC_REG(EMC_EINPUT) = params->emc_einput; - MAKE_EMC_REG(EMC_EINPUT_DURATION) = params->emc_einput_duration; - MAKE_EMC_REG(EMC_PUTERM_EXTRA) = params->emc_puterm_extra; - MAKE_EMC_REG(EMC_PUTERM_WIDTH) = params->emc_puterm_width; - MAKE_EMC_REG(EMC_PMACRO_COMMON_PAD_TX_CTRL) = params->emc_pmacro_common_pad_tx_ctrl; - MAKE_EMC_REG(EMC_DBG) = params->emc_dbg; - MAKE_EMC_REG(EMC_QRST) = params->emc_qrst; + MAKE_EMC_REG(EMC_CFG_2) = params->EmcCfg2; + MAKE_EMC_REG(EMC_CFG_PIPE) = params->EmcCfgPipe; + MAKE_EMC_REG(EMC_CFG_PIPE_1) = params->EmcCfgPipe1; + MAKE_EMC_REG(EMC_CFG_PIPE_2) = params->EmcCfgPipe2; + MAKE_EMC_REG(EMC_CMDQ) = params->EmcCmdQ; + MAKE_EMC_REG(EMC_MC2EMCQ) = params->EmcMc2EmcQ; + MAKE_EMC_REG(EMC_MRS_WAIT_CNT) = params->EmcMrsWaitCnt; + MAKE_EMC_REG(EMC_MRS_WAIT_CNT2) = params->EmcMrsWaitCnt2; + MAKE_EMC_REG(EMC_FBIO_CFG5) = params->EmcFbioCfg5; + MAKE_EMC_REG(EMC_RC) = params->EmcRc; + MAKE_EMC_REG(EMC_RFC) = params->EmcRfc; + MAKE_EMC_REG(EMC_RFCPB) = params->EmcRfcPb; + MAKE_EMC_REG(EMC_REFCTRL2) = params->EmcRefctrl2; + MAKE_EMC_REG(EMC_RFC_SLR) = params->EmcRfcSlr; + MAKE_EMC_REG(EMC_RAS) = params->EmcRas; + MAKE_EMC_REG(EMC_RP) = params->EmcRp; + MAKE_EMC_REG(EMC_TPPD) = params->EmcTppd; + MAKE_EMC_REG(EMC_R2R) = params->EmcR2r; + MAKE_EMC_REG(EMC_W2W) = params->EmcW2w; + MAKE_EMC_REG(EMC_R2W) = params->EmcR2w; + MAKE_EMC_REG(EMC_W2R) = params->EmcW2r; + MAKE_EMC_REG(EMC_R2P) = params->EmcR2p; + MAKE_EMC_REG(EMC_W2P) = params->EmcW2p; + MAKE_EMC_REG(EMC_CCDMW) = params->EmcCcdmw; + MAKE_EMC_REG(EMC_RD_RCD) = params->EmcRdRcd; + MAKE_EMC_REG(EMC_WR_RCD) = params->EmcWrRcd; + MAKE_EMC_REG(EMC_RRD) = params->EmcRrd; + MAKE_EMC_REG(EMC_REXT) = params->EmcRext; + MAKE_EMC_REG(EMC_WEXT) = params->EmcWext; + MAKE_EMC_REG(EMC_WDV) = params->EmcWdv; + MAKE_EMC_REG(EMC_WDV_CHK) = params->EmcWdvChk; + MAKE_EMC_REG(EMC_WSV) = params->EmcWsv; + MAKE_EMC_REG(EMC_WEV) = params->EmcWev; + MAKE_EMC_REG(EMC_WDV_MASK) = params->EmcWdvMask; + MAKE_EMC_REG(EMC_WS_DURATION) = params->EmcWsDuration; + MAKE_EMC_REG(EMC_WE_DURATION) = params->EmcWeDuration; + MAKE_EMC_REG(EMC_QUSE) = params->EmcQUse; + MAKE_EMC_REG(EMC_QUSE_WIDTH) = params->EmcQuseWidth; + MAKE_EMC_REG(EMC_IBDLY) = params->EmcIbdly; + MAKE_EMC_REG(EMC_OBDLY) = params->EmcObdly; + MAKE_EMC_REG(EMC_EINPUT) = params->EmcEInput; + MAKE_EMC_REG(EMC_EINPUT_DURATION) = params->EmcEInputDuration; + MAKE_EMC_REG(EMC_PUTERM_EXTRA) = params->EmcPutermExtra; + MAKE_EMC_REG(EMC_PUTERM_WIDTH) = params->EmcPutermWidth; + MAKE_EMC_REG(EMC_PMACRO_COMMON_PAD_TX_CTRL) = params->EmcPmacroCommonPadTxCtrl; + MAKE_EMC_REG(EMC_DBG) = params->EmcDbg; + MAKE_EMC_REG(EMC_QRST) = params->EmcQRst; MAKE_EMC_REG(EMC_ISSUE_QRST) = 0; - MAKE_EMC_REG(EMC_QSAFE) = params->emc_qsafe; - MAKE_EMC_REG(EMC_RDV) = params->emc_rdv; - MAKE_EMC_REG(EMC_RDV_MASK) = params->emc_rdv_mask; - MAKE_EMC_REG(EMC_RDV_EARLY) = params->emc_rdv_early; - MAKE_EMC_REG(EMC_RDV_EARLY_MASK) = params->emc_rdv_early_mask; - MAKE_EMC_REG(EMC_QPOP) = params->emc_qpop; - MAKE_EMC_REG(EMC_REFRESH) = params->emc_refresh; - MAKE_EMC_REG(EMC_BURST_REFRESH_NUM) = params->emc_burst_refresh_num; - MAKE_EMC_REG(EMC_PRE_REFRESH_REQ_CNT) = params->emc_prerefresh_req_cnt; - MAKE_EMC_REG(EMC_PDEX2WR) = params->emc_pdex2wr; - MAKE_EMC_REG(EMC_PDEX2RD) = params->emc_pdex2rd; - MAKE_EMC_REG(EMC_PCHG2PDEN) = params->emc_pchg2pden; - MAKE_EMC_REG(EMC_ACT2PDEN) = params->emc_act2pden; - MAKE_EMC_REG(EMC_AR2PDEN) = params->emc_ar2pden; - MAKE_EMC_REG(EMC_RW2PDEN) = params->emc_rw2pden; - MAKE_EMC_REG(EMC_CKE2PDEN) = params->emc_cke2pden; - MAKE_EMC_REG(EMC_PDEX2CKE) = params->emc_pdex2che; - MAKE_EMC_REG(EMC_PDEX2MRR) = params->emc_pdex2mrr; - MAKE_EMC_REG(EMC_TXSR) = params->emc_txsr; - MAKE_EMC_REG(EMC_TXSRDLL) = params->emc_txsr_dll; - MAKE_EMC_REG(EMC_TCKE) = params->emc_tcke; - MAKE_EMC_REG(EMC_TCKESR) = params->emc_tckesr; - MAKE_EMC_REG(EMC_TPD) = params->emc_tpd; - MAKE_EMC_REG(EMC_TFAW) = params->emc_tfaw; - MAKE_EMC_REG(EMC_TRPAB) = params->emc_trpab; - MAKE_EMC_REG(EMC_TCLKSTABLE) = params->emc_tclkstable; - MAKE_EMC_REG(EMC_TCLKSTOP) = params->emc_tclkstop; - MAKE_EMC_REG(EMC_TREFBW) = params->emc_trefbw; - MAKE_EMC_REG(EMC_ODT_WRITE) = params->emc_odt_write; - MAKE_EMC_REG(EMC_CFG_DIG_DLL) = params->emc_cfg_dig_dll; - MAKE_EMC_REG(EMC_CFG_DIG_DLL_PERIOD) = params->emc_cfg_dig_dll_period; - MAKE_EMC_REG(EMC_FBIO_SPARE) = params->emc_fbio_spare & 0xFFFFFFFD; - MAKE_EMC_REG(EMC_CFG_RSV) = params->emc_cfg_rsv; - MAKE_EMC_REG(EMC_PMC_SCRATCH1) = params->emc_pmc_scratch1; - MAKE_EMC_REG(EMC_PMC_SCRATCH2) = params->emc_pmc_scratch2; - MAKE_EMC_REG(EMC_PMC_SCRATCH3) = params->emc_pmc_scratch3; - MAKE_EMC_REG(EMC_ACPD_CONTROL) = params->emc_acpd_control; - MAKE_EMC_REG(EMC_TXDSRVTTGEN) = params->emc_txdsrvttgen; - MAKE_EMC_REG(EMC_CFG) = (params->emc_cfg & 0xE) | 0x3C00000; + MAKE_EMC_REG(EMC_QSAFE) = params->EmcQSafe; + MAKE_EMC_REG(EMC_RDV) = params->EmcRdv; + MAKE_EMC_REG(EMC_RDV_MASK) = params->EmcRdvMask; + MAKE_EMC_REG(EMC_RDV_EARLY) = params->EmcRdvEarly; + MAKE_EMC_REG(EMC_RDV_EARLY_MASK) = params->EmcRdvEarlyMask; + MAKE_EMC_REG(EMC_QPOP) = params->EmcQpop; + MAKE_EMC_REG(EMC_REFRESH) = params->EmcRefresh; + MAKE_EMC_REG(EMC_BURST_REFRESH_NUM) = params->EmcBurstRefreshNum; + MAKE_EMC_REG(EMC_PRE_REFRESH_REQ_CNT) = params->EmcPreRefreshReqCnt; + MAKE_EMC_REG(EMC_PDEX2WR) = params->EmcPdEx2Wr; + MAKE_EMC_REG(EMC_PDEX2RD) = params->EmcPdEx2Rd; + MAKE_EMC_REG(EMC_PCHG2PDEN) = params->EmcPChg2Pden; + MAKE_EMC_REG(EMC_ACT2PDEN) = params->EmcAct2Pden; + MAKE_EMC_REG(EMC_AR2PDEN) = params->EmcAr2Pden; + MAKE_EMC_REG(EMC_RW2PDEN) = params->EmcRw2Pden; + MAKE_EMC_REG(EMC_CKE2PDEN) = params->EmcCke2Pden; + MAKE_EMC_REG(EMC_PDEX2CKE) = params->EmcPdex2Cke; + MAKE_EMC_REG(EMC_PDEX2MRR) = params->EmcPdex2Mrr; + MAKE_EMC_REG(EMC_TXSR) = params->EmcTxsr; + MAKE_EMC_REG(EMC_TXSRDLL) = params->EmcTxsrDll; + MAKE_EMC_REG(EMC_TCKE) = params->EmcTcke; + MAKE_EMC_REG(EMC_TCKESR) = params->EmcTckesr; + MAKE_EMC_REG(EMC_TPD) = params->EmcTpd; + MAKE_EMC_REG(EMC_TFAW) = params->EmcTfaw; + MAKE_EMC_REG(EMC_TRPAB) = params->EmcTrpab; + MAKE_EMC_REG(EMC_TCLKSTABLE) = params->EmcTClkStable; + MAKE_EMC_REG(EMC_TCLKSTOP) = params->EmcTClkStop; + MAKE_EMC_REG(EMC_TREFBW) = params->EmcTRefBw; + MAKE_EMC_REG(EMC_ODT_WRITE) = params->EmcOdtWrite; + MAKE_EMC_REG(EMC_CFG_DIG_DLL) = params->EmcCfgDigDll; + MAKE_EMC_REG(EMC_CFG_DIG_DLL_PERIOD) = params->EmcCfgDigDllPeriod; + MAKE_EMC_REG(EMC_FBIO_SPARE) = params->EmcFbioSpare & 0xFFFFFFFD; + MAKE_EMC_REG(EMC_CFG_RSV) = params->EmcCfgRsv; + MAKE_EMC_REG(EMC_PMC_SCRATCH1) = params->EmcPmcScratch1; + MAKE_EMC_REG(EMC_PMC_SCRATCH2) = params->EmcPmcScratch2; + MAKE_EMC_REG(EMC_PMC_SCRATCH3) = params->EmcPmcScratch3; + MAKE_EMC_REG(EMC_ACPD_CONTROL) = params->EmcAcpdControl; + MAKE_EMC_REG(EMC_TXDSRVTTGEN) = params->EmcTxdsrvttgen; + MAKE_EMC_REG(EMC_CFG) = (params->EmcCfg & 0xE) | 0x3C00000; - if (params->boot_rom_patch_control & 0x80000000) - { - *(volatile uint32_t *)(4 * (params->boot_rom_patch_control + 0x1C000000)) = params->boot_rom_patch_data; + if (params->BootRomPatchControl & 0x80000000) { + *(volatile uint32_t *)(4 * (params->BootRomPatchControl + 0x1C000000)) = params->BootRomPatchData; MAKE_MC_REG(MC_TIMING_CONTROL) = 1; } - pmc->io_dpd3_req = (((4 * params->emc_pmc_scratch1 >> 2) + 0x40000000) & 0xCFFF0000); - udelay(params->pmc_io_dpd3_req_wait); + pmc->io_dpd3_req = (((4 * params->EmcPmcScratch1 >> 2) + 0x40000000) & 0xCFFF0000); + udelay(params->PmcIoDpd3ReqWait); - if (!params->emc_auto_cal_interval) - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG) = (params->emc_auto_cal_config | 0x200); + if (!params->EmcAutoCalInterval) { + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG) = (params->EmcAutoCalConfig | 0x200); + } - MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU2) = params->emc_pmacro_brick_ctrl_rfu2; + MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU2) = params->EmcPmacroBrickCtrlRfu2; - if (params->emc_zcal_warm_cold_boot_enables & 1) - { - if (params->memory_type == 2) - MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = (8 * params->emc_zcal_wait_cnt); - - if (params->memory_type == 3) - { - MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt; - MAKE_EMC_REG(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; + if (params->EmcZcalWarmColdBootEnables & 1) { + if (params->MemoryType == NvBootMemoryType_Ddr3) { + MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = (8 * params->EmcZcalWaitCnt); + } else if (params->MemoryType == NvBootMemoryType_LpDdr4) { + MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = params->EmcZcalWaitCnt; + MAKE_EMC_REG(EMC_ZCAL_MRW_CMD) = params->EmcZcalMrwCmd; } } MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; - udelay(params->emc_timing_control_wait); + udelay(params->EmcTimingControlWait); pmc->ddr_cntrl &= 0xFFF8007F; - udelay(params->pmc_ddr_ctrl_wait); + udelay(params->PmcDdrCntrlWait); - if (params->memory_type == 2) - { - MAKE_EMC_REG(EMC_PIN) = ((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)); - udelay(params->emc_pin_extra_wait + 200); - MAKE_EMC_REG(EMC_PIN) = (((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 256); - udelay(params->emc_pin_extra_wait + 500); + MAKE_EMC_REG(EMC_PIN) = (params->EmcPinGpioEn << 16) | (params->EmcPinGpio << 12); + udelay(params->EmcPinExtraWait + 200); + MAKE_EMC_REG(EMC_PIN) = ((params->EmcPinGpioEn << 16) | (params->EmcPinGpio << 12)) + 256; + + if (params->MemoryType == NvBootMemoryType_Ddr3) { + udelay(params->EmcPinExtraWait + 500); + } else if (params->MemoryType == NvBootMemoryType_LpDdr4) { + udelay(params->EmcPinExtraWait + 2000); } - if (params->memory_type == 3) - { - MAKE_EMC_REG(EMC_PIN) = ((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)); - udelay(params->emc_pin_extra_wait + 200); - MAKE_EMC_REG(EMC_PIN) = (((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 256); - udelay(params->emc_pin_extra_wait + 2000); - } + MAKE_EMC_REG(EMC_PIN) = (((params->EmcPinGpioEn << 16) | (params->EmcPinGpio << 12)) + 0x101); + udelay(params->EmcPinProgramWait); - MAKE_EMC_REG(EMC_PIN) = (((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 0x101); - udelay(params->emc_pin_program_wait); - - if (params->memory_type != 3) - MAKE_EMC_REG(EMC_NOP) = ((params->emc_dev_select << 30) + 1); - - if (params->memory_type == 1) - udelay(params->emc_pin_extra_wait + 200); - - if (params->memory_type == 3) - { - if (params->emc_bct_spare10) - *(volatile uint32_t *)params->emc_bct_spare10 = params->emc_bct_spare11; + if (params->MemoryType != NvBootMemoryType_LpDdr4) { + MAKE_EMC_REG(EMC_NOP) = (params->EmcDevSelect << 30) + 1; + if (params->MemoryType == NvBootMemoryType_LpDdr2) { + udelay(params->EmcPinExtraWait + 200); + } + } else { + if (params->EmcBctSpare10) { + *(volatile uint32_t *)params->EmcBctSpare10 = params->EmcBctSpare11; + } - MAKE_EMC_REG(EMC_MRW2) = params->emc_mrw2; - MAKE_EMC_REG(EMC_MRW) = params->emc_mrw1; - MAKE_EMC_REG(EMC_MRW3) = params->emc_mrw3; - MAKE_EMC_REG(EMC_MRW4) = params->emc_mrw4; - MAKE_EMC_REG(EMC_MRW6) = params->emc_mrw6; - MAKE_EMC_REG(EMC_MRW14) = params->emc_mrw14; - MAKE_EMC_REG(EMC_MRW8) = params->emc_mrw8; - MAKE_EMC_REG(EMC_MRW12) = params->emc_mrw12; - MAKE_EMC_REG(EMC_MRW9) = params->emc_mrw9; - MAKE_EMC_REG(EMC_MRW13) = params->emc_mrw13; + MAKE_EMC_REG(EMC_MRW2) = params->EmcMrw2; + MAKE_EMC_REG(EMC_MRW) = params->EmcMrw1; + MAKE_EMC_REG(EMC_MRW3) = params->EmcMrw3; + MAKE_EMC_REG(EMC_MRW4) = params->EmcMrw4; + MAKE_EMC_REG(EMC_MRW6) = params->EmcMrw6; + MAKE_EMC_REG(EMC_MRW14) = params->EmcMrw14; + MAKE_EMC_REG(EMC_MRW8) = params->EmcMrw8; + MAKE_EMC_REG(EMC_MRW12) = params->EmcMrw12; + MAKE_EMC_REG(EMC_MRW9) = params->EmcMrw9; + MAKE_EMC_REG(EMC_MRW13) = params->EmcMrw13; - if (params->emc_zcal_warm_cold_boot_enables & 1) - { - MAKE_EMC_REG(EMC_ZQ_CAL) = params->emc_zcal_init_dev0; - udelay(params->emc_zcal_init_wait); - MAKE_EMC_REG(EMC_ZQ_CAL) = (params->emc_zcal_init_dev0 ^ 3); + if (params->EmcZcalWarmColdBootEnables & 1) { + MAKE_EMC_REG(EMC_ZQ_CAL) = params->EmcZcalInitDev0; + udelay(params->EmcZcalInitWait); + MAKE_EMC_REG(EMC_ZQ_CAL) = (params->EmcZcalInitDev0 ^ 3); - if (!(params->emc_dev_select & 2)) - { - MAKE_EMC_REG(EMC_ZQ_CAL) = params->emc_zcal_init_dev1; - udelay(params->emc_zcal_init_wait); - MAKE_EMC_REG(EMC_ZQ_CAL) = (params->emc_zcal_init_dev1 ^ 3); + if (!(params->EmcDevSelect & 2)) { + MAKE_EMC_REG(EMC_ZQ_CAL) = params->EmcZcalInitDev1; + udelay(params->EmcZcalInitWait); + MAKE_EMC_REG(EMC_ZQ_CAL) = (params->EmcZcalInitDev1 ^ 3); } } } - pmc->ddr_cfg = params->pmc_ddr_cfg; - if ((params->memory_type - 1) <= 2) - { - MAKE_EMC_REG(EMC_ZCAL_INTERVAL) = params->emc_zcal_interval; - MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt; - MAKE_EMC_REG(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; + pmc->ddr_cfg = params->PmcDdrCfg; + if ((params->MemoryType == NvBootMemoryType_LpDdr2) + || (params->MemoryType == NvBootMemoryType_Ddr3) + || (params->MemoryType == NvBootMemoryType_LpDdr4)) { + MAKE_EMC_REG(EMC_ZCAL_INTERVAL) = params->EmcZcalInterval; + MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = params->EmcZcalWaitCnt; + MAKE_EMC_REG(EMC_ZCAL_MRW_CMD) = params->EmcZcalMrwCmd; } - if (params->emc_bct_spare12) - *(volatile uint32_t *)params->emc_bct_spare12 = params->emc_bct_spare13; + if (params->EmcBctSpare12) { + *(volatile uint32_t *)params->EmcBctSpare12 = params->EmcBctSpare13; + } MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; - if (params->emc_extra_refresh_num) - MAKE_EMC_REG(EMC_REF) = (((1 << params->emc_extra_refresh_num << 8) - 0xFD) | (params->emc_pin_gpio << 30)); + if (params->EmcExtraRefreshNum) { + MAKE_EMC_REG(EMC_REF) = (((1 << params->EmcExtraRefreshNum << 8) - 0xFD) | (params->EmcPinGpio << 30)); + } - MAKE_EMC_REG(EMC_REFCTRL) = (params->emc_dev_select | 0x80000000); - MAKE_EMC_REG(EMC_DYN_SELF_REF_CONTROL) = params->emc_dyn_self_ref_control; - MAKE_EMC_REG(EMC_CFG_UPDATE) = params->emc_cfg_update; - MAKE_EMC_REG(EMC_CFG) = params->emc_cfg; - MAKE_EMC_REG(EMC_FDPD_CTRL_DQ) = params->emc_fdpd_ctrl_dq; - MAKE_EMC_REG(EMC_FDPD_CTRL_CMD) = params->emc_fdpd_ctrl_cmd; - MAKE_EMC_REG(EMC_SEL_DPD_CTRL) = params->emc_sel_dpd_ctrl; - MAKE_EMC_REG(EMC_FBIO_SPARE) = (params->emc_fbio_spare | 2); + MAKE_EMC_REG(EMC_REFCTRL) = (params->EmcDevSelect | 0x80000000); + MAKE_EMC_REG(EMC_DYN_SELF_REF_CONTROL) = params->EmcDynSelfRefControl; + MAKE_EMC_REG(EMC_CFG_UPDATE) = params->EmcCfgUpdate; + MAKE_EMC_REG(EMC_CFG) = params->EmcCfg; + MAKE_EMC_REG(EMC_FDPD_CTRL_DQ) = params->EmcFdpdCtrlDq; + MAKE_EMC_REG(EMC_FDPD_CTRL_CMD) = params->EmcFdpdCtrlCmd; + MAKE_EMC_REG(EMC_SEL_DPD_CTRL) = params->EmcSelDpdCtrl; + MAKE_EMC_REG(EMC_FBIO_SPARE) = (params->EmcFbioSpare | 2); MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; - MAKE_EMC_REG(EMC_CFG_PIPE_CLK) = params->emc_cfg_pipe_clk; - MAKE_EMC_REG(EMC_FDPD_CTRL_CMD_NO_RAMP) = params->emc_fdpd_ctrl_cmd_no_ramp; + MAKE_EMC_REG(EMC_CFG_PIPE_CLK) = params->EmcCfgPipeClk; + MAKE_EMC_REG(EMC_FDPD_CTRL_CMD_NO_RAMP) = params->EmcFdpdCtrlCmdNoRamp; - AHB_ARBITRATION_XBAR_CTRL_0 = ((AHB_ARBITRATION_XBAR_CTRL_0 & 0xFFFEFFFF) | ((params->ahb_arbitration_xbar_ctrl_meminit_done & 0xFFFF) << 16)); + AHB_ARBITRATION_XBAR_CTRL_0 = ((AHB_ARBITRATION_XBAR_CTRL_0 & 0xFFFEFFFF) | ((params->AhbArbitrationXbarCtrlMemInitDone & 0xFFFF) << 16)); - MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = params->mc_video_protect_write_access; - MAKE_MC_REG(MC_SEC_CARVEOUT_REG_CTRL) = params->mc_sec_carveout_protect_write_access; - MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = params->mc_mts_carveout_reg_ctrl; - MAKE_MC_REG(MC_EMEM_CFG_ACCESS_CTRL) = 1; /* Disable write access to a bunch of MC registers. */ + MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = params->McVideoProtectWriteAccess; + MAKE_MC_REG(MC_SEC_CARVEOUT_REG_CTRL) = params->McSecCarveoutProtectWriteAccess; + MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = params->McMtsCarveoutRegCtrl; + MAKE_MC_REG(MC_EMEM_CFG_ACCESS_CTRL) = 1; } -const void *sdram_get_params() -{ - /* TODO: sdram_id should be in [0, 7]. */ +static void sdram_config_mariko(const sdram_params_mariko_t *params) { + volatile tegra_car_t *car = car_get_regs(); + volatile tegra_pmc_t *pmc = pmc_get_regs(); + + if (params->EmcBctSpare0) { + *(volatile uint32_t *)params->EmcBctSpare0 = params->EmcBctSpare1; + } + + if (params->ClkRstControllerPllmMisc2OverrideEnable) { + car->pllm_misc2 = params->ClkRstControllerPllmMisc2Override; + } + + pmc->weak_bias = ((~params->EmcPmcScratch1 & 0x1000) << 19) | ((~params->EmcPmcScratch1 & 0xFFF) << 18) | ((~params->EmcPmcScratch1 & 0x8000) << 15); + pmc->io_dpd3_req = (~params->EmcPmcScratch1 & 0x9FFF) + 0x80000000; + udelay(params->PmcIoDpd3ReqWait); + pmc->io_dpd4_req = (~params->EmcPmcScratch2 & 0x3FFF0000) + 0x80000000; + udelay(params->PmcIoDpd4ReqWait); + pmc->io_dpd4_req = (~params->EmcPmcScratch2 & 0x1FFF) + 0x80000000; + udelay(1); + + MAKE_EMC_REG(EMC_FBIO_CFG7) = params->EmcFbioCfg7; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_0) = params->EmcCmdMappingCmd0_0; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_1) = params->EmcCmdMappingCmd0_1; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_2) = params->EmcCmdMappingCmd0_2; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_0) = params->EmcCmdMappingCmd1_0; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_1) = params->EmcCmdMappingCmd1_1; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_2) = params->EmcCmdMappingCmd1_2; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_0) = params->EmcCmdMappingCmd2_0; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_1) = params->EmcCmdMappingCmd2_1; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_2) = params->EmcCmdMappingCmd2_2; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_0) = params->EmcCmdMappingCmd3_0; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_1) = params->EmcCmdMappingCmd3_1; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_2) = params->EmcCmdMappingCmd3_2; + MAKE_EMC_REG(EMC_CMD_MAPPING_BYTE) = params->EmcCmdMappingByte; + MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_0) = params->EmcPmacroBrickMapping0; + MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_1) = params->EmcPmacroBrickMapping1; + MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_2) = params->EmcPmacroBrickMapping2; + MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_0) = params->EmcPmacroVttgenCtrl0; + MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_1) = params->EmcPmacroVttgenCtrl1; + MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_2) = params->EmcPmacroVttgenCtrl2; + MAKE_EMC_REG(EMC_PMACRO_BG_BIAS_CTRL_0) = params->EmcPmacroBgBiasCtrl0; + + if (params->EmcBctSpareSecure0) { + *(volatile uint32_t *)params->EmcBctSpareSecure0 = params->EmcBctSpareSecure1; + } + if (params->EmcBctSpareSecure2) { + *(volatile uint32_t *)params->EmcBctSpareSecure2 = params->EmcBctSpareSecure3; + } + if (params->EmcBctSpareSecure4) { + *(volatile uint32_t *)params->EmcBctSpareSecure4 = params->EmcBctSpareSecure5; + } + + MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; + udelay(params->PmcVddpSelWait + 2); + car->clk_source_emc = params->EmcClockSource; + car->clk_source_emc_dll = params->EmcClockSourceDll; + MAKE_EMC_REG(EMC_DBG) = params->EmcDbg | 2 * params->EmcDbgWriteMux; + + if (params->EmcBctSpare2) { + *(volatile uint32_t *)params->EmcBctSpare2 = params->EmcBctSpare3; + } + + MAKE_EMC_REG(EMC_CONFIG_SAMPLE_DELAY) = params->EmcConfigSampleDelay; + MAKE_EMC_REG(EMC_FBIO_CFG8) = params->EmcFbioCfg8; + MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE0) = params->EmcSwizzleRank0Byte0; + MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE1) = params->EmcSwizzleRank0Byte1; + MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE2) = params->EmcSwizzleRank0Byte2; + MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE3) = params->EmcSwizzleRank0Byte3; + MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE0) = params->EmcSwizzleRank1Byte0; + MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE1) = params->EmcSwizzleRank1Byte1; + MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE2) = params->EmcSwizzleRank1Byte2; + MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE3) = params->EmcSwizzleRank1Byte3; + + if (params->EmcBctSpare6) { + *(volatile uint32_t *)params->EmcBctSpare6 = params->EmcBctSpare7; + } + + MAKE_EMC_REG(EMC_XM2COMPPADCTRL) = params->EmcXm2CompPadCtrl; + MAKE_EMC_REG(EMC_XM2COMPPADCTRL2) = params->EmcXm2CompPadCtrl2; + MAKE_EMC_REG(EMC_XM2COMPPADCTRL3) = params->EmcXm2CompPadCtrl3; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG2) = params->EmcAutoCalConfig2; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG3) = params->EmcAutoCalConfig3; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG4) = params->EmcAutoCalConfig4; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG5) = params->EmcAutoCalConfig5; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG6) = params->EmcAutoCalConfig6; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG7) = params->EmcAutoCalConfig7; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG8) = params->EmcAutoCalConfig8; + MAKE_EMC_REG(EMC_PMACRO_RX_TERM) = params->EmcPmacroRxTerm; + MAKE_EMC_REG(EMC_PMACRO_DQ_TX_DRV) = params->EmcPmacroDqTxDrv; + MAKE_EMC_REG(EMC_PMACRO_CA_TX_DRV) = params->EmcPmacroCaTxDrv; + MAKE_EMC_REG(EMC_PMACRO_CMD_TX_DRV) = params->EmcPmacroCmdTxDrv; + MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_COMMON) = params->EmcPmacroAutocalCfgCommon; + MAKE_EMC_REG(EMC_AUTO_CAL_CHANNEL) = params->EmcAutoCalChannel; + MAKE_EMC_REG(EMC_PMACRO_ZCTRL) = params->EmcPmacroZctrl; + MAKE_EMC_REG(EMC_DLL_CFG_0) = params->EmcPmacroDllCfg0; + MAKE_EMC_REG(EMC_DLL_CFG_1) = params->EmcPmacroDllCfg1; + MAKE_EMC_REG(EMC_CFG_DIG_DLL_1) = params->EmcCfgDigDll_1; + MAKE_EMC_REG(EMC_DATA_BRLSHFT_0) = params->EmcDataBrlshft0; + MAKE_EMC_REG(EMC_DATA_BRLSHFT_1) = params->EmcDataBrlshft1; + MAKE_EMC_REG(EMC_DQS_BRLSHFT_0) = params->EmcDqsBrlshft0; + MAKE_EMC_REG(EMC_DQS_BRLSHFT_1) = params->EmcDqsBrlshft1; + MAKE_EMC_REG(EMC_CMD_BRLSHFT_0) = params->EmcCmdBrlshft0; + MAKE_EMC_REG(EMC_CMD_BRLSHFT_1) = params->EmcCmdBrlshft1; + MAKE_EMC_REG(EMC_CMD_BRLSHFT_2) = params->EmcCmdBrlshft2; + MAKE_EMC_REG(EMC_CMD_BRLSHFT_3) = params->EmcCmdBrlshft3; + MAKE_EMC_REG(EMC_QUSE_BRLSHFT_0) = params->EmcQuseBrlshft0; + MAKE_EMC_REG(EMC_QUSE_BRLSHFT_1) = params->EmcQuseBrlshft1; + MAKE_EMC_REG(EMC_QUSE_BRLSHFT_2) = params->EmcQuseBrlshft2; + MAKE_EMC_REG(EMC_QUSE_BRLSHFT_3) = params->EmcQuseBrlshft3; + MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = params->EmcPmacroBrickCtrlRfu1; + MAKE_EMC_REG(EMC_PMACRO_PAD_CFG_CTRL) = params->EmcPmacroPadCfgCtrl; + MAKE_EMC_REG(EMC_PMACRO_CMD_BRICK_CTRL_FDPD) = params->EmcPmacroCmdBrickCtrlFdpd; + MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU2) = params->EmcPmacroBrickCtrlRfu2; + MAKE_EMC_REG(EMC_PMACRO_DATA_BRICK_CTRL_FDPD) = params->EmcPmacroDataBrickCtrlFdpd; + MAKE_EMC_REG(EMC_PMACRO_DATA_PAD_RX_CTRL) = params->EmcPmacroDataPadRxCtrl; + MAKE_EMC_REG(EMC_PMACRO_CMD_PAD_RX_CTRL) = params->EmcPmacroCmdPadRxCtrl; + MAKE_EMC_REG(EMC_PMACRO_DATA_PAD_TX_CTRL) = params->EmcPmacroDataPadTxCtrl; + MAKE_EMC_REG(EMC_PMACRO_DATA_RX_TERM_MODE) = params->EmcPmacroDataRxTermMode; + MAKE_EMC_REG(EMC_PMACRO_CMD_RX_TERM_MODE) = params->EmcPmacroCmdRxTermMode; + MAKE_EMC_REG(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->EmcPmacroCmdPadTxCtrl & 0xEFFFFFFF; + MAKE_EMC_REG(EMC_CFG_3) = params->EmcCfg3; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_0) = params->EmcPmacroTxPwrd0; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_1) = params->EmcPmacroTxPwrd1; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_2) = params->EmcPmacroTxPwrd2; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_3) = params->EmcPmacroTxPwrd3; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_4) = params->EmcPmacroTxPwrd4; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_5) = params->EmcPmacroTxPwrd5; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_0) = params->EmcPmacroTxSelClkSrc0; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_1) = params->EmcPmacroTxSelClkSrc1; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_2) = params->EmcPmacroTxSelClkSrc2; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_3) = params->EmcPmacroTxSelClkSrc3; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_4) = params->EmcPmacroTxSelClkSrc4; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_5) = params->EmcPmacroTxSelClkSrc5; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_FGCG_CTRL_0) = params->EmcPmacroPerbitFgcgCtrl0; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_FGCG_CTRL_1) = params->EmcPmacroPerbitFgcgCtrl1; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_FGCG_CTRL_2) = params->EmcPmacroPerbitFgcgCtrl2; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_FGCG_CTRL_3) = params->EmcPmacroPerbitFgcgCtrl3; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_FGCG_CTRL_4) = params->EmcPmacroPerbitFgcgCtrl4; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_FGCG_CTRL_5) = params->EmcPmacroPerbitFgcgCtrl5; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU_CTRL_0) = params->EmcPmacroPerbitRfuCtrl0; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU_CTRL_1) = params->EmcPmacroPerbitRfuCtrl1; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU_CTRL_2) = params->EmcPmacroPerbitRfuCtrl2; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU_CTRL_3) = params->EmcPmacroPerbitRfuCtrl3; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU_CTRL_4) = params->EmcPmacroPerbitRfuCtrl4; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU_CTRL_5) = params->EmcPmacroPerbitRfuCtrl5; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU1_CTRL_0) = params->EmcPmacroPerbitRfu1Ctrl0; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU1_CTRL_1) = params->EmcPmacroPerbitRfu1Ctrl1; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU1_CTRL_2) = params->EmcPmacroPerbitRfu1Ctrl2; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU1_CTRL_3) = params->EmcPmacroPerbitRfu1Ctrl3; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU1_CTRL_4) = params->EmcPmacroPerbitRfu1Ctrl4; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU1_CTRL_5) = params->EmcPmacroPerbitRfu1Ctrl5; + MAKE_EMC_REG(EMC_PMACRO_DATA_PI_CTRL) = params->EmcPmacroDataPiCtrl; + MAKE_EMC_REG(EMC_PMACRO_CMD_PI_CTRL) = params->EmcPmacroCmdPiCtrl; + MAKE_EMC_REG(EMC_PMACRO_DDLL_BYPASS) = params->EmcPmacroDdllBypass; + MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_0) = params->EmcPmacroDdllPwrd0; + MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_1) = params->EmcPmacroDdllPwrd1; + MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_2) = params->EmcPmacroDdllPwrd2; + MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_0) = params->EmcPmacroCmdCtrl0; + MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_1) = params->EmcPmacroCmdCtrl1; + MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_2) = params->EmcPmacroCmdCtrl2; + MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQ_0) = params->EmcPmacroIbVrefDq_0; + MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQ_1) = params->EmcPmacroIbVrefDq_1; + MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQS_0) = params->EmcPmacroIbVrefDqs_0; + MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQS_1) = params->EmcPmacroIbVrefDqs_1; + MAKE_EMC_REG(EMC_PMACRO_IB_RXRT) = params->EmcPmacroIbRxrt; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_0) = params->EmcPmacroQuseDdllRank0_0; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_1) = params->EmcPmacroQuseDdllRank0_1; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_2) = params->EmcPmacroQuseDdllRank0_2; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_3) = params->EmcPmacroQuseDdllRank0_3; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_4) = params->EmcPmacroQuseDdllRank0_4; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_5) = params->EmcPmacroQuseDdllRank0_5; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_0) = params->EmcPmacroQuseDdllRank1_0; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_1) = params->EmcPmacroQuseDdllRank1_1; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_2) = params->EmcPmacroQuseDdllRank1_2; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_3) = params->EmcPmacroQuseDdllRank1_3; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_4) = params->EmcPmacroQuseDdllRank1_4; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_5) = params->EmcPmacroQuseDdllRank1_5; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0) = params->EmcPmacroObDdllLongDqRank0_0; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1) = params->EmcPmacroObDdllLongDqRank0_1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2) = params->EmcPmacroObDdllLongDqRank0_2; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3) = params->EmcPmacroObDdllLongDqRank0_3; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4) = params->EmcPmacroObDdllLongDqRank0_4; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5) = params->EmcPmacroObDdllLongDqRank0_5; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0) = params->EmcPmacroObDdllLongDqRank1_0; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1) = params->EmcPmacroObDdllLongDqRank1_1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2) = params->EmcPmacroObDdllLongDqRank1_2; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3) = params->EmcPmacroObDdllLongDqRank1_3; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4) = params->EmcPmacroObDdllLongDqRank1_4; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5) = params->EmcPmacroObDdllLongDqRank1_5; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0) = params->EmcPmacroObDdllLongDqsRank0_0; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1) = params->EmcPmacroObDdllLongDqsRank0_1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2) = params->EmcPmacroObDdllLongDqsRank0_2; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3) = params->EmcPmacroObDdllLongDqsRank0_3; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4) = params->EmcPmacroObDdllLongDqsRank0_4; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5) = params->EmcPmacroObDdllLongDqsRank0_5; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0) = params->EmcPmacroObDdllLongDqsRank1_0; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1) = params->EmcPmacroObDdllLongDqsRank1_1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2) = params->EmcPmacroObDdllLongDqsRank1_2; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3) = params->EmcPmacroObDdllLongDqsRank1_3; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4) = params->EmcPmacroObDdllLongDqsRank1_4; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5) = params->EmcPmacroObDdllLongDqsRank1_5; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0) = params->EmcPmacroIbDdllLongDqsRank0_0; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1) = params->EmcPmacroIbDdllLongDqsRank0_1; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2) = params->EmcPmacroIbDdllLongDqsRank0_2; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3) = params->EmcPmacroIbDdllLongDqsRank0_3; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0) = params->EmcPmacroIbDdllLongDqsRank1_0; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1) = params->EmcPmacroIbDdllLongDqsRank1_1; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2) = params->EmcPmacroIbDdllLongDqsRank1_2; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3) = params->EmcPmacroIbDdllLongDqsRank1_3; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_0) = params->EmcPmacroDdllLongCmd_0; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_1) = params->EmcPmacroDdllLongCmd_1; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_2) = params->EmcPmacroDdllLongCmd_2; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_3) = params->EmcPmacroDdllLongCmd_3; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_4) = params->EmcPmacroDdllLongCmd_4; + MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_0) = params->EmcPmacroDdllShortCmd_0; + MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_1) = params->EmcPmacroDdllShortCmd_1; + MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_2) = params->EmcPmacroDdllShortCmd_2; + MAKE_EMC_REG(EMC_PMACRO_DDLL_PERIODIC_OFFSET) = params->EmcPmacroDdllPeriodicOffset; + + if (params->EmcBctSpare4) { + *(volatile uint32_t *)params->EmcBctSpare4 = params->EmcBctSpare5; + } + if (params->EmcBctSpareSecure6) { + *(volatile uint32_t *)params->EmcBctSpareSecure6 = params->EmcBctSpareSecure7; + } + if (params->EmcBctSpareSecure8) { + *(volatile uint32_t *)params->EmcBctSpareSecure8 = params->EmcBctSpareSecure9; + } + if (params->EmcBctSpareSecure10) { + *(volatile uint32_t *)params->EmcBctSpareSecure10 = params->EmcBctSpareSecure11; + } + + MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; + + MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = params->McVideoProtectBom; + MAKE_MC_REG(MC_VIDEO_PROTECT_BOM_ADR_HI) = params->McVideoProtectBomAdrHi; + MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = params->McVideoProtectSizeMb; + MAKE_MC_REG(MC_VIDEO_PROTECT_VPR_OVERRIDE) = params->McVideoProtectVprOverride; + MAKE_MC_REG(MC_VIDEO_PROTECT_VPR_OVERRIDE1) = params->McVideoProtectVprOverride1; + MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = params->McVideoProtectGpuOverride0; + MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = params->McVideoProtectGpuOverride1; + MAKE_MC_REG(MC_EMEM_ADR_CFG) = params->McEmemAdrCfg; + MAKE_MC_REG(MC_EMEM_ADR_CFG_DEV0) = params->McEmemAdrCfgDev0; + MAKE_MC_REG(MC_EMEM_ADR_CFG_DEV1) = params->McEmemAdrCfgDev1; + MAKE_MC_REG(MC_EMEM_ADR_CFG_CHANNEL_MASK) = params->McEmemAdrCfgChannelMask; + MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_0) = params->McEmemAdrCfgBankMask0; + MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_1) = params->McEmemAdrCfgBankMask1; + MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_2) = params->McEmemAdrCfgBankMask2; + MAKE_MC_REG(MC_EMEM_CFG) = params->McEmemCfg; + MAKE_MC_REG(MC_SEC_CARVEOUT_BOM) = params->McSecCarveoutBom; + MAKE_MC_REG(MC_SEC_CARVEOUT_ADR_HI) = params->McSecCarveoutAdrHi; + MAKE_MC_REG(MC_SEC_CARVEOUT_SIZE_MB) = params->McSecCarveoutSizeMb; + MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = params->McMtsCarveoutBom; + MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = params->McMtsCarveoutAdrHi; + MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = params->McMtsCarveoutSizeMb; + MAKE_MC_REG(MC_EMEM_ARB_CFG) = params->McEmemArbCfg; + MAKE_MC_REG(MC_EMEM_ARB_OUTSTANDING_REQ) = params->McEmemArbOutstandingReq; + MAKE_MC_REG(MC_EMEM_ARB_REFPB_HP_CTRL) = params->McEmemArbRefpbHpCtrl; + MAKE_MC_REG(MC_EMEM_ARB_REFPB_BANK_CTRL) = params->McEmemArbRefpbBankCtrl; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RCD) = params->McEmemArbTimingRcd; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RP) = params->McEmemArbTimingRp; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RC) = params->McEmemArbTimingRc; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RAS) = params->McEmemArbTimingRas; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_FAW) = params->McEmemArbTimingFaw; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RRD) = params->McEmemArbTimingRrd; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RAP2PRE) = params->McEmemArbTimingRap2Pre; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_WAP2PRE) = params->McEmemArbTimingWap2Pre; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_R2R) = params->McEmemArbTimingR2R; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_W2W) = params->McEmemArbTimingW2W; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_CCDMW) = params->McEmemArbTimingCcdmw; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_R2W) = params->McEmemArbTimingR2W; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_W2R) = params->McEmemArbTimingW2R; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RFCPB) = params->McEmemArbTimingRFCPB; + MAKE_MC_REG(MC_EMEM_ARB_DA_TURNS) = params->McEmemArbDaTurns; + MAKE_MC_REG(MC_EMEM_ARB_DA_COVERS) = params->McEmemArbDaCovers; + MAKE_MC_REG(MC_EMEM_ARB_MISC0) = params->McEmemArbMisc0; + MAKE_MC_REG(MC_EMEM_ARB_MISC1) = params->McEmemArbMisc1; + MAKE_MC_REG(MC_EMEM_ARB_MISC2) = params->McEmemArbMisc2; + MAKE_MC_REG(MC_EMEM_ARB_RING1_THROTTLE) = params->McEmemArbRing1Throttle; + MAKE_MC_REG(MC_EMEM_ARB_OVERRIDE) = params->McEmemArbOverride; + MAKE_MC_REG(MC_EMEM_ARB_OVERRIDE_1) = params->McEmemArbOverride1; + MAKE_MC_REG(MC_EMEM_ARB_RSV) = params->McEmemArbRsv; + MAKE_MC_REG(MC_DA_CONFIG0) = params->McDaCfg0; + MAKE_MC_REG(MC_TIMING_CONTROL) = 1; + MAKE_MC_REG(MC_CLKEN_OVERRIDE) = params->McClkenOverride; + MAKE_MC_REG(MC_STAT_CONTROL) = params->McStatControl; + + MAKE_EMC_REG(EMC_ADR_CFG) = params->EmcAdrCfg; + MAKE_EMC_REG(EMC_CLKEN_OVERRIDE) = params->EmcClkenOverride; + MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_0) = params->EmcPmacroAutocalCfg0; + MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_1) = params->EmcPmacroAutocalCfg1; + MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_2) = params->EmcPmacroAutocalCfg2; + MAKE_EMC_REG(EMC_AUTO_CAL_VREF_SEL_0) = params->EmcAutoCalVrefSel0; + MAKE_EMC_REG(EMC_AUTO_CAL_VREF_SEL_1) = params->EmcAutoCalVrefSel1; + MAKE_EMC_REG(EMC_AUTO_CAL_INTERVAL) = params->EmcAutoCalInterval; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG) = params->EmcAutoCalConfig; + udelay(params->EmcAutoCalWait); + + if (params->EmcBctSpare8) { + *(volatile uint32_t *)params->EmcBctSpare8 = params->EmcBctSpare9; + } + + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG9) = params->EmcAutoCalConfig9; + MAKE_EMC_REG(EMC_CFG_2) = params->EmcCfg2; + MAKE_EMC_REG(EMC_CFG_PIPE) = params->EmcCfgPipe; + MAKE_EMC_REG(EMC_CFG_PIPE_1) = params->EmcCfgPipe1; + MAKE_EMC_REG(EMC_CFG_PIPE_2) = params->EmcCfgPipe2; + MAKE_EMC_REG(EMC_CMDQ) = params->EmcCmdQ; + MAKE_EMC_REG(EMC_MC2EMCQ) = params->EmcMc2EmcQ; + MAKE_EMC_REG(EMC_MRS_WAIT_CNT) = params->EmcMrsWaitCnt; + MAKE_EMC_REG(EMC_MRS_WAIT_CNT2) = params->EmcMrsWaitCnt2; + MAKE_EMC_REG(EMC_FBIO_CFG5) = params->EmcFbioCfg5; + MAKE_EMC_REG(EMC_RC) = params->EmcRc; + MAKE_EMC_REG(EMC_RFC) = params->EmcRfc; + MAKE_EMC_REG(EMC_RFCPB) = params->EmcRfcPb; + MAKE_EMC_REG(EMC_REFCTRL2) = params->EmcRefctrl2; + MAKE_EMC_REG(EMC_RFC_SLR) = params->EmcRfcSlr; + MAKE_EMC_REG(EMC_RAS) = params->EmcRas; + MAKE_EMC_REG(EMC_RP) = params->EmcRp; + MAKE_EMC_REG(EMC_TPPD) = params->EmcTppd; + MAKE_EMC_REG(EMC_TRTM) = params->EmcTrtm; + MAKE_EMC_REG(EMC_TWTM) = params->EmcTwtm; + MAKE_EMC_REG(EMC_TRATM) = params->EmcTratm; + MAKE_EMC_REG(EMC_TWATM) = params->EmcTwatm; + MAKE_EMC_REG(EMC_TR2REF) = params->EmcTr2ref; + MAKE_EMC_REG(EMC_R2R) = params->EmcR2r; + MAKE_EMC_REG(EMC_W2W) = params->EmcW2w; + MAKE_EMC_REG(EMC_R2W) = params->EmcR2w; + MAKE_EMC_REG(EMC_W2R) = params->EmcW2r; + MAKE_EMC_REG(EMC_R2P) = params->EmcR2p; + MAKE_EMC_REG(EMC_W2P) = params->EmcW2p; + MAKE_EMC_REG(EMC_CCDMW) = params->EmcCcdmw; + MAKE_EMC_REG(EMC_RD_RCD) = params->EmcRdRcd; + MAKE_EMC_REG(EMC_WR_RCD) = params->EmcWrRcd; + MAKE_EMC_REG(EMC_RRD) = params->EmcRrd; + MAKE_EMC_REG(EMC_REXT) = params->EmcRext; + MAKE_EMC_REG(EMC_WEXT) = params->EmcWext; + MAKE_EMC_REG(EMC_WDV) = params->EmcWdv; + MAKE_EMC_REG(EMC_WDV_CHK) = params->EmcWdvChk; + MAKE_EMC_REG(EMC_WSV) = params->EmcWsv; + MAKE_EMC_REG(EMC_WEV) = params->EmcWev; + MAKE_EMC_REG(EMC_WDV_MASK) = params->EmcWdvMask; + MAKE_EMC_REG(EMC_WS_DURATION) = params->EmcWsDuration; + MAKE_EMC_REG(EMC_WE_DURATION) = params->EmcWeDuration; + MAKE_EMC_REG(EMC_QUSE) = params->EmcQUse; + MAKE_EMC_REG(EMC_QUSE_WIDTH) = params->EmcQuseWidth; + MAKE_EMC_REG(EMC_IBDLY) = params->EmcIbdly; + MAKE_EMC_REG(EMC_OBDLY) = params->EmcObdly; + MAKE_EMC_REG(EMC_EINPUT) = params->EmcEInput; + MAKE_EMC_REG(EMC_EINPUT_DURATION) = params->EmcEInputDuration; + MAKE_EMC_REG(EMC_PUTERM_EXTRA) = params->EmcPutermExtra; + MAKE_EMC_REG(EMC_PUTERM_WIDTH) = params->EmcPutermWidth; + MAKE_EMC_REG(EMC_DBG) = params->EmcDbg; + MAKE_EMC_REG(EMC_QRST) = params->EmcQRst; + MAKE_EMC_REG(EMC_ISSUE_QRST) = 0; + MAKE_EMC_REG(EMC_QSAFE) = params->EmcQSafe; + MAKE_EMC_REG(EMC_RDV) = params->EmcRdv; + MAKE_EMC_REG(EMC_RDV_MASK) = params->EmcRdvMask; + MAKE_EMC_REG(EMC_RDV_EARLY) = params->EmcRdvEarly; + MAKE_EMC_REG(EMC_RDV_EARLY_MASK) = params->EmcRdvEarlyMask; + MAKE_EMC_REG(EMC_QPOP) = params->EmcQpop; + MAKE_EMC_REG(EMC_REFRESH) = params->EmcRefresh; + MAKE_EMC_REG(EMC_BURST_REFRESH_NUM) = params->EmcBurstRefreshNum; + MAKE_EMC_REG(EMC_PRE_REFRESH_REQ_CNT) = params->EmcPreRefreshReqCnt; + MAKE_EMC_REG(EMC_PDEX2WR) = params->EmcPdEx2Wr; + MAKE_EMC_REG(EMC_PDEX2RD) = params->EmcPdEx2Rd; + MAKE_EMC_REG(EMC_PCHG2PDEN) = params->EmcPChg2Pden; + MAKE_EMC_REG(EMC_ACT2PDEN) = params->EmcAct2Pden; + MAKE_EMC_REG(EMC_AR2PDEN) = params->EmcAr2Pden; + MAKE_EMC_REG(EMC_RW2PDEN) = params->EmcRw2Pden; + MAKE_EMC_REG(EMC_CKE2PDEN) = params->EmcCke2Pden; + MAKE_EMC_REG(EMC_PDEX2CKE) = params->EmcPdex2Cke; + MAKE_EMC_REG(EMC_PDEX2MRR) = params->EmcPdex2Mrr; + MAKE_EMC_REG(EMC_TXSR) = params->EmcTxsr; + MAKE_EMC_REG(EMC_TXSRDLL) = params->EmcTxsrDll; + MAKE_EMC_REG(EMC_TCKE) = params->EmcTcke; + MAKE_EMC_REG(EMC_TCKESR) = params->EmcTckesr; + MAKE_EMC_REG(EMC_TPD) = params->EmcTpd; + MAKE_EMC_REG(EMC_TFAW) = params->EmcTfaw; + MAKE_EMC_REG(EMC_TRPAB) = params->EmcTrpab; + MAKE_EMC_REG(EMC_TCLKSTABLE) = params->EmcTClkStable; + MAKE_EMC_REG(EMC_TCLKSTOP) = params->EmcTClkStop; + MAKE_EMC_REG(EMC_TREFBW) = params->EmcTRefBw; + MAKE_EMC_REG(EMC_ODT_WRITE) = params->EmcOdtWrite; + MAKE_EMC_REG(EMC_CFG_DIG_DLL) = params->EmcCfgDigDll; + MAKE_EMC_REG(EMC_CFG_DIG_DLL_PERIOD) = params->EmcCfgDigDllPeriod; + MAKE_EMC_REG(EMC_FBIO_SPARE) = params->EmcFbioSpare & 0xFFFFFFFD; + MAKE_EMC_REG(EMC_CFG_RSV) = params->EmcCfgRsv; + MAKE_EMC_REG(EMC_PMC_SCRATCH1) = params->EmcPmcScratch1; + MAKE_EMC_REG(EMC_PMC_SCRATCH2) = params->EmcPmcScratch2; + MAKE_EMC_REG(EMC_PMC_SCRATCH3) = params->EmcPmcScratch3; + MAKE_EMC_REG(EMC_ACPD_CONTROL) = params->EmcAcpdControl; + MAKE_EMC_REG(EMC_TXDSRVTTGEN) = params->EmcTxdsrvttgen; + MAKE_EMC_REG(EMC_PMACRO_DSR_VTTGEN_CTRL_0) = params->EmcPmacroDsrVttgenCtrl0; + MAKE_EMC_REG(EMC_CFG) = ((((((params->EmcCfg & 4) | 0x3C00000) & 0xFFFFFFF7) | (params->EmcCfg & 8)) & 0xFFFFFFFD) | (params->EmcCfg & 2)); + + if (params->BootRomPatchControl) { + *(volatile uint32_t *)params->BootRomPatchControl = params->BootRomPatchData; + MAKE_MC_REG(MC_TIMING_CONTROL) = 1; + } + + if (params->EmcBctSpareSecure12) { + *(volatile uint32_t *)params->EmcBctSpareSecure12 = params->EmcBctSpareSecure13; + } + if (params->EmcBctSpareSecure14) { + *(volatile uint32_t *)params->EmcBctSpareSecure14 = params->EmcBctSpareSecure15; + } + if (params->EmcBctSpareSecure16) { + *(volatile uint32_t *)params->EmcBctSpareSecure16 = params->EmcBctSpareSecure17; + } + + pmc->io_dpd3_req = ((4 * params->EmcPmcScratch1 >> 2) + 0x40000000) & 0xCFFF0000; + udelay(params->PmcIoDpd3ReqWait); + MAKE_EMC_REG(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->EmcPmacroCmdPadTxCtrl; + + if (params->EmcZcalWarmColdBootEnables & 1) { + if (params->MemoryType == NvBootMemoryType_Ddr3) { + MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = 8 * params->EmcZcalWaitCnt; + } else if (params->MemoryType == NvBootMemoryType_LpDdr4) { + MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = params->EmcZcalWaitCnt; + MAKE_EMC_REG(EMC_ZCAL_MRW_CMD) = params->EmcZcalMrwCmd; + } + } + + MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; + udelay(params->EmcTimingControlWait); + + pmc->ddr_cntrl &= 0xFF78007F; + udelay(params->PmcDdrCntrlWait); + + MAKE_EMC_REG(EMC_PIN) = (params->EmcPinGpioEn << 16) | (params->EmcPinGpio << 12); + udelay(params->EmcPinExtraWait + 200); + MAKE_EMC_REG(EMC_PIN) = ((params->EmcPinGpioEn << 16) | (params->EmcPinGpio << 12)) + 256; + + if (params->MemoryType == NvBootMemoryType_Ddr3) { + udelay(params->EmcPinExtraWait + 500); + } else if (params->MemoryType == NvBootMemoryType_LpDdr4) { + udelay(params->EmcPinExtraWait + 2000); + } + + MAKE_EMC_REG(EMC_PIN) = ((params->EmcPinGpioEn << 16) | (params->EmcPinGpio << 12)) + 257; + udelay(params->EmcPinProgramWait); + + if (params->MemoryType != NvBootMemoryType_LpDdr4) { + MAKE_EMC_REG(EMC_NOP) = (params->EmcDevSelect << 30) + 1; + if (params->MemoryType == NvBootMemoryType_LpDdr2) { + udelay(params->EmcPinExtraWait + 200); + } + } else { + if (params->EmcBctSpare10) { + *(volatile uint32_t *)params->EmcBctSpare10 = params->EmcBctSpare11; + } + + MAKE_EMC_REG(EMC_MRW2) = params->EmcMrw2; + MAKE_EMC_REG(EMC_MRW) = params->EmcMrw1; + MAKE_EMC_REG(EMC_MRW3) = params->EmcMrw3; + MAKE_EMC_REG(EMC_MRW4) = params->EmcMrw4; + MAKE_EMC_REG(EMC_MRW6) = params->EmcMrw6; + MAKE_EMC_REG(EMC_MRW14) = params->EmcMrw14; + MAKE_EMC_REG(EMC_MRW8) = params->EmcMrw8; + MAKE_EMC_REG(EMC_MRW12) = params->EmcMrw12; + MAKE_EMC_REG(EMC_MRW9) = params->EmcMrw9; + MAKE_EMC_REG(EMC_MRW13) = params->EmcMrw13; + + if (params->EmcZcalWarmColdBootEnables & 1) { + MAKE_EMC_REG(EMC_ZQ_CAL) = params->EmcZcalInitDev0; + udelay(params->EmcZcalInitWait); + MAKE_EMC_REG(EMC_ZQ_CAL) = params->EmcZcalInitDev0 ^ 3; + + if (!(params->EmcDevSelect & 2)) { + MAKE_EMC_REG(EMC_ZQ_CAL) = params->EmcZcalInitDev1; + udelay(params->EmcZcalInitWait); + MAKE_EMC_REG(EMC_ZQ_CAL) = params->EmcZcalInitDev1 ^ 3; + } + } + } + + if (params->EmcBctSpareSecure18) { + *(volatile uint32_t *)params->EmcBctSpareSecure18 = params->EmcBctSpareSecure19; + } + if (params->EmcBctSpareSecure20) { + *(volatile uint32_t *)params->EmcBctSpareSecure20 = params->EmcBctSpareSecure21; + } + if (params->EmcBctSpareSecure22) { + *(volatile uint32_t *)params->EmcBctSpareSecure22 = params->EmcBctSpareSecure23; + } + + pmc->ddr_cfg = params->PmcDdrCfg; + if ((params->MemoryType == NvBootMemoryType_LpDdr2) + || (params->MemoryType == NvBootMemoryType_Ddr3) + || (params->MemoryType == NvBootMemoryType_LpDdr4)) { + MAKE_EMC_REG(EMC_ZCAL_INTERVAL) = params->EmcZcalInterval; + MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = params->EmcZcalWaitCnt; + MAKE_EMC_REG(EMC_ZCAL_MRW_CMD) = params->EmcZcalMrwCmd; + } + + if (params->EmcBctSpare12) { + *(volatile uint32_t *)params->EmcBctSpare12 = params->EmcBctSpare13; + } + + MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; + + if (params->EmcExtraRefreshNum) { + MAKE_EMC_REG(EMC_REF) = ((1 << params->EmcExtraRefreshNum << 8) - 253) | (params->EmcDevSelect << 30); + } + + MAKE_EMC_REG(EMC_REFCTRL) = params->EmcDevSelect | 0x80000000; + MAKE_EMC_REG(EMC_DYN_SELF_REF_CONTROL) = params->EmcDynSelfRefControl; + MAKE_EMC_REG(EMC_CFG) = params->EmcCfg; + MAKE_EMC_REG(EMC_FDPD_CTRL_DQ) = params->EmcFdpdCtrlDq; + MAKE_EMC_REG(EMC_FDPD_CTRL_CMD) = params->EmcFdpdCtrlCmd; + MAKE_EMC_REG(EMC_SEL_DPD_CTRL) = params->EmcSelDpdCtrl; + MAKE_EMC_REG(EMC_FBIO_SPARE) = params->EmcFbioSpare | 2; + MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; + MAKE_EMC_REG(EMC_CFG_UPDATE) = params->EmcCfgUpdate; + MAKE_EMC_REG(EMC_CFG_PIPE_CLK) = params->EmcCfgPipeClk; + MAKE_EMC_REG(EMC_FDPD_CTRL_CMD_NO_RAMP) = params->EmcFdpdCtrlCmdNoRamp; + MAKE_MC_REG(MC_UNTRANSLATED_REGION_CHECK) = params->McUntranslatedRegionCheck; + MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = params->McVideoProtectWriteAccess; + MAKE_MC_REG(MC_SEC_CARVEOUT_REG_CTRL) = params->McSecCarveoutProtectWriteAccess; + MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = params->McMtsCarveoutRegCtrl; + MAKE_MC_REG(MC_EMEM_CFG_ACCESS_CTRL) = 1; + + AHB_ARBITRATION_XBAR_CTRL_0 = ((AHB_ARBITRATION_XBAR_CTRL_0 & 0xFFFEFFFF) | ((params->AhbArbitrationXbarCtrlMemInitDone & 0xFFFF) << 16)); +} -#ifdef CONFIG_SDRAM_COMPRESS_CFG +const void *sdram_get_params_erista(uint32_t dram_id) { + uint32_t sdram_params_index = sdram_params_index_table_erista[dram_id]; +#ifdef CONFIG_SDRAM_COMPRESS uint8_t *buf = (uint8_t *)0x40030000; - LZ_Uncompress(_dram_cfg_lz, buf, sizeof(_dram_cfg_lz)); - return (const void *)&buf[sizeof(sdram_params_t) * _get_sdram_id()]; + LZ_Uncompress(sdram_params_erista_lz, buf, sizeof(sdram_params_erista_lz)); + return (const void *)&buf[sizeof(sdram_params_erista_t) * sdram_params_index]; #else - return _dram_cfgs[_get_sdram_id()]; + return sdram_params_erista[sdram_params_index]; #endif } -void sdram_init() -{ - volatile tegra_pmc_t *pmc = pmc_get_regs(); - - /* TODO: sdram_id should be in [0,4]. */ - const sdram_params_t *params = (const sdram_params_t *)sdram_get_params(); +const void *sdram_get_params_mariko(uint32_t dram_id) { + uint32_t sdram_params_index = sdram_params_index_table_mariko[dram_id]; +#ifdef CONFIG_SDRAM_COMPRESS + uint8_t *buf = (uint8_t *)0x40030000; + LZ_Uncompress(sdram_params_mariko_lz, buf, sizeof(sdram_params_mariko_lz)); + return (const void *)&buf[sizeof(sdram_params_mariko_t) * sdram_params_index]; +#else + return sdram_params_mariko[sdram_params_index]; +#endif +} +void sdram_init_erista(void) { + volatile tegra_pmc_t *pmc = pmc_get_regs(); + const sdram_params_erista_t *params = (const sdram_params_erista_t *)sdram_get_params_erista(fuse_get_dram_id()); + + /* Enable VddMemory. */ uint8_t val = 5; i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD_CFG2, &val, 1); val = 40; /* 40 = (1000 * 1100 - 600000) / 12500 -> 1.1V */ i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD1, &val, 1); - pmc->vddp_sel = params->pmc_vddp_sel; - udelay(params->pmc_vddp_sel_wait); - + pmc->vddp_sel = params->PmcVddpSel; + udelay(params->PmcVddpSelWait); pmc->ddr_pwr = pmc->ddr_pwr; - pmc->no_iopower = params->pmc_no_io_power; - pmc->reg_short = params->pmc_reg_short; - pmc->ddr_cntrl = params->pmc_ddr_ctrl; + pmc->no_iopower = params->PmcNoIoPower; + pmc->reg_short = params->PmcRegShort; + pmc->ddr_cntrl = params->PmcDdrCntrl; - if (params->emc_bct_spare0) - *(volatile uint32_t *)params->emc_bct_spare0 = params->emc_bct_spare1; - - _sdram_config(params); + if (params->EmcBctSpare0) { + *(volatile uint32_t *)params->EmcBctSpare0 = params->EmcBctSpare1; + } + + sdram_config_erista(params); } + +void sdram_init_mariko(void) { + volatile tegra_pmc_t *pmc = pmc_get_regs(); + const sdram_params_mariko_t *params = (const sdram_params_mariko_t *)sdram_get_params_mariko(fuse_get_dram_id()); + + /* Enable VddMemory. */ + uint8_t val = 5; + i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD_CFG2, &val, 1); + + pmc->vddp_sel = params->PmcVddpSel; + udelay(params->PmcVddpSelWait); + pmc->no_iopower = params->PmcNoIoPower; + pmc->reg_short = params->PmcRegShort; + pmc->ddr_cntrl = params->PmcDdrCntrl; + + if (params->EmcBctSpare0) { + *(volatile uint32_t *)params->EmcBctSpare0 = params->EmcBctSpare1; + } + + sdram_config_mariko(params); +} + +void sdram_save_params_erista(const void *save_params) { + const sdram_params_erista_t *params = (const sdram_params_erista_t *)save_params; + volatile tegra_pmc_t *pmc = pmc_get_regs(); + +#define pack(src, src_bits, dst, dst_bits) { \ + uint32_t mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \ + dst &= ~(mask << (0 ? dst_bits)); \ + dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \ +} + +#define s(param, src_bits, pmcreg, dst_bits) \ + pack(params->param, src_bits, pmc->pmcreg, dst_bits) + +#define c(value, pmcreg, dst_bits) \ + pack(value, (1 ? dst_bits) - (0 ? dst_bits) : 0, pmc->pmcreg, dst_bits) + +/* 32 bits version of s macro */ +#define s32(param, pmcreg) pmc->pmcreg = params->param + +/* 32 bits version c macro */ +#define c32(value, pmcreg) pmc->pmcreg = value + + //TODO: pkg1.1 (1.X - 3.X) reads them from MC. + // Patch carveout parameters. + /*params->McGeneralizedCarveout1Bom = 0; + params->McGeneralizedCarveout1BomHi = 0; + params->McGeneralizedCarveout1Size128kb = 0; + params->McGeneralizedCarveout1Access0 = 0; + params->McGeneralizedCarveout1Access1 = 0; + params->McGeneralizedCarveout1Access2 = 0; + params->McGeneralizedCarveout1Access3 = 0; + params->McGeneralizedCarveout1Access4 = 0; + params->McGeneralizedCarveout1ForceInternalAccess0 = 0; + params->McGeneralizedCarveout1ForceInternalAccess1 = 0; + params->McGeneralizedCarveout1ForceInternalAccess2 = 0; + params->McGeneralizedCarveout1ForceInternalAccess3 = 0; + params->McGeneralizedCarveout1ForceInternalAccess4 = 0; + params->McGeneralizedCarveout1Cfg0 = 0; + params->McGeneralizedCarveout2Bom = 0x80020000; + params->McGeneralizedCarveout2BomHi = 0; + params->McGeneralizedCarveout2Size128kb = 2; + params->McGeneralizedCarveout2Access0 = 0; + params->McGeneralizedCarveout2Access1 = 0; + params->McGeneralizedCarveout2Access2 = 0x3000000; + params->McGeneralizedCarveout2Access3 = 0; + params->McGeneralizedCarveout2Access4 = 0x300; + params->McGeneralizedCarveout2ForceInternalAccess0 = 0; + params->McGeneralizedCarveout2ForceInternalAccess1 = 0; + params->McGeneralizedCarveout2ForceInternalAccess2 = 0; + params->McGeneralizedCarveout2ForceInternalAccess3 = 0; + params->McGeneralizedCarveout2ForceInternalAccess4 = 0; + params->McGeneralizedCarveout2Cfg0 = 0x440167E; + params->McGeneralizedCarveout3Bom = 0; + params->McGeneralizedCarveout3BomHi = 0; + params->McGeneralizedCarveout3Size128kb = 0; + params->McGeneralizedCarveout3Access0 = 0; + params->McGeneralizedCarveout3Access1 = 0; + params->McGeneralizedCarveout3Access2 = 0x3000000; + params->McGeneralizedCarveout3Access3 = 0; + params->McGeneralizedCarveout3Access4 = 0x300; + params->McGeneralizedCarveout3ForceInternalAccess0 = 0; + params->McGeneralizedCarveout3ForceInternalAccess1 = 0; + params->McGeneralizedCarveout3ForceInternalAccess2 = 0; + params->McGeneralizedCarveout3ForceInternalAccess3 = 0; + params->McGeneralizedCarveout3ForceInternalAccess4 = 0; + params->McGeneralizedCarveout3Cfg0 = 0x4401E7E; + params->McGeneralizedCarveout4Bom = 0; + params->McGeneralizedCarveout4BomHi = 0; + params->McGeneralizedCarveout4Size128kb = 0; + params->McGeneralizedCarveout4Access0 = 0; + params->McGeneralizedCarveout4Access1 = 0; + params->McGeneralizedCarveout4Access2 = 0; + params->McGeneralizedCarveout4Access3 = 0; + params->McGeneralizedCarveout4Access4 = 0; + params->McGeneralizedCarveout4ForceInternalAccess0 = 0; + params->McGeneralizedCarveout4ForceInternalAccess1 = 0; + params->McGeneralizedCarveout4ForceInternalAccess2 = 0; + params->McGeneralizedCarveout4ForceInternalAccess3 = 0; + params->McGeneralizedCarveout4ForceInternalAccess4 = 0; + params->McGeneralizedCarveout4Cfg0 = 0x8F; + params->McGeneralizedCarveout5Bom = 0; + params->McGeneralizedCarveout5BomHi = 0; + params->McGeneralizedCarveout5Size128kb = 0; + params->McGeneralizedCarveout5Access0 = 0; + params->McGeneralizedCarveout5Access1 = 0; + params->McGeneralizedCarveout5Access2 = 0; + params->McGeneralizedCarveout5Access3 = 0; + params->McGeneralizedCarveout5Access4 = 0; + params->McGeneralizedCarveout5ForceInternalAccess0 = 0; + params->McGeneralizedCarveout5ForceInternalAccess1 = 0; + params->McGeneralizedCarveout5ForceInternalAccess2 = 0; + params->McGeneralizedCarveout5ForceInternalAccess3 = 0; + params->McGeneralizedCarveout5ForceInternalAccess4 = 0; + params->McGeneralizedCarveout5Cfg0 = 0x8F;*/ + + //TODO: this is 4.X+ behaviour which seems to work fine for < 4.X. + // Patch carveout parameters. + *(volatile uint32_t *)params->McGeneralizedCarveout1Cfg0 = 0; + *(volatile uint32_t *)params->McGeneralizedCarveout2Cfg0 = 0; + *(volatile uint32_t *)params->McGeneralizedCarveout3Cfg0 = 0; + *(volatile uint32_t *)params->McGeneralizedCarveout4Cfg0 = 0; + *(volatile uint32_t *)params->McGeneralizedCarveout5Cfg0 = 0; + + // Patch SDRAM parameters. + uint32_t t0 = params->EmcSwizzleRank0Byte0 << 5 >> 29 > params->EmcSwizzleRank0Byte0 << 1 >> 29; + uint32_t t1 = (t0 & 0xFFFFFFEF) | ((params->EmcSwizzleRank1Byte0 << 5 >> 29 > params->EmcSwizzleRank1Byte0 << 1 >> 29) << 4); + uint32_t t2 = (t1 & 0xFFFFFFFD) | ((params->EmcSwizzleRank0Byte1 << 5 >> 29 > params->EmcSwizzleRank0Byte1 << 1 >> 29) << 1); + uint32_t t3 = (t2 & 0xFFFFFFDF) | ((params->EmcSwizzleRank1Byte1 << 5 >> 29 > params->EmcSwizzleRank1Byte1 << 1 >> 29) << 5); + uint32_t t4 = (t3 & 0xFFFFFFFB) | ((params->EmcSwizzleRank0Byte2 << 5 >> 29 > params->EmcSwizzleRank0Byte2 << 1 >> 29) << 2); + uint32_t t5 = (t4 & 0xFFFFFFBF) | ((params->EmcSwizzleRank1Byte2 << 5 >> 29 > params->EmcSwizzleRank1Byte2 << 1 >> 29) << 6); + uint32_t t6 = (t5 & 0xFFFFFFF7) | ((params->EmcSwizzleRank0Byte3 << 5 >> 29 > params->EmcSwizzleRank0Byte3 << 1 >> 29) << 3); + uint32_t t7 = (t6 & 0xFFFFFF7F) | ((params->EmcSwizzleRank1Byte3 << 5 >> 29 > params->EmcSwizzleRank1Byte3 << 1 >> 29) << 7); + *(volatile uint32_t *)params->SwizzleRankByteEncode = t7; + *(volatile uint32_t *)params->EmcBctSpare2 = 0x40000DD8; + *(volatile uint32_t *)params->EmcBctSpare3 = t7; + + s(EmcClockSource, 7:0, scratch6, 15:8); + s(EmcClockSourceDll, 7:0, scratch6, 23:16); + s(EmcClockSource, 31:29, scratch6, 26:24); + s(EmcClockSourceDll, 31:29, scratch6, 29:27); + s(EmcClockSourceDll, 11:10, scratch6, 31:30); + s(ClkRstControllerPllmMisc2Override, 9:8, scratch7, 1:0); + s(ClkRstControllerPllmMisc2Override, 2:1, scratch7, 3:2); + s(EmcZqCalLpDdr4WarmBoot, 31:30, scratch7, 5:4); + s(EmcClockSource, 15:15, scratch7, 6:6); + s(EmcClockSource, 26:26, scratch7, 7:7); + s(EmcClockSource, 20:20, scratch7, 8:8); + s(EmcClockSource, 19:19, scratch7, 9:9); + s(ClkRstControllerPllmMisc2Override, 13:13, scratch7, 10:10); + s(ClkRstControllerPllmMisc2Override, 12:12, scratch7, 11:11); + s(ClkRstControllerPllmMisc2Override, 11:11, scratch7, 12:12); + s(ClkRstControllerPllmMisc2Override, 10:10, scratch7, 13:13); + s(ClkRstControllerPllmMisc2Override, 5:5, scratch7, 14:14); + s(ClkRstControllerPllmMisc2Override, 4:4, scratch7, 15:15); + s(ClkRstControllerPllmMisc2Override, 3:3, scratch7, 16:16); + s(ClkRstControllerPllmMisc2Override, 0:0, scratch7, 17:17); + s(EmcZqCalLpDdr4WarmBoot, 1:0, scratch7, 19:18); + s(EmcZqCalLpDdr4WarmBoot, 4:4, scratch7, 20:20); + s(EmcOdtWrite, 5:0, scratch7, 26:21); + s(EmcOdtWrite, 11:8, scratch7, 30:27); + s(EmcOdtWrite, 31:31, scratch7, 31:31); + s(EmcFdpdCtrlCmdNoRamp, 0:0, scratch13, 30:30); + s(EmcCfgPipeClk, 0:0, scratch13, 31:31); + s(McEmemArbMisc2, 0:0, scratch14, 30:30); + s(McDaCfg0, 0:0, scratch14, 31:31); + s(EmcQRst, 6:0, scratch15, 26:20); + s(EmcQRst, 20:16, scratch15, 31:27); + s(EmcPmacroCmdTxDrv, 5:0, scratch16, 25:20); + s(EmcPmacroCmdTxDrv, 13:8, scratch16, 31:26); + s(EmcPmacroAutocalCfg0, 2:0, scratch17, 22:20); + s(EmcPmacroAutocalCfg0, 10:8, scratch17, 25:23); + s(EmcPmacroAutocalCfg0, 18:16, scratch17, 28:26); + s(EmcPmacroAutocalCfg0, 26:24, scratch17, 31:29); + s(EmcPmacroAutocalCfg1, 2:0, scratch18, 22:20); + s(EmcPmacroAutocalCfg1, 10:8, scratch18, 25:23); + s(EmcPmacroAutocalCfg1, 18:16, scratch18, 28:26); + s(EmcPmacroAutocalCfg1, 26:24, scratch18, 31:29); + s(EmcPmacroAutocalCfg2, 2:0, scratch19, 22:20); + s(EmcPmacroAutocalCfg2, 10:8, scratch19, 25:23); + s(EmcPmacroAutocalCfg2, 18:16, scratch19, 28:26); + s(EmcPmacroAutocalCfg2, 26:24, scratch19, 31:29); + s32(EmcCfgRsv,scratch22); + s32(EmcAutoCalConfig, scratch23); + s32(EmcAutoCalVrefSel0, scratch24); + s32(EmcPmacroBrickCtrlRfu1, scratch25); + s32(EmcPmacroBrickCtrlRfu2, scratch26); + s32(EmcPmcScratch1, scratch27); + s32(EmcPmcScratch2, scratch28); + s32(EmcPmcScratch3, scratch29); + s32(McEmemArbDaTurns, scratch30); + s(EmcFbioSpare, 31:24, scratch58, 7:0); + s(EmcFbioSpare, 23:16, scratch58, 15:8); + s(EmcFbioSpare, 15:8, scratch58, 23:16); + s(EmcFbioSpare, 7:2, scratch58, 29:24); + s(EmcFbioSpare, 0:0, scratch58, 30:30); + s(EmcDllCfg0, 29:0, scratch59, 29:0); + s(EmcPmacroDdllBypass, 11:0, scratch60, 11:0); + s(EmcPmacroDdllBypass, 27:13, scratch60, 26:12); + s(EmcPmacroDdllBypass, 31:29, scratch60, 29:27); + s(McEmemArbMisc0, 14:0, scratch61, 14:0); + s(McEmemArbMisc0, 30:16, scratch61, 29:15); + s(EmcFdpdCtrlCmd, 16:0, scratch62, 16:0); + s(EmcFdpdCtrlCmd, 31:20, scratch62, 28:17); + s(EmcAutoCalConfig2, 27:0, scratch63, 27:0); + s(EmcBurstRefreshNum, 3:0, scratch63, 31:28); + s(EmcPmacroZctrl, 27:0, scratch64, 27:0); + s(EmcTppd, 3:0, scratch64, 31:28); + s(EmcCfgDigDll, 10:0, scratch65, 10:0); + s(EmcCfgDigDll, 25:12, scratch65, 24:11); + s(EmcCfgDigDll, 27:27, scratch65, 25:25); + s(EmcCfgDigDll, 31:30, scratch65, 27:26); + s(EmcR2r, 3:0, scratch65, 31:28); + s(EmcFdpdCtrlDq, 16:0, scratch66, 16:0); + s(EmcFdpdCtrlDq, 28:20, scratch66, 25:17); + s(EmcFdpdCtrlDq, 31:30, scratch66, 27:26); + s(EmcW2w, 3:0, scratch66, 31:28); + s(EmcPmacroTxPwrd4, 13:0, scratch67, 13:0); + s(EmcPmacroTxPwrd4, 29:16, scratch67, 27:14); + s(EmcPmacroCommonPadTxCtrl, 3:0, scratch67, 31:28); + s(EmcPmacroTxPwrd5, 13:0, scratch68, 13:0); + s(EmcPmacroTxPwrd5, 29:16, scratch68, 27:14); + s(EmcPmacroDdllPwrd0, 4:0, scratch69, 4:0); + s(EmcPmacroDdllPwrd0, 12:6, scratch69, 11:5); + s(EmcPmacroDdllPwrd0, 20:14, scratch69, 18:12); + s(EmcPmacroDdllPwrd0, 28:22, scratch69, 25:19); + s(EmcPmacroDdllPwrd0, 31:30, scratch69, 27:26); + s(EmcCfg, 4:4, scratch69, 31:31); + s(EmcPmacroDdllPwrd1, 4:0, scratch70, 4:0); + s(EmcPmacroDdllPwrd1, 12:6, scratch70, 11:5); + s(EmcPmacroDdllPwrd1, 20:14, scratch70, 18:12); + s(EmcPmacroDdllPwrd1, 28:22, scratch70, 25:19); + s(EmcPmacroDdllPwrd1, 31:30, scratch70, 27:26); + s(EmcCfg, 5:5, scratch70, 31:31); + s(EmcPmacroDdllPwrd2, 4:0, scratch71, 4:0); + s(EmcPmacroDdllPwrd2, 12:6, scratch71, 11:5); + s(EmcPmacroDdllPwrd2, 20:14, scratch71, 18:12); + s(EmcPmacroDdllPwrd2, 28:22, scratch71, 25:19); + s(EmcPmacroDdllPwrd2, 31:30, scratch71, 27:26); + s(EmcFbioCfg5, 23:20, scratch71, 31:28); + s(EmcPmacroIbVrefDq_0, 6:0, scratch72, 6:0); + s(EmcPmacroIbVrefDq_0, 14:8, scratch72, 13:7); + s(EmcPmacroIbVrefDq_0, 22:16, scratch72, 20:14); + s(EmcPmacroIbVrefDq_0, 30:24, scratch72, 27:21); + s(EmcFbioCfg5, 15:13, scratch72, 30:28); + s(EmcCfg, 6:6, scratch72, 31:31); + s(EmcPmacroIbVrefDq_1, 6:0, scratch73, 6:0); + s(EmcPmacroIbVrefDq_1, 14:8, scratch73, 13:7); + s(EmcPmacroIbVrefDq_1, 22:16, scratch73, 20:14); + s(EmcPmacroIbVrefDq_1, 30:24, scratch73, 27:21); + s(EmcCfg2, 5:3, scratch73, 30:28); + s(EmcCfg, 7:7, scratch73, 31:31); + s(EmcPmacroIbVrefDqs_0, 6:0, scratch74, 6:0); + s(EmcPmacroIbVrefDqs_0, 14:8, scratch74, 13:7); + s(EmcPmacroIbVrefDqs_0, 22:16, scratch74, 20:14); + s(EmcPmacroIbVrefDqs_0, 30:24, scratch74, 27:21); + s(EmcCfg, 17:16, scratch74, 29:28); + s(EmcFbioCfg5, 1:0, scratch74, 31:30); + s(EmcPmacroIbVrefDqs_1, 6:0, scratch75, 6:0); + s(EmcPmacroIbVrefDqs_1, 14:8, scratch75, 13:7); + s(EmcPmacroIbVrefDqs_1, 22:16, scratch75, 20:14); + s(EmcPmacroIbVrefDqs_1, 30:24, scratch75, 27:21); + s(EmcFbioCfg5, 3:2, scratch75, 29:28); + s(EmcCfg2, 27:26, scratch75, 31:30); + s(EmcPmacroDdllShortCmd_0, 6:0, scratch76, 6:0); + s(EmcPmacroDdllShortCmd_0, 14:8, scratch76, 13:7); + s(EmcPmacroDdllShortCmd_0, 22:16, scratch76, 20:14); + s(EmcPmacroDdllShortCmd_0, 30:24, scratch76, 27:21); + s(EmcPmacroCmdPadTxCtrl, 3:2, scratch76, 29:28); + s(EmcPmacroCmdPadTxCtrl, 7:6, scratch76, 31:30); + s(EmcPmacroDdllShortCmd_1, 6:0, scratch77, 6:0); + s(EmcPmacroDdllShortCmd_1, 14:8, scratch77, 13:7); + s(EmcPmacroDdllShortCmd_1, 22:16, scratch77, 20:14); + s(EmcPmacroDdllShortCmd_1, 30:24, scratch77, 27:21); + s(EmcPmacroCmdPadTxCtrl, 11:10, scratch77, 29:28); + s(EmcPmacroCmdPadTxCtrl, 15:14, scratch77, 31:30); + s(EmcAutoCalChannel, 5:0, scratch78, 5:0); + s(EmcAutoCalChannel, 11:8, scratch78, 9:6); + s(EmcAutoCalChannel, 27:16, scratch78, 21:10); + s(EmcAutoCalChannel, 31:29, scratch78, 24:22); + s(EmcConfigSampleDelay, 6:0, scratch78, 31:25); + s(EmcPmacroRxTerm, 5:0, scratch79, 5:0); + s(EmcPmacroRxTerm, 13:8, scratch79, 11:6); + s(EmcPmacroRxTerm, 21:16, scratch79, 17:12); + s(EmcPmacroRxTerm, 29:24, scratch79, 23:18); + s(EmcRc, 7:0, scratch79, 31:24); + s(EmcPmacroDqTxDrv, 5:0, scratch80, 5:0); + s(EmcPmacroDqTxDrv, 13:8, scratch80, 11:6); + s(EmcPmacroDqTxDrv, 21:16, scratch80, 17:12); + s(EmcPmacroDqTxDrv, 29:24, scratch80, 23:18); + s(EmcSelDpdCtrl, 5:2, scratch80, 27:24); + s(EmcSelDpdCtrl, 8:8, scratch80, 28:28); + s(EmcSelDpdCtrl, 18:16, scratch80, 31:29); + s(EmcPmacroCaTxDrv, 5:0, scratch81, 5:0); + s(EmcPmacroCaTxDrv, 13:8, scratch81, 11:6); + s(EmcPmacroCaTxDrv, 21:16, scratch81, 17:12); + s(EmcPmacroCaTxDrv, 29:24, scratch81, 23:18); + s(EmcObdly, 5:0, scratch81, 29:24); + s(EmcObdly, 29:28, scratch81, 31:30); + s(EmcZcalInterval, 23:10, scratch82, 13:0); + s(EmcZcalInterval, 9:0, scratch82, 23:14); + s(EmcPmacroCmdRxTermMode, 1:0, scratch82, 25:24); + s(EmcPmacroCmdRxTermMode, 5:4, scratch82, 27:26); + s(EmcPmacroCmdRxTermMode, 9:8, scratch82, 29:28); + s(EmcPmacroCmdRxTermMode, 13:12, scratch82, 31:30); + s(EmcDataBrlshft0, 23:0, scratch83, 23:0); + s(EmcPmacroDataRxTermMode, 1:0, scratch83, 25:24); + s(EmcPmacroDataRxTermMode, 5:4, scratch83, 27:26); + s(EmcPmacroDataRxTermMode, 9:8, scratch83, 29:28); + s(EmcPmacroDataRxTermMode, 13:12, scratch83, 31:30); + s(EmcDataBrlshft1, 23:0, scratch84, 23:0); + s(McEmemArbTimingRc, 7:0, scratch84, 31:24); + s(EmcDqsBrlshft0, 23:0, scratch85, 23:0); + s(McEmemArbRsv, 7:0, scratch85, 31:24); + s(EmcDqsBrlshft1, 23:0, scratch86, 23:0); + s(EmcCfgPipe2, 11:0, scratch87, 11:0); + s(EmcCfgPipe2, 27:16, scratch87, 23:12); + s(EmcCfgPipe1, 11:0, scratch88, 11:0); + s(EmcCfgPipe1, 27:16, scratch88, 23:12); + s(EmcPmacroCmdCtrl0, 5:0, scratch89, 5:0); + s(EmcPmacroCmdCtrl0, 13:8, scratch89, 11:6); + s(EmcPmacroCmdCtrl0, 21:16, scratch89, 17:12); + s(EmcPmacroCmdCtrl0, 29:24, scratch89, 23:18); + s(EmcPmacroCmdCtrl1, 5:0, scratch90, 5:0); + s(EmcPmacroCmdCtrl1, 13:8, scratch90, 11:6); + s(EmcPmacroCmdCtrl1, 21:16, scratch90, 17:12); + s(EmcPmacroCmdCtrl1, 29:24, scratch90, 23:18); + s(EmcRas, 6:0, scratch90, 30:24); + s(EmcCfg, 8:8, scratch90, 31:31); + s(EmcPmacroVttgenCtrl2, 23:0, scratch91, 23:0); + s(EmcW2p, 6:0, scratch91, 30:24); + s(EmcCfg, 9:9, scratch91, 31:31); + s(EmcPmacroCmdPadRxCtrl, 2:0, scratch92, 2:0); + s(EmcPmacroCmdPadRxCtrl, 5:4, scratch92, 4:3); + s(EmcPmacroCmdPadRxCtrl, 10:8, scratch92, 7:5); + s(EmcPmacroCmdPadRxCtrl, 22:12, scratch92, 18:8); + s(EmcPmacroCmdPadRxCtrl, 28:24, scratch92, 23:19); + s(EmcQSafe, 6:0, scratch92, 30:24); + s(EmcCfg, 18:18, scratch92, 31:31); + s(EmcPmacroDataPadRxCtrl, 2:0, scratch93, 2:0); + s(EmcPmacroDataPadRxCtrl, 5:4, scratch93, 4:3); + s(EmcPmacroDataPadRxCtrl, 10:8, scratch93, 7:5); + s(EmcPmacroDataPadRxCtrl, 22:12, scratch93, 18:8); + s(EmcPmacroDataPadRxCtrl, 28:24, scratch93, 23:19); + s(EmcRdv, 6:0, scratch93, 30:24); + s(EmcCfg, 21:21, scratch93, 31:31); + s(McEmemArbDaCovers, 23:0, scratch94, 23:0); + s(EmcRw2Pden, 6:0, scratch94, 30:24); + s(EmcCfg, 22:22, scratch94, 31:31); + s(EmcPmacroCmdCtrl2, 5:0, scratch95, 5:0); + s(EmcPmacroCmdCtrl2, 13:9, scratch95, 10:6); + s(EmcPmacroCmdCtrl2, 21:16, scratch95, 16:11); + s(EmcPmacroCmdCtrl2, 29:24, scratch95, 22:17); + s(EmcRfcPb, 8:0, scratch95, 31:23); + s(EmcPmacroQuseDdllRank0_0, 10:0, scratch96, 10:0); + s(EmcPmacroQuseDdllRank0_0, 26:16, scratch96, 21:11); + s(EmcCfgUpdate, 2:0, scratch96, 24:22); + s(EmcCfgUpdate, 10:8, scratch96, 27:25); + s(EmcCfgUpdate, 31:28, scratch96, 31:28); + s(EmcPmacroQuseDdllRank0_1, 10:0, scratch97, 10:0); + s(EmcPmacroQuseDdllRank0_1, 26:16, scratch97, 21:11); + s(EmcRfc, 9:0, scratch97, 31:22); + s(EmcPmacroQuseDdllRank0_2, 10:0, scratch98, 10:0); + s(EmcPmacroQuseDdllRank0_2, 26:16, scratch98, 21:11); + s(EmcTxsr, 9:0, scratch98, 31:22); + s(EmcPmacroQuseDdllRank0_3, 10:0, scratch99, 10:0); + s(EmcPmacroQuseDdllRank0_3, 26:16, scratch99, 21:11); + s(EmcMc2EmcQ, 2:0, scratch99, 24:22); + s(EmcMc2EmcQ, 10:8, scratch99, 27:25); + s(EmcMc2EmcQ, 27:24, scratch99, 31:28); + s(EmcPmacroQuseDdllRank0_4, 10:0, scratch100, 10:0); + s(EmcPmacroQuseDdllRank0_4, 26:16, scratch100, 21:11); + s(McEmemArbRing1Throttle, 4:0, scratch100, 26:22); + s(McEmemArbRing1Throttle, 20:16, scratch100, 31:27); + s(EmcPmacroQuseDdllRank0_5, 10:0, scratch101, 10:0); + s(EmcPmacroQuseDdllRank0_5, 26:16, scratch101, 21:11); + s(EmcPmacroQuseDdllRank1_0, 10:0, scratch102, 10:0); + s(EmcPmacroQuseDdllRank1_0, 26:16, scratch102, 21:11); + s(EmcAr2Pden, 8:0, scratch102, 30:22); + s(EmcCfg, 23:23, scratch102, 31:31); + s(EmcPmacroQuseDdllRank1_1, 10:0, scratch103, 10:0); + s(EmcPmacroQuseDdllRank1_1, 26:16, scratch103, 21:11); + s(EmcRfcSlr, 8:0, scratch103, 30:22); + s(EmcCfg, 24:24, scratch103, 31:31); + s(EmcPmacroQuseDdllRank1_2, 10:0, scratch104, 10:0); + s(EmcPmacroQuseDdllRank1_2, 26:16, scratch104, 21:11); + s(EmcIbdly, 6:0, scratch104, 28:22); + s(EmcIbdly, 29:28, scratch104, 30:29); + s(EmcCfg, 25:25, scratch104, 31:31); + s(EmcPmacroQuseDdllRank1_3, 10:0, scratch105, 10:0); + s(EmcPmacroQuseDdllRank1_3, 26:16, scratch105, 21:11); + s(McEmemArbTimingRFCPB, 8:0, scratch105, 30:22); + s(EmcCfg, 26:26, scratch105, 31:31); + s(EmcPmacroQuseDdllRank1_4, 10:0, scratch106, 10:0); + s(EmcPmacroQuseDdllRank1_4, 26:16, scratch106, 21:11); + s(EmcTfaw, 6:0, scratch106, 28:22); + s(EmcPmacroDataPadTxCtrl, 3:2, scratch106, 30:29); + s(EmcCfg, 28:28, scratch106, 31:31); + s(EmcPmacroQuseDdllRank1_5, 10:0, scratch107, 10:0); + s(EmcPmacroQuseDdllRank1_5, 26:16, scratch107, 21:11); + s(EmcTClkStable, 6:0, scratch107, 28:22); + s(EmcPmacroDataPadTxCtrl, 7:6, scratch107, 30:29); + s(EmcCfg, 29:29, scratch107, 31:31); + s(EmcPmacroObDdllLongDqRank0_0, 10:0, scratch108, 10:0); + s(EmcPmacroObDdllLongDqRank0_0, 26:16, scratch108, 21:11); + s(EmcPdex2Mrr, 6:0, scratch108, 28:22); + s(EmcPmacroDataPadTxCtrl, 11:10, scratch108, 30:29); + s(EmcCfg, 30:30, scratch108, 31:31); + s(EmcPmacroObDdllLongDqRank0_1, 10:0, scratch109, 10:0); + s(EmcPmacroObDdllLongDqRank0_1, 26:16, scratch109, 21:11); + s(EmcRdvMask, 6:0, scratch109, 28:22); + s(EmcPmacroDataPadTxCtrl, 15:14, scratch109, 30:29); + s(EmcCfg, 31:31, scratch109, 31:31); + s(EmcPmacroObDdllLongDqRank0_2, 10:0, scratch110, 10:0); + s(EmcPmacroObDdllLongDqRank0_2, 26:16, scratch110, 21:11); + s(EmcRdvEarlyMask, 6:0, scratch110, 28:22); + s(EmcFbioCfg5, 4:4, scratch110, 29:29); + s(EmcFbioCfg5, 8:8, scratch110, 30:30); + s(EmcFbioCfg5, 10:10, scratch110, 31:31); + s(EmcPmacroObDdllLongDqRank0_3, 10:0, scratch111, 10:0); + s(EmcPmacroObDdllLongDqRank0_3, 26:16, scratch111, 21:11); + s(EmcRdvEarly, 6:0, scratch111, 28:22); + s(EmcFbioCfg5, 12:12, scratch111, 29:29); + s(EmcFbioCfg5, 25:24, scratch111, 31:30); + s(EmcPmacroObDdllLongDqRank0_4, 10:0, scratch112, 10:0); + s(EmcPmacroObDdllLongDqRank0_4, 26:16, scratch112, 21:11); + s(EmcPmacroDdllShortCmd_2, 6:0, scratch112, 28:22); + s(EmcFbioCfg5, 28:26, scratch112, 31:29); + s(EmcPmacroObDdllLongDqRank0_5, 10:0, scratch113, 10:0); + s(EmcPmacroObDdllLongDqRank0_5, 26:16, scratch113, 21:11); + s(McEmemArbTimingRp, 6:0, scratch113, 28:22); + s(EmcFbioCfg5, 31:30, scratch113, 30:29); + s(EmcCfg2, 0:0, scratch113, 31:31); + s(EmcPmacroObDdllLongDqRank1_0, 10:0, scratch114, 10:0); + s(EmcPmacroObDdllLongDqRank1_0, 26:16, scratch114, 21:11); + s(McEmemArbTimingRas, 6:0, scratch114, 28:22); + s(EmcCfg2, 2:1, scratch114, 30:29); + s(EmcCfg2, 7:7, scratch114, 31:31); + s(EmcPmacroObDdllLongDqRank1_1, 10:0, scratch115, 10:0); + s(EmcPmacroObDdllLongDqRank1_1, 26:16, scratch115, 21:11); + s(McEmemArbTimingFaw, 6:0, scratch115, 28:22); + s(EmcCfg2, 11:10, scratch115, 30:29); + s(EmcCfg2, 14:14, scratch115, 31:31); + s(EmcPmacroObDdllLongDqRank1_2, 10:0, scratch123, 10:0); + s(EmcPmacroObDdllLongDqRank1_2, 26:16, scratch123, 21:11); + s(McEmemArbTimingRap2Pre, 6:0, scratch123, 28:22); + s(EmcCfg2, 16:15, scratch123, 30:29); + s(EmcCfg2, 20:20, scratch123, 31:31); + s(EmcPmacroObDdllLongDqRank1_3, 10:0, scratch124, 10:0); + s(EmcPmacroObDdllLongDqRank1_3, 26:16, scratch124, 21:11); + s(McEmemArbTimingWap2Pre, 6:0, scratch124, 28:22); + s(EmcCfg2, 24:22, scratch124, 31:29); + s(EmcPmacroObDdllLongDqRank1_4, 10:0, scratch125, 10:0); + s(EmcPmacroObDdllLongDqRank1_4, 26:16, scratch125, 21:11); + s(McEmemArbTimingR2W, 6:0, scratch125, 28:22); + s(EmcCfg2, 25:25, scratch125, 29:29); + s(EmcCfg2, 29:28, scratch125, 31:30); + s(EmcPmacroObDdllLongDqRank1_5, 10:0, scratch126, 10:0); + s(EmcPmacroObDdllLongDqRank1_5, 26:16, scratch126, 21:11); + s(McEmemArbTimingW2R, 6:0, scratch126, 28:22); + s(EmcCfg2, 31:30, scratch126, 30:29); + s(EmcCfgPipe, 0:0, scratch126, 31:31); + s(EmcPmacroObDdllLongDqsRank0_0, 10:0, scratch127, 10:0); + s(EmcPmacroObDdllLongDqsRank0_0, 26:16, scratch127, 21:11); + s(EmcRp, 5:0, scratch127, 27:22); + s(EmcCfgPipe, 4:1, scratch127, 31:28); + s(EmcPmacroObDdllLongDqsRank0_1, 10:0, scratch128, 10:0); + s(EmcPmacroObDdllLongDqsRank0_1, 26:16, scratch128, 21:11); + s(EmcR2w, 5:0, scratch128, 27:22); + s(EmcCfgPipe, 8:5, scratch128, 31:28); + s(EmcPmacroObDdllLongDqsRank0_2, 10:0, scratch129, 10:0); + s(EmcPmacroObDdllLongDqsRank0_2, 26:16, scratch129, 21:11); + s(EmcW2r, 5:0, scratch129, 27:22); + s(EmcCfgPipe, 11:9, scratch129, 30:28); + s(EmcCfgPipe, 16:16, scratch129, 31:31); + s(EmcPmacroObDdllLongDqsRank0_3, 10:0, scratch130, 10:0); + s(EmcPmacroObDdllLongDqsRank0_3, 26:16, scratch130, 21:11); + s(EmcR2p, 5:0, scratch130, 27:22); + s(EmcCfgPipe, 20:17, scratch130, 31:28); + s(EmcPmacroObDdllLongDqsRank0_4, 10:0, scratch131, 10:0); + s(EmcPmacroObDdllLongDqsRank0_4, 26:16, scratch131, 21:11); + s(EmcCcdmw, 5:0, scratch131, 27:22); + s(EmcCfgPipe, 24:21, scratch131, 31:28); + s(EmcPmacroObDdllLongDqsRank0_5, 10:0, scratch132, 10:0); + s(EmcPmacroObDdllLongDqsRank0_5, 26:16, scratch132, 21:11); + s(EmcRdRcd, 5:0, scratch132, 27:22); + s(EmcCfgPipe, 27:25, scratch132, 30:28); + s(EmcPmacroTxPwrd0, 0:0, scratch132, 31:31); + s(EmcPmacroObDdllLongDqsRank1_0, 10:0, scratch133, 10:0); + s(EmcPmacroObDdllLongDqsRank1_0, 26:16, scratch133, 21:11); + s(EmcWrRcd, 5:0, scratch133, 27:22); + s(EmcPmacroTxPwrd0, 4:1, scratch133, 31:28); + s(EmcPmacroObDdllLongDqsRank1_1, 10:0, scratch134, 10:0); + s(EmcPmacroObDdllLongDqsRank1_1, 26:16, scratch134, 21:11); + s(EmcWdv, 5:0, scratch134, 27:22); + s(EmcPmacroTxPwrd0, 8:5, scratch134, 31:28); + s(EmcPmacroObDdllLongDqsRank1_2, 10:0, scratch135, 10:0); + s(EmcPmacroObDdllLongDqsRank1_2, 26:16, scratch135, 21:11); + s(EmcQUse, 5:0, scratch135, 27:22); + s(EmcPmacroTxPwrd0, 12:9, scratch135, 31:28); + s(EmcPmacroObDdllLongDqsRank1_3, 10:0, scratch136, 10:0); + s(EmcPmacroObDdllLongDqsRank1_3, 26:16, scratch136, 21:11); + s(EmcPdEx2Wr, 5:0, scratch136, 27:22); + s(EmcPmacroTxPwrd0, 13:13, scratch136, 28:28); + s(EmcPmacroTxPwrd0, 18:16, scratch136, 31:29); + s(EmcPmacroObDdllLongDqsRank1_4, 10:0, scratch137, 10:0); + s(EmcPmacroObDdllLongDqsRank1_4, 26:16, scratch137, 21:11); + s(EmcPdEx2Rd, 5:0, scratch137, 27:22); + s(EmcPmacroTxPwrd0, 22:19, scratch137, 31:28); + s(EmcPmacroObDdllLongDqsRank1_5, 10:0, scratch138, 10:0); + s(EmcPmacroObDdllLongDqsRank1_5, 26:16, scratch138, 21:11); + s(EmcPdex2Cke, 5:0, scratch138, 27:22); + s(EmcPmacroTxPwrd0, 26:23, scratch138, 31:28); + s(EmcPmacroIbDdllLongDqsRank0_0, 10:0, scratch139, 10:0); + s(EmcPmacroIbDdllLongDqsRank0_0, 26:16, scratch139, 21:11); + s(EmcPChg2Pden, 5:0, scratch139, 27:22); + s(EmcPmacroTxPwrd0, 29:27, scratch139, 30:28); + s(EmcPmacroTxPwrd1, 0:0, scratch139, 31:31); + s(EmcPmacroIbDdllLongDqsRank0_1, 10:0, scratch140, 10:0); + s(EmcPmacroIbDdllLongDqsRank0_1, 26:16, scratch140, 21:11); + s(EmcAct2Pden, 5:0, scratch140, 27:22); + s(EmcPmacroTxPwrd1, 4:1, scratch140, 31:28); + s(EmcPmacroIbDdllLongDqsRank0_2, 10:0, scratch141, 10:0); + s(EmcPmacroIbDdllLongDqsRank0_2, 26:16, scratch141, 21:11); + s(EmcCke2Pden, 5:0, scratch141, 27:22); + s(EmcPmacroTxPwrd1, 8:5, scratch141, 31:28); + s(EmcPmacroIbDdllLongDqsRank0_3, 10:0, scratch142, 10:0); + s(EmcPmacroIbDdllLongDqsRank0_3, 26:16, scratch142, 21:11); + s(EmcTcke, 5:0, scratch142, 27:22); + s(EmcPmacroTxPwrd1, 12:9, scratch142, 31:28); + s(EmcPmacroIbDdllLongDqsRank1_0, 10:0, scratch143, 10:0); + s(EmcPmacroIbDdllLongDqsRank1_0, 26:16, scratch143, 21:11); + s(EmcTrpab, 5:0, scratch143, 27:22); + s(EmcPmacroTxPwrd1, 13:13, scratch143, 28:28); + s(EmcPmacroTxPwrd1, 18:16, scratch143, 31:29); + s(EmcPmacroIbDdllLongDqsRank1_1, 10:0, scratch144, 10:0); + s(EmcPmacroIbDdllLongDqsRank1_1, 26:16, scratch144, 21:11); + s(EmcClkenOverride, 3:1, scratch144, 24:22); + s(EmcClkenOverride, 8:6, scratch144, 27:25); + s(EmcPmacroTxPwrd1, 22:19, scratch144, 31:28); + s(EmcPmacroIbDdllLongDqsRank1_2, 10:0, scratch145, 10:0); + s(EmcPmacroIbDdllLongDqsRank1_2, 26:16, scratch145, 21:11); + s(EmcEInput, 5:0, scratch145, 27:22); + s(EmcPmacroTxPwrd1, 26:23, scratch145, 31:28); + s(EmcPmacroIbDdllLongDqsRank1_3, 10:0, scratch146, 10:0); + s(EmcPmacroIbDdllLongDqsRank1_3, 26:16, scratch146, 21:11); + s(EmcEInputDuration, 5:0, scratch146, 27:22); + s(EmcPmacroTxPwrd1, 29:27, scratch146, 30:28); + s(EmcPmacroTxPwrd2, 0:0, scratch146, 31:31); + s(EmcPmacroDdllLongCmd_0, 10:0, scratch147, 10:0); + s(EmcPmacroDdllLongCmd_0, 26:16, scratch147, 21:11); + s(EmcPutermExtra, 5:0, scratch147, 27:22); + s(EmcPmacroTxPwrd2, 4:1, scratch147, 31:28); + s(EmcPmacroDdllLongCmd_1, 10:0, scratch148, 10:0); + s(EmcPmacroDdllLongCmd_1, 26:16, scratch148, 21:11); + s(EmcTckesr, 5:0, scratch148, 27:22); + s(EmcPmacroTxPwrd2, 8:5, scratch148, 31:28); + s(EmcPmacroDdllLongCmd_2, 10:0, scratch149, 10:0); + s(EmcPmacroDdllLongCmd_2, 26:16, scratch149, 21:11); + s(EmcTpd, 5:0, scratch149, 27:22); + s(EmcPmacroTxPwrd2, 12:9, scratch149, 31:28); + s(EmcPmacroDdllLongCmd_3, 10:0, scratch150, 10:0); + s(EmcPmacroDdllLongCmd_3, 26:16, scratch150, 21:11); + s(EmcWdvMask, 5:0, scratch150, 27:22); + s(EmcPmacroTxPwrd2, 13:13, scratch150, 28:28); + s(EmcPmacroTxPwrd2, 18:16, scratch150, 31:29); + s(McEmemArbCfg, 8:0, scratch151, 8:0); + s(McEmemArbCfg, 20:16, scratch151, 13:9); + s(McEmemArbCfg, 31:24, scratch151, 21:14); + s(EmcWdvChk, 5:0, scratch151, 27:22); + s(EmcPmacroTxPwrd2, 22:19, scratch151, 31:28); + s(McEmemArbMisc1, 12:0, scratch152, 12:0); + s(McEmemArbMisc1, 25:21, scratch152, 17:13); + s(McEmemArbMisc1, 31:28, scratch152, 21:18); + s(EmcCmdBrlshft0, 5:0, scratch152, 27:22); + s(EmcPmacroTxPwrd2, 26:23, scratch152, 31:28); + s(EmcMrsWaitCnt2, 9:0, scratch153, 9:0); + s(EmcMrsWaitCnt2, 26:16, scratch153, 20:10); + s(EmcPmacroIbRxrt, 10:0, scratch153, 31:21); + s(EmcMrsWaitCnt, 9:0, scratch154, 9:0); + s(EmcMrsWaitCnt, 26:16, scratch154, 20:10); + s(EmcPmacroDdllLongCmd_4, 10:0, scratch154, 31:21); + s(EmcAutoCalInterval, 20:0, scratch155, 20:0); + s(McEmemArbOutstandingReq, 8:0, scratch155, 29:21); + s(McEmemArbOutstandingReq, 31:30, scratch155, 31:30); + s(McEmemArbRefpbHpCtrl, 6:0, scratch156, 6:0); + s(McEmemArbRefpbHpCtrl, 14:8, scratch156, 13:7); + s(McEmemArbRefpbHpCtrl, 22:16, scratch156, 20:14); + s(EmcCmdBrlshft1, 5:0, scratch156, 26:21); + s(EmcRrd, 4:0, scratch156, 31:27); + s(EmcQuseBrlshft0, 19:0, scratch157, 19:0); + s(EmcFbioCfg8, 27:16, scratch157, 31:20); + s(EmcQuseBrlshft1, 19:0, scratch158, 19:0); + s(EmcTxsrDll, 11:0, scratch158, 31:20); + s(EmcQuseBrlshft2, 19:0, scratch159, 19:0); + s(EmcTxdsrvttgen, 11:0, scratch159, 31:20); + s(EmcQuseBrlshft3, 19:0, scratch160, 19:0); + s(EmcPmacroVttgenCtrl0, 3:0, scratch160, 23:20); + s(EmcPmacroVttgenCtrl0, 11:8, scratch160, 27:24); + s(EmcPmacroVttgenCtrl0, 19:16, scratch160, 31:28); + s(EmcPmacroVttgenCtrl1, 19:0, scratch161, 19:0); + s(EmcCmdBrlshft2, 5:0, scratch161, 25:20); + s(EmcCmdBrlshft3, 5:0, scratch161, 31:26); + s(EmcAutoCalConfig3, 5:0, scratch162, 5:0); + s(EmcAutoCalConfig3, 13:8, scratch162, 11:6); + s(EmcAutoCalConfig3, 18:16, scratch162, 14:12); + s(EmcAutoCalConfig3, 22:20, scratch162, 17:15); + s(EmcTRefBw, 13:0, scratch162, 31:18); + s(EmcAutoCalConfig4, 5:0, scratch163, 5:0); + s(EmcAutoCalConfig4, 13:8, scratch163, 11:6); + s(EmcAutoCalConfig4, 18:16, scratch163, 14:12); + s(EmcAutoCalConfig4, 22:20, scratch163, 17:15); + s(EmcQpop, 6:0, scratch163, 24:18); + s(EmcQpop, 22:16, scratch163, 31:25); + s(EmcAutoCalConfig5, 5:0, scratch164, 5:0); + s(EmcAutoCalConfig5, 13:8, scratch164, 11:6); + s(EmcAutoCalConfig5, 18:16, scratch164, 14:12); + s(EmcAutoCalConfig5, 22:20, scratch164, 17:15); + s(EmcPmacroAutocalCfgCommon, 5:0, scratch164, 23:18); + s(EmcPmacroAutocalCfgCommon, 13:8, scratch164, 29:24); + s(EmcPmacroAutocalCfgCommon, 16:16, scratch164, 30:30); + s(EmcPmacroTxPwrd2, 27:27, scratch164, 31:31); + s(EmcAutoCalConfig6, 5:0, scratch165, 5:0); + s(EmcAutoCalConfig6, 13:8, scratch165, 11:6); + s(EmcAutoCalConfig6, 18:16, scratch165, 14:12); + s(EmcAutoCalConfig6, 22:20, scratch165, 17:15); + s(EmcWev, 5:0, scratch165, 23:18); + s(EmcWsv, 5:0, scratch165, 29:24); + s(EmcPmacroTxPwrd2, 29:28, scratch165, 31:30); + s(EmcAutoCalConfig7, 5:0, scratch166, 5:0); + s(EmcAutoCalConfig7, 13:8, scratch166, 11:6); + s(EmcAutoCalConfig7, 18:16, scratch166, 14:12); + s(EmcAutoCalConfig7, 22:20, scratch166, 17:15); + s(EmcCfg3, 2:0, scratch166, 20:18); + s(EmcCfg3, 6:4, scratch166, 23:21); + s(EmcQuseWidth, 3:0, scratch166, 27:24); + s(EmcQuseWidth, 29:28, scratch166, 29:28); + s(EmcPmacroTxPwrd3, 1:0, scratch166, 31:30); + s(EmcAutoCalConfig8, 5:0, scratch167, 5:0); + s(EmcAutoCalConfig8, 13:8, scratch167, 11:6); + s(EmcAutoCalConfig8, 18:16, scratch167, 14:12); + s(EmcAutoCalConfig8, 22:20, scratch167, 17:15); + s(EmcPmacroBgBiasCtrl0, 2:0, scratch167, 20:18); + s(EmcPmacroBgBiasCtrl0, 6:4, scratch167, 23:21); + s(McEmemArbTimingRcd, 5:0, scratch167, 29:24); + s(EmcPmacroTxPwrd3, 3:2, scratch167, 31:30); + s(EmcXm2CompPadCtrl2, 17:0, scratch168, 17:0); + s(McEmemArbTimingCcdmw, 5:0, scratch168, 23:18); + s(McEmemArbOverride, 27:27, scratch168, 24:24); + s(McEmemArbOverride, 26:26, scratch168, 25:25); + s(McEmemArbOverride, 16:16, scratch168, 26:26); + s(McEmemArbOverride, 10:10, scratch168, 27:27); + s(McEmemArbOverride, 4:4, scratch168, 28:28); + s(McEmemArbOverride, 3:3, scratch168, 29:29); + s(EmcPmacroTxPwrd3, 5:4, scratch168, 31:30); + s(EmcXm2CompPadCtrl3, 17:0, scratch169, 17:0); + s(EmcRext, 4:0, scratch169, 22:18); + s(EmcTClkStop, 4:0, scratch169, 27:23); + s(EmcPmacroTxPwrd3, 9:6, scratch169, 31:28); + s(EmcZcalWaitCnt, 10:0, scratch170, 10:0); + s(EmcZcalWaitCnt, 21:16, scratch170, 16:11); + s(EmcZcalWaitCnt, 31:31, scratch170, 17:17); + s(EmcWext, 4:0, scratch170, 22:18); + s(EmcRefctrl2, 0:0, scratch170, 23:23); + s(EmcRefctrl2, 26:24, scratch170, 26:24); + s(EmcRefctrl2, 31:31, scratch170, 27:27); + s(EmcPmacroTxPwrd3, 13:10, scratch170, 31:28); + s(EmcZcalMrwCmd, 7:0, scratch171, 7:0); + s(EmcZcalMrwCmd, 23:16, scratch171, 15:8); + s(EmcZcalMrwCmd, 31:30, scratch171, 17:16); + s(EmcWeDuration, 4:0, scratch171, 22:18); + s(EmcWsDuration, 4:0, scratch171, 27:23); + s(EmcPmacroTxPwrd3, 19:16, scratch171, 31:28); + s(EmcSwizzleRank0Byte0, 2:0, scratch172, 2:0); + s(EmcSwizzleRank0Byte0, 6:4, scratch172, 5:3); + s(EmcSwizzleRank0Byte0, 10:8, scratch172, 8:6); + s(EmcSwizzleRank0Byte0, 14:12, scratch172, 11:9); + s(EmcSwizzleRank0Byte0, 18:16, scratch172, 14:12); + s(EmcSwizzleRank0Byte0, 22:20, scratch172, 17:15); + s(EmcPutermWidth, 31:31, scratch172, 18:18); + s(EmcPutermWidth, 3:0, scratch172, 22:19); + s(McEmemArbTimingRrd, 4:0, scratch172, 27:23); + s(EmcPmacroTxPwrd3, 23:20, scratch172, 31:28); + s(EmcSwizzleRank0Byte1, 2:0, scratch173, 2:0); + s(EmcSwizzleRank0Byte1, 6:4, scratch173, 5:3); + s(EmcSwizzleRank0Byte1, 10:8, scratch173, 8:6); + s(EmcSwizzleRank0Byte1, 14:12, scratch173, 11:9); + s(EmcSwizzleRank0Byte1, 18:16, scratch173, 14:12); + s(EmcSwizzleRank0Byte1, 22:20, scratch173, 17:15); + s(McEmemArbTimingR2R, 4:0, scratch173, 22:18); + s(McEmemArbTimingW2W, 4:0, scratch173, 27:23); + s(EmcPmacroTxPwrd3, 27:24, scratch173, 31:28); + s(EmcSwizzleRank0Byte2, 2:0, scratch174, 2:0); + s(EmcSwizzleRank0Byte2, 6:4, scratch174, 5:3); + s(EmcSwizzleRank0Byte2, 10:8, scratch174, 8:6); + s(EmcSwizzleRank0Byte2, 14:12, scratch174, 11:9); + s(EmcSwizzleRank0Byte2, 18:16, scratch174, 14:12); + s(EmcSwizzleRank0Byte2, 22:20, scratch174, 17:15); + s(EmcPmacroTxPwrd3, 29:28, scratch174, 19:18); + s(EmcPmacroTxSelClkSrc0, 11:0, scratch174, 31:20); + s(EmcSwizzleRank0Byte3, 2:0, scratch175, 2:0); + s(EmcSwizzleRank0Byte3, 6:4, scratch175, 5:3); + s(EmcSwizzleRank0Byte3, 10:8, scratch175, 8:6); + s(EmcSwizzleRank0Byte3, 14:12, scratch175, 11:9); + s(EmcSwizzleRank0Byte3, 18:16, scratch175, 14:12); + s(EmcSwizzleRank0Byte3, 22:20, scratch175, 17:15); + s(EmcPmacroTxSelClkSrc0, 27:16, scratch175, 29:18); + s(EmcPmacroTxSelClkSrc1, 1:0, scratch175, 31:30); + s(EmcSwizzleRank1Byte0, 2:0, scratch176, 2:0); + s(EmcSwizzleRank1Byte0, 6:4, scratch176, 5:3); + s(EmcSwizzleRank1Byte0, 10:8, scratch176, 8:6); + s(EmcSwizzleRank1Byte0, 14:12, scratch176, 11:9); + s(EmcSwizzleRank1Byte0, 18:16, scratch176, 14:12); + s(EmcSwizzleRank1Byte0, 22:20, scratch176, 17:15); + s(EmcPmacroTxSelClkSrc1, 11:2, scratch176, 27:18); + s(EmcPmacroTxSelClkSrc1, 19:16, scratch176, 31:28); + s(EmcSwizzleRank1Byte1, 2:0, scratch177, 2:0); + s(EmcSwizzleRank1Byte1, 6:4, scratch177, 5:3); + s(EmcSwizzleRank1Byte1, 10:8, scratch177, 8:6); + s(EmcSwizzleRank1Byte1, 14:12, scratch177, 11:9); + s(EmcSwizzleRank1Byte1, 18:16, scratch177, 14:12); + s(EmcSwizzleRank1Byte1, 22:20, scratch177, 17:15); + s(EmcPmacroTxSelClkSrc1, 27:20, scratch177, 25:18); + s(EmcPmacroTxSelClkSrc3, 5:0, scratch177, 31:26); + s(EmcSwizzleRank1Byte2, 2:0, scratch178, 2:0); + s(EmcSwizzleRank1Byte2, 6:4, scratch178, 5:3); + s(EmcSwizzleRank1Byte2, 10:8, scratch178, 8:6); + s(EmcSwizzleRank1Byte2, 14:12, scratch178, 11:9); + s(EmcSwizzleRank1Byte2, 18:16, scratch178, 14:12); + s(EmcSwizzleRank1Byte2, 22:20, scratch178, 17:15); + s(EmcPmacroTxSelClkSrc3, 11:6, scratch178, 23:18); + s(EmcPmacroTxSelClkSrc3, 23:16, scratch178, 31:24); + s(EmcSwizzleRank1Byte3, 2:0, scratch179, 2:0); + s(EmcSwizzleRank1Byte3, 6:4, scratch179, 5:3); + s(EmcSwizzleRank1Byte3, 10:8, scratch179, 8:6); + s(EmcSwizzleRank1Byte3, 14:12, scratch179, 11:9); + s(EmcSwizzleRank1Byte3, 18:16, scratch179, 14:12); + s(EmcSwizzleRank1Byte3, 22:20, scratch179, 17:15); + s(EmcPmacroTxSelClkSrc3, 27:24, scratch179, 21:18); + s(EmcPmacroTxSelClkSrc2, 9:0, scratch179, 31:22); + s(EmcPmacroCmdBrickCtrlFdpd, 17:0, scratch180, 17:0); + s(EmcPmacroTxSelClkSrc2, 11:10, scratch180, 19:18); + s(EmcPmacroTxSelClkSrc2, 27:16, scratch180, 31:20); + s(EmcPmacroDataBrickCtrlFdpd, 17:0, scratch181, 17:0); + s(EmcPmacroTxSelClkSrc4, 11:0, scratch181, 29:18); + s(EmcPmacroTxSelClkSrc4, 17:16, scratch181, 31:30); + s(EmcFbioCfg7, 16:0, scratch182, 16:0); + s(McEmemArbRefpbBankCtrl, 6:0, scratch182, 23:17); + s(McEmemArbRefpbBankCtrl, 14:8, scratch182, 30:24); + s(McEmemArbRefpbBankCtrl, 31:31, scratch182, 31:31); + s(EmcDynSelfRefControl, 15:0, scratch183, 15:0); + s(EmcDynSelfRefControl, 31:31, scratch183, 16:16); + s(EmcPmacroTxSelClkSrc4, 27:18, scratch183, 26:17); + s(EmcPmacroTxSelClkSrc5, 4:0, scratch183, 31:27); + s(EmcDllCfg1, 16:0, scratch184, 16:0); + s(EmcPmacroTxSelClkSrc5, 11:5, scratch184, 23:17); + s(EmcPmacroTxSelClkSrc5, 23:16, scratch184, 31:24); + s(EmcPmacroPadCfgCtrl, 1:0, scratch185, 1:0); + s(EmcPmacroPadCfgCtrl, 6:5, scratch185, 3:2); + s(EmcPmacroPadCfgCtrl, 11:9, scratch185, 6:4); + s(EmcPmacroPadCfgCtrl, 13:13, scratch185, 7:7); + s(EmcPmacroPadCfgCtrl, 17:16, scratch185, 9:8); + s(EmcPmacroPadCfgCtrl, 21:20, scratch185, 11:10); + s(EmcPmacroPadCfgCtrl, 25:24, scratch185, 13:12); + s(EmcPmacroPadCfgCtrl, 30:28, scratch185, 16:14); + s(EmcPmacroTxSelClkSrc5, 27:24, scratch185, 20:17); + s(EmcPmacroCmdPadTxCtrl, 1:0, scratch185, 22:21); + s(EmcPmacroCmdPadTxCtrl, 5:4, scratch185, 24:23); + s(EmcPmacroCmdPadTxCtrl, 9:8, scratch185, 26:25); + s(EmcPmacroCmdPadTxCtrl, 13:12, scratch185, 28:27); + s(EmcPmacroCmdPadTxCtrl, 16:16, scratch185, 29:29); + s(EmcPmacroCmdPadTxCtrl, 21:20, scratch185, 31:30); + s(EmcRefresh, 15:0, scratch186, 15:0); + s(EmcCmdQ, 4:0, scratch186, 20:16); + s(EmcCmdQ, 10:8, scratch186, 23:21); + s(EmcCmdQ, 14:12, scratch186, 26:24); + s(EmcCmdQ, 28:24, scratch186, 31:27); + s(EmcAcpdControl, 15:0, scratch187, 15:0); + s(EmcAutoCalVrefSel1, 15:0, scratch187, 31:16); + s(EmcXm2CompPadCtrl, 1:0, scratch188, 1:0); + s(EmcXm2CompPadCtrl, 6:3, scratch188, 5:2); + s(EmcXm2CompPadCtrl, 9:9, scratch188, 6:6); + s(EmcXm2CompPadCtrl, 19:11, scratch188, 15:7); + s(EmcCfgDigDllPeriod, 15:0, scratch188, 31:16); + s(EmcCfgDigDll_1, 15:0, scratch189, 15:0); + s(EmcPreRefreshReqCnt, 15:0, scratch189, 31:16); + s(EmcPmacroCmdPadTxCtrl, 27:24, scratch190, 19:16); + s(EmcPmacroDataPadTxCtrl, 1:0, scratch190, 21:20); + s(EmcPmacroDataPadTxCtrl, 5:4, scratch190, 23:22); + s(EmcPmacroDataPadTxCtrl, 9:8, scratch190, 25:24); + s(EmcPmacroDataPadTxCtrl, 13:12, scratch190, 27:26); + s(EmcPmacroDataPadTxCtrl, 16:16, scratch190, 28:28); + s(EmcPmacroDataPadTxCtrl, 21:20, scratch190, 30:29); + s(EmcPmacroDataPadTxCtrl, 24:24, scratch190, 31:31); + s(EmcPmacroDataPadTxCtrl, 27:25, scratch191, 2:0); + + s(EmcPinGpio, 1:0, scratch8, 31:30); + s(EmcPinGpioEn, 1:0, scratch9, 31:30); + s(EmcDevSelect, 1:0, scratch10, 31:30); + s(EmcZcalWarmColdBootEnables, 1:0, scratch11, 31:30); + s(EmcCfgDigDllPeriodWarmBoot, 1:0, scratch12, 31:30); + s32(EmcBctSpare13, scratch31); + s32(EmcBctSpare12, scratch32); + s32(EmcBctSpare7, scratch33); + s32(EmcBctSpare6, scratch40); + s32(EmcBctSpare5, scratch42); + s32(EmcBctSpare4, scratch44); + s32(EmcBctSpare3, scratch45); + s32(EmcBctSpare2, scratch46); + s32(EmcBctSpare1, scratch47); + s32(EmcBctSpare0, scratch48); + s32(EmcBctSpare9, scratch50); + s32(EmcBctSpare8, scratch51); + s32(BootRomPatchData, scratch56); + s32(BootRomPatchControl, scratch57); + s(McClkenOverrideAllWarmBoot, 0:0, scratch58, 31:31); + s(EmcClkenOverrideAllWarmBoot, 0:0, scratch59, 30:30); + s(EmcMrsWarmBootEnable, 0:0, scratch59, 31:31); + s(ClearClk2Mc1, 0:0, scratch60, 30:30); + s(EmcWarmBootExtraModeRegWriteEnable, 0:0, scratch60, 31:31); + s(ClkRstControllerPllmMisc2OverrideEnable, 0:0, scratch61, 30:30); + s(EmcDbgWriteMux, 0:0, scratch61, 31:31); + s(EmcExtraRefreshNum, 2:0, scratch62, 31:29); + s(PmcIoDpd3ReqWait, 2:0, scratch68, 30:28); + s(AhbArbitrationXbarCtrlMemInitDone, 0:0, scratch68, 31:31); + s(MemoryType, 2:0, scratch69, 30:28); + s(PmcIoDpd4ReqWait, 2:0, scratch70, 30:28); + s(EmcTimingControlWait, 7:0, scratch86, 31:24); + s(EmcZcalWarmBootWait, 7:0, scratch87, 31:24); + s(WarmBootWait, 7:0, scratch88, 31:24); + s(EmcPinProgramWait, 7:0, scratch89, 31:24); + s(EmcAutoCalWait, 9:0, scratch101, 31:22); + s(SwizzleRankByteEncode, 15:0, scratch190, 15:0); + + switch (params->MemoryType) { + case NvBootMemoryType_LpDdr2: + case NvBootMemoryType_LpDdr4: + s(EmcMrwLpddr2ZcalWarmBoot, 23:16, scratch5, 7:0); + s(EmcMrwLpddr2ZcalWarmBoot, 7:0, scratch5, 15:8); + s(EmcWarmBootMrwExtra, 23:16, scratch5, 23:16); + s(EmcWarmBootMrwExtra, 7:0, scratch5, 31:24); + s(EmcMrwLpddr2ZcalWarmBoot, 31:30, scratch6, 1:0); + s(EmcWarmBootMrwExtra, 31:30, scratch6, 3:2); + s(EmcMrwLpddr2ZcalWarmBoot, 27:26, scratch6, 5:4); + s(EmcWarmBootMrwExtra, 27:26, scratch6, 7:6); + s(EmcMrw6, 27:0, scratch8, 27:0); + s(EmcMrw6, 31:30, scratch8, 29:28); + s(EmcMrw8, 27:0, scratch9, 27:0); + s(EmcMrw8, 31:30, scratch9, 29:28); + s(EmcMrw9, 27:0, scratch10, 27:0); + s(EmcMrw9, 31:30, scratch10, 29:28); + s(EmcMrw10, 27:0, scratch11, 27:0); + s(EmcMrw10, 31:30, scratch11, 29:28); + s(EmcMrw12, 27:0, scratch12, 27:0); + s(EmcMrw12, 31:30, scratch12, 29:28); + s(EmcMrw13, 27:0, scratch13, 27:0); + s(EmcMrw13, 31:30, scratch13, 29:28); + s(EmcMrw14, 27:0, scratch14, 27:0); + s(EmcMrw14, 31:30, scratch14, 29:28); + s(EmcMrw1, 7:0, scratch15, 7:0); + s(EmcMrw1, 23:16, scratch15, 15:8); + s(EmcMrw1, 27:26, scratch15, 17:16); + s(EmcMrw1, 31:30, scratch15, 19:18); + s(EmcWarmBootMrwExtra, 7:0, scratch16, 7:0); + s(EmcWarmBootMrwExtra, 23:16, scratch16, 15:8); + s(EmcWarmBootMrwExtra, 27:26, scratch16, 17:16); + s(EmcWarmBootMrwExtra, 31:30, scratch16, 19:18); + s(EmcMrw2, 7:0, scratch17, 7:0); + s(EmcMrw2, 23:16, scratch17, 15:8); + s(EmcMrw2, 27:26, scratch17, 17:16); + s(EmcMrw2, 31:30, scratch17, 19:18); + s(EmcMrw3, 7:0, scratch18, 7:0); + s(EmcMrw3, 23:16, scratch18, 15:8); + s(EmcMrw3, 27:26, scratch18, 17:16); + s(EmcMrw3, 31:30, scratch18, 19:18); + s(EmcMrw4, 7:0, scratch19, 7:0); + s(EmcMrw4, 23:16, scratch19, 15:8); + s(EmcMrw4, 27:26, scratch19, 17:16); + s(EmcMrw4, 31:30, scratch19, 19:18); + break; + case NvBootMemoryType_Ddr3: + s(EmcMrs, 13:0, scratch5, 13:0); + s(EmcEmrs, 13:0, scratch5, 27:14); + s(EmcMrs, 21:20, scratch5, 29:28); + s(EmcMrs, 31:30, scratch5, 31:30); + s(EmcEmrs2, 13:0, scratch8, 13:0); + s(EmcEmrs3, 13:0, scratch8, 27:14); + s(EmcEmrs, 21:20, scratch8, 29:28); + s(EmcWarmBootMrsExtra, 13:0, scratch9, 13:0); + s(EmcEmrs, 31:30, scratch9, 15:14); + s(EmcEmrs2, 21:20, scratch9, 17:16); + s(EmcEmrs2, 31:30, scratch9, 19:18); + s(EmcEmrs3, 21:20, scratch9, 21:20); + s(EmcEmrs3, 31:30, scratch9, 23:22); + s(EmcWarmBootMrsExtra, 31:30, scratch9, 25:24); + s(EmcWarmBootMrsExtra, 21:20, scratch9, 27:26); + s(EmcZqCalDdr3WarmBoot, 31:30, scratch9, 29:28); + s(EmcMrs, 27:26, scratch10, 1:0); + s(EmcEmrs, 27:26, scratch10, 3:2); + s(EmcEmrs2, 27:26, scratch10, 5:4); + s(EmcEmrs3, 27:26, scratch10, 7:6); + s(EmcWarmBootMrsExtra, 27:27, scratch10, 8:8); + s(EmcWarmBootMrsExtra, 26:26, scratch10, 9:9); + s(EmcZqCalDdr3WarmBoot, 0:0, scratch10, 10:10); + s(EmcZqCalDdr3WarmBoot, 4:4, scratch10, 11:11); + break; + default: break; + } + + s32(EmcCmdMappingByte, secure_scratch8); + s32(EmcPmacroBrickMapping0, secure_scratch9); + s32(EmcPmacroBrickMapping1, secure_scratch10); + s32(EmcPmacroBrickMapping2, secure_scratch11); + s32(McVideoProtectGpuOverride0, secure_scratch12); + s(EmcCmdMappingCmd0_0, 6:0, secure_scratch13, 6:0); + s(EmcCmdMappingCmd0_0, 14:8, secure_scratch13, 13:7); + s(EmcCmdMappingCmd0_0, 22:16, secure_scratch13, 20:14); + s(EmcCmdMappingCmd0_0, 30:24, secure_scratch13, 27:21); + s(McVideoProtectBomAdrHi, 1:0, secure_scratch13, 29:28); + s(McVideoProtectWriteAccess, 1:0, secure_scratch13, 31:30); + s(EmcCmdMappingCmd0_1, 6:0, secure_scratch14, 6:0); + s(EmcCmdMappingCmd0_1, 14:8, secure_scratch14, 13:7); + s(EmcCmdMappingCmd0_1, 22:16, secure_scratch14, 20:14); + s(EmcCmdMappingCmd0_1, 30:24, secure_scratch14, 27:21); + s(McSecCarveoutAdrHi, 1:0, secure_scratch14, 29:28); + s(McMtsCarveoutAdrHi, 1:0, secure_scratch14, 31:30); + s(EmcCmdMappingCmd1_0, 6:0, secure_scratch15, 6:0); + s(EmcCmdMappingCmd1_0, 14:8, secure_scratch15, 13:7); + s(EmcCmdMappingCmd1_0, 22:16, secure_scratch15, 20:14); + s(EmcCmdMappingCmd1_0, 30:24, secure_scratch15, 27:21); + s(McGeneralizedCarveout5BomHi, 1:0, secure_scratch15, 29:28); + s(McGeneralizedCarveout3BomHi, 1:0, secure_scratch15, 31:30); + s(EmcCmdMappingCmd1_1, 6:0, secure_scratch16, 6:0); + s(EmcCmdMappingCmd1_1, 14:8, secure_scratch16, 13:7); + s(EmcCmdMappingCmd1_1, 22:16, secure_scratch16, 20:14); + s(EmcCmdMappingCmd1_1, 30:24, secure_scratch16, 27:21); + s(McGeneralizedCarveout2BomHi, 1:0, secure_scratch16, 29:28); + s(McGeneralizedCarveout4BomHi, 1:0, secure_scratch16, 31:30); + s(EmcCmdMappingCmd2_0, 6:0, secure_scratch17, 6:0); + s(EmcCmdMappingCmd2_0, 14:8, secure_scratch17, 13:7); + s(EmcCmdMappingCmd2_0, 22:16, secure_scratch17, 20:14); + s(EmcCmdMappingCmd2_0, 30:24, secure_scratch17, 27:21); + s(McGeneralizedCarveout1BomHi, 1:0, secure_scratch17, 29:28); + s(EmcAdrCfg, 0:0, secure_scratch17, 30:30); + s(EmcFbioSpare, 1:1, secure_scratch17, 31:31); + s(EmcCmdMappingCmd2_1, 6:0, secure_scratch18, 6:0); + s(EmcCmdMappingCmd2_1, 14:8, secure_scratch18, 13:7); + s(EmcCmdMappingCmd2_1, 22:16, secure_scratch18, 20:14); + s(EmcCmdMappingCmd2_1, 30:24, secure_scratch18, 27:21); + s(EmcFbioCfg8, 15:15, secure_scratch18, 28:28); + s(McEmemAdrCfg, 0:0, secure_scratch18, 29:29); + s(McSecCarveoutProtectWriteAccess, 0:0, secure_scratch18, 30:30); + s(McMtsCarveoutRegCtrl, 0:0, secure_scratch18, 31:31); + s(EmcCmdMappingCmd3_0, 6:0, secure_scratch19, 6:0); + s(EmcCmdMappingCmd3_0, 14:8, secure_scratch19, 13:7); + s(EmcCmdMappingCmd3_0, 22:16, secure_scratch19, 20:14); + s(EmcCmdMappingCmd3_0, 30:24, secure_scratch19, 27:21); + s(McGeneralizedCarveout2Cfg0, 6:3, secure_scratch19, 31:28); + s(EmcCmdMappingCmd3_1, 6:0, secure_scratch20, 6:0); + s(EmcCmdMappingCmd3_1, 14:8, secure_scratch20, 13:7); + s(EmcCmdMappingCmd3_1, 22:16, secure_scratch20, 20:14); + s(EmcCmdMappingCmd3_1, 30:24, secure_scratch20, 27:21); + s(McGeneralizedCarveout2Cfg0, 10:7, secure_scratch20, 31:28); + s(McGeneralizedCarveout4Cfg0, 26:0, secure_scratch39, 26:0); + s(McGeneralizedCarveout2Cfg0, 17:14, secure_scratch39, 30:27); + s(McVideoProtectVprOverride, 0:0, secure_scratch39, 31:31); + s(McGeneralizedCarveout5Cfg0, 26:0, secure_scratch40, 26:0); + s(McGeneralizedCarveout2Cfg0, 21:18, secure_scratch40, 30:27); + s(McVideoProtectVprOverride, 1:1, secure_scratch40, 31:31); + s(EmcCmdMappingCmd0_2, 6:0, secure_scratch41, 6:0); + s(EmcCmdMappingCmd0_2, 14:8, secure_scratch41, 13:7); + s(EmcCmdMappingCmd0_2, 22:16, secure_scratch41, 20:14); + s(EmcCmdMappingCmd0_2, 27:24, secure_scratch41, 24:21); + s(McGeneralizedCarveout1Cfg0, 6:3, secure_scratch41, 28:25); + s(McGeneralizedCarveout2Cfg0, 13:11, secure_scratch41, 31:29); + s(EmcCmdMappingCmd1_2, 6:0, secure_scratch42, 6:0); + s(EmcCmdMappingCmd1_2, 14:8, secure_scratch42, 13:7); + s(EmcCmdMappingCmd1_2, 22:16, secure_scratch42, 20:14); + s(EmcCmdMappingCmd1_2, 27:24, secure_scratch42, 24:21); + s(McGeneralizedCarveout1Cfg0, 13:7, secure_scratch42, 31:25); + s(EmcCmdMappingCmd2_2, 6:0, secure_scratch43, 6:0); + s(EmcCmdMappingCmd2_2, 14:8, secure_scratch43, 13:7); + s(EmcCmdMappingCmd2_2, 22:16, secure_scratch43, 20:14); + s(EmcCmdMappingCmd2_2, 27:24, secure_scratch43, 24:21); + s(McGeneralizedCarveout1Cfg0, 17:14, secure_scratch43, 28:25); + s(McGeneralizedCarveout3Cfg0, 13:11, secure_scratch43, 31:29); + s(EmcCmdMappingCmd3_2, 6:0, secure_scratch44, 6:0); + s(EmcCmdMappingCmd3_2, 14:8, secure_scratch44, 13:7); + s(EmcCmdMappingCmd3_2, 22:16, secure_scratch44, 20:14); + s(EmcCmdMappingCmd3_2, 27:24, secure_scratch44, 24:21); + s(McGeneralizedCarveout1Cfg0, 21:18, secure_scratch44, 28:25); + s(McVideoProtectVprOverride, 3:2, secure_scratch44, 30:29); + s(McVideoProtectVprOverride, 6:6, secure_scratch44, 31:31); + s(McEmemAdrCfgChannelMask, 31:9, secure_scratch45, 22:0); + s(McEmemAdrCfgDev0, 2:0, secure_scratch45, 25:23); + s(McEmemAdrCfgDev0, 9:8, secure_scratch45, 27:26); + s(McEmemAdrCfgDev0, 19:16, secure_scratch45, 31:28); + s(McEmemAdrCfgBankMask0, 31:10, secure_scratch46, 21:0); + s(McEmemAdrCfgDev1, 2:0, secure_scratch46, 24:22); + s(McEmemAdrCfgDev1, 9:8, secure_scratch46, 26:25); + s(McEmemAdrCfgDev1, 19:16, secure_scratch46, 30:27); + s(McVideoProtectVprOverride, 7:7, secure_scratch46, 31:31); + s(McEmemAdrCfgBankMask1, 31:10, secure_scratch47, 21:0); + s(McGeneralizedCarveout3Cfg0, 10:3, secure_scratch47, 29:22); + s(McVideoProtectVprOverride, 9:8, secure_scratch47, 31:30); + s(McEmemAdrCfgBankMask2, 31:10, secure_scratch48, 21:0); + s(McGeneralizedCarveout3Cfg0, 21:14, secure_scratch48, 29:22); + s(McVideoProtectVprOverride, 11:11, secure_scratch48, 30:30); + s(McVideoProtectVprOverride, 14:14, secure_scratch48, 31:31); + s(McVideoProtectGpuOverride1, 15:0, secure_scratch49, 15:0); + s(McEmemCfg, 13:0, secure_scratch49, 29:16); + s(McEmemCfg, 31:31, secure_scratch49, 30:30); + s(McVideoProtectVprOverride, 15:15, secure_scratch49, 31:31); + s(McGeneralizedCarveout3Bom, 31:17, secure_scratch50, 14:0); + s(McGeneralizedCarveout1Bom, 31:17, secure_scratch50, 29:15); + s(McVideoProtectVprOverride, 18:17, secure_scratch50, 31:30); + s(McGeneralizedCarveout4Bom, 31:17, secure_scratch51, 14:0); + s(McGeneralizedCarveout2Bom, 31:17, secure_scratch51, 29:15); + s(McVideoProtectVprOverride, 20:19, secure_scratch51, 31:30); + s(McGeneralizedCarveout5Bom, 31:17, secure_scratch52, 14:0); + s(McVideoProtectBom, 31:20, secure_scratch52, 26:15); + s(McVideoProtectVprOverride, 23:21, secure_scratch52, 29:27); + s(McVideoProtectVprOverride, 26:26, secure_scratch52, 30:30); + s(McVideoProtectVprOverride, 29:29, secure_scratch52, 31:31); + s(McVideoProtectSizeMb, 11:0, secure_scratch53, 11:0); + s(McSecCarveoutBom, 31:20, secure_scratch53, 23:12); + s(McVideoProtectVprOverride, 31:30, secure_scratch53, 25:24); + s(McVideoProtectVprOverride1, 1:0, secure_scratch53, 27:26); + s(McVideoProtectVprOverride1, 7:4, secure_scratch53, 31:28); + s(McSecCarveoutSizeMb, 11:0, secure_scratch54, 11:0); + s(McMtsCarveoutBom, 31:20, secure_scratch54, 23:12); + s(McVideoProtectVprOverride1, 15:8, secure_scratch54, 31:24); + s(McMtsCarveoutSizeMb, 11:0, secure_scratch55, 11:0); + s(McGeneralizedCarveout4Size128kb, 11:0, secure_scratch55, 23:12); + s(McVideoProtectVprOverride1, 16:16, secure_scratch55, 24:24); + s(McGeneralizedCarveout2Cfg0, 2:0, secure_scratch55, 27:25); + s(McGeneralizedCarveout2Cfg0, 25:22, secure_scratch55, 31:28); + s(McGeneralizedCarveout3Size128kb, 11:0, secure_scratch56, 11:0); + s(McGeneralizedCarveout2Size128kb, 11:0, secure_scratch56, 23:12); + s(McGeneralizedCarveout2Cfg0, 26:26, secure_scratch56, 24:24); + s(McGeneralizedCarveout1Cfg0, 2:0, secure_scratch56, 27:25); + s(McGeneralizedCarveout1Cfg0, 25:22, secure_scratch56, 31:28); + s(McGeneralizedCarveout1Size128kb, 11:0, secure_scratch57, 11:0); + s(McGeneralizedCarveout5Size128kb, 11:0, secure_scratch57, 23:12); + s(McGeneralizedCarveout1Cfg0, 26:26, secure_scratch57, 24:24); + s(McGeneralizedCarveout3Cfg0, 2:0, secure_scratch57, 27:25); + s(McGeneralizedCarveout3Cfg0, 25:22, secure_scratch57, 31:28); + s(McGeneralizedCarveout3Cfg0, 26:26, secure_scratch58, 0:0); + + s32(McGeneralizedCarveout1Access0, secure_scratch59); + s32(McGeneralizedCarveout1Access1, secure_scratch60); + s32(McGeneralizedCarveout1Access2, secure_scratch61); + s32(McGeneralizedCarveout1Access3, secure_scratch62); + s32(McGeneralizedCarveout1Access4, secure_scratch63); + s32(McGeneralizedCarveout2Access0, secure_scratch64); + s32(McGeneralizedCarveout2Access1, secure_scratch65); + s32(McGeneralizedCarveout2Access2, secure_scratch66); + s32(McGeneralizedCarveout2Access3, secure_scratch67); + s32(McGeneralizedCarveout2Access4, secure_scratch68); + s32(McGeneralizedCarveout3Access0, secure_scratch69); + s32(McGeneralizedCarveout3Access1, secure_scratch70); + s32(McGeneralizedCarveout3Access2, secure_scratch71); + s32(McGeneralizedCarveout3Access3, secure_scratch72); + s32(McGeneralizedCarveout3Access4, secure_scratch73); + s32(McGeneralizedCarveout4Access0, secure_scratch74); + s32(McGeneralizedCarveout4Access1, secure_scratch75); + s32(McGeneralizedCarveout4Access2, secure_scratch76); + s32(McGeneralizedCarveout4Access3, secure_scratch77); + s32(McGeneralizedCarveout4Access4, secure_scratch78); + s32(McGeneralizedCarveout5Access0, secure_scratch79); + s32(McGeneralizedCarveout5Access1, secure_scratch80); + s32(McGeneralizedCarveout5Access2, secure_scratch81); + s32(McGeneralizedCarveout5Access3, secure_scratch82); + s32(McGeneralizedCarveout1ForceInternalAccess0, secure_scratch84); + s32(McGeneralizedCarveout1ForceInternalAccess1, secure_scratch85); + s32(McGeneralizedCarveout1ForceInternalAccess2, secure_scratch86); + s32(McGeneralizedCarveout1ForceInternalAccess3, secure_scratch87); + s32(McGeneralizedCarveout1ForceInternalAccess4, secure_scratch88); + s32(McGeneralizedCarveout2ForceInternalAccess0, secure_scratch89); + s32(McGeneralizedCarveout2ForceInternalAccess1, secure_scratch90); + s32(McGeneralizedCarveout2ForceInternalAccess2, secure_scratch91); + s32(McGeneralizedCarveout2ForceInternalAccess3, secure_scratch92); + s32(McGeneralizedCarveout2ForceInternalAccess4, secure_scratch93); + s32(McGeneralizedCarveout3ForceInternalAccess0, secure_scratch94); + s32(McGeneralizedCarveout3ForceInternalAccess1, secure_scratch95); + s32(McGeneralizedCarveout3ForceInternalAccess2, secure_scratch96); + s32(McGeneralizedCarveout3ForceInternalAccess3, secure_scratch97); + s32(McGeneralizedCarveout3ForceInternalAccess4, secure_scratch98); + s32(McGeneralizedCarveout4ForceInternalAccess0, secure_scratch99); + s32(McGeneralizedCarveout4ForceInternalAccess1, secure_scratch100); + s32(McGeneralizedCarveout4ForceInternalAccess2, secure_scratch101); + s32(McGeneralizedCarveout4ForceInternalAccess3, secure_scratch102); + s32(McGeneralizedCarveout4ForceInternalAccess4, secure_scratch103); + s32(McGeneralizedCarveout5ForceInternalAccess0, secure_scratch104); + s32(McGeneralizedCarveout5ForceInternalAccess1, secure_scratch105); + s32(McGeneralizedCarveout5ForceInternalAccess2, secure_scratch106); + s32(McGeneralizedCarveout5ForceInternalAccess3, secure_scratch107); + + c32(0, scratch2); + s(PllMInputDivider, 7:0, scratch2, 7:0); + s(PllMFeedbackDivider, 7:0, scratch2, 15:8); + s(PllMPostDivider, 4:0, scratch2, 20:16); + s(PllMKVCO, 0:0, scratch2, 21:21); + s(PllMKCP, 1:0, scratch2, 23:22); + + c32(0, scratch35); + s(PllMSetupControl, 15:0, scratch35, 15:0); + + c32(0, scratch3); + s(PllMInputDivider, 7:0, scratch3, 7:0); + c(0x3e, scratch3, 15:8); + c(0, scratch3, 20:16); + s(PllMKVCO, 0:0, scratch3, 21:21); + s(PllMKCP, 1:0, scratch3, 23:22); + + c32(0, scratch36); + s(PllMSetupControl, 23:0, scratch36, 23:0); + + c32(0, scratch4); + s(PllMStableTime, 9:0, scratch4, 9:0); +} + +void sdram_save_params_mariko(const void *save_params) { + /* TODO */ +} \ No newline at end of file diff --git a/fusee/fusee-primary/src/sdram.h b/fusee/fusee-primary/src/sdram.h index 98e3b0990..5e81ac279 100644 --- a/fusee/fusee-primary/src/sdram.h +++ b/fusee/fusee-primary/src/sdram.h @@ -18,8 +18,11 @@ #ifndef FUSEE_SDRAM_H_ #define FUSEE_SDRAM_H_ -void sdram_init(); -const void *sdram_get_params(); -void sdram_lp0_save_params(const void *params); +void sdram_init_erista(void); +void sdram_init_mariko(void); +const void *sdram_get_params_erista(uint32_t dram_id); +const void *sdram_get_params_mariko(uint32_t dram_id); +void sdram_save_params_erista(const void *save_params); +void sdram_save_params_mariko(const void *save_params); #endif diff --git a/fusee/fusee-primary/src/sdram.inl b/fusee/fusee-primary/src/sdram.inl index 845ad1161..0036c0ca7 100644 --- a/fusee/fusee-primary/src/sdram.inl +++ b/fusee/fusee-primary/src/sdram.inl @@ -1,5 +1,6 @@ /* * Copyright (c) 2018 naehrwert + * Copyright (c) 2018-2020 Atmosphère-NX * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -14,7 +15,7 @@ * along with this program. If not, see . */ -static const uint8_t _dram_cfg_0[1896] = { +static const uint8_t sdram_params_erista_0[1896] = { 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -175,7 +176,7 @@ static const uint8_t _dram_cfg_0[1896] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -static const uint8_t _dram_cfg_1[1896] = { +static const uint8_t sdram_params_erista_1[1896] = { 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -336,7 +337,7 @@ static const uint8_t _dram_cfg_1[1896] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -static const uint8_t _dram_cfg_2[1896] = { +static const uint8_t sdram_params_erista_2[1896] = { 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -497,7 +498,7 @@ static const uint8_t _dram_cfg_2[1896] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -static const uint8_t _dram_cfg_3[1896] = { +static const uint8_t sdram_params_erista_3[1896] = { 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -658,7 +659,7 @@ static const uint8_t _dram_cfg_3[1896] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -static const uint8_t _dram_cfg_4[1896] = { +static const uint8_t sdram_params_erista_4[1896] = { 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -819,7 +820,7 @@ static const uint8_t _dram_cfg_4[1896] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -static const uint8_t _dram_cfg_5[1896] = { +static const uint8_t sdram_params_erista_5[1896] = { 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -980,7 +981,7 @@ static const uint8_t _dram_cfg_5[1896] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -static const uint8_t _dram_cfg_6[1896] = { +static const uint8_t sdram_params_erista_6[1896] = { 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1141,12 +1142,2237 @@ static const uint8_t _dram_cfg_6[1896] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -static const uint32_t *_dram_cfgs[7] = { - (const uint32_t *)_dram_cfg_0, - (const uint32_t *)_dram_cfg_1, - (const uint32_t *)_dram_cfg_2, - (const uint32_t *)_dram_cfg_3, - (const uint32_t *)_dram_cfg_4, - (const uint32_t *)_dram_cfg_5, - (const uint32_t *)_dram_cfg_6 +static const uint8_t sdram_params_mariko_0[2104] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x40, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00, 0x20, 0x12, 0x00, 0x00, + 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xBC, 0xBC, 0xC5, 0xB3, 0x3C, 0x9E, 0x00, 0x00, + 0x02, 0x03, 0xE0, 0xC1, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, + 0x04, 0x04, 0x04, 0x04, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x3F, 0x3F, 0x20, 0x12, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, + 0x50, 0x50, 0x50, 0x00, 0xA1, 0x01, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, + 0x00, 0x10, 0x00, 0x16, 0x00, 0x10, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, + 0x3A, 0x00, 0x00, 0x00, 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, + 0x17, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x20, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, + 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x0E, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, + 0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, + 0x1A, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, + 0x0A, 0x00, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xC1, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x14, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x3B, 0x00, 0x00, 0x00, 0x3B, 0x00, 0x00, 0x00, + 0x05, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91, + 0x3F, 0x3A, 0x00, 0x00, 0x00, 0x00, 0xF3, 0x0C, 0x04, 0x05, 0x1B, 0x06, + 0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A, + 0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03, 0x02, 0x1B, 0x1C, 0x23, + 0x03, 0x04, 0x07, 0x05, 0x06, 0x25, 0x25, 0x02, 0x0A, 0x0B, 0x1D, 0x0D, + 0x08, 0x0C, 0x09, 0x1E, 0x24, 0x26, 0x26, 0x08, 0x24, 0x06, 0x07, 0x9A, + 0x12, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x01, 0x88, 0x00, 0x00, 0x02, 0x88, 0x00, 0x00, 0x0D, 0x88, + 0x00, 0x00, 0x00, 0xC0, 0x31, 0x31, 0x03, 0x88, 0x00, 0x00, 0x0B, 0x88, + 0x5D, 0x5D, 0x0E, 0x8C, 0x5D, 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0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x2C, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t sdram_params_mariko_2[2104] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 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0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x2C, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t sdram_params_mariko_3[2104] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, + 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00, 0x20, 0x12, 0x00, 0x00, + 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xBC, 0xBC, 0xC5, 0xB3, 0x3C, 0x9E, 0x00, 0x00, + 0x02, 0x03, 0xE0, 0xC1, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, + 0x04, 0x04, 0x04, 0x04, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x3F, 0x3F, 0x20, 0x12, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, + 0x50, 0x50, 0x50, 0x00, 0xA1, 0x01, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, + 0x00, 0x10, 0x00, 0x16, 0x00, 0x10, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, + 0x3A, 0x00, 0x00, 0x00, 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x08, 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0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x2C, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t sdram_params_mariko_5[2104] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x2C, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t sdram_params_mariko_6[2104] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x2C, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t sdram_params_mariko_8[2104] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 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0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x2C, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t sdram_params_mariko_9[2104] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 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0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, + 0x3A, 0x00, 0x00, 0x00, 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, + 0x17, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x20, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, + 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x0E, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, + 0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, + 0x1A, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, + 0x0A, 0x00, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xC1, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x14, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x3B, 0x00, 0x00, 0x00, 0x3B, 0x00, 0x00, 0x00, + 0x05, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91, + 0x3F, 0x3A, 0x00, 0x00, 0x00, 0x00, 0xF3, 0x0C, 0x04, 0x05, 0x1B, 0x06, + 0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A, + 0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03, 0x02, 0x1B, 0x1C, 0x23, + 0x03, 0x04, 0x07, 0x05, 0x06, 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0x1E, 0x40, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x2C, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t sdram_params_mariko_10[2104] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 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0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t sdram_params_mariko_11[2104] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const uint32_t sdram_params_index_table_erista[28] = { + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, +}; + +static const uint32_t *sdram_params_erista[7] = { + (const uint32_t *)sdram_params_erista_0, + (const uint32_t *)sdram_params_erista_1, + (const uint32_t *)sdram_params_erista_2, + (const uint32_t *)sdram_params_erista_3, + (const uint32_t *)sdram_params_erista_4, + (const uint32_t *)sdram_params_erista_5, + (const uint32_t *)sdram_params_erista_6, +}; + +static const uint32_t sdram_params_index_table_mariko[28] = { + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0, + 1, + 2, + 3, + 4, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 6, + 8, + 9, + 0xA, + 7, + 6, + 0xB, + 0xB, + 0xB, +}; + +static const uint32_t *sdram_params_mariko[12] = { + (const uint32_t *)sdram_params_mariko_0, + (const uint32_t *)sdram_params_mariko_1, + (const uint32_t *)sdram_params_mariko_2, + (const uint32_t *)sdram_params_mariko_3, + (const uint32_t *)sdram_params_mariko_4, + (const uint32_t *)sdram_params_mariko_5, + (const uint32_t *)sdram_params_mariko_6, + (const uint32_t *)sdram_params_mariko_7, + (const uint32_t *)sdram_params_mariko_8, + (const uint32_t *)sdram_params_mariko_9, + (const uint32_t *)sdram_params_mariko_10, + (const uint32_t *)sdram_params_mariko_11, }; diff --git a/fusee/fusee-primary/src/sdram_lp0.c b/fusee/fusee-primary/src/sdram_lp0.c deleted file mode 100644 index 12864e63c..000000000 --- a/fusee/fusee-primary/src/sdram_lp0.c +++ /dev/null @@ -1,1125 +0,0 @@ -/* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * Copyright 2014 Google Inc. - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 CTCaer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include "pmc.h" -#include "sdram_param_t210_lp0.h" - -/* - * This function reads SDRAM parameters from the common BCT format and - * writes them into PMC scratch registers (where the BootROM expects them - * on LP0 resume). - */ -void sdram_lp0_save_params(const void *params) -{ - struct sdram_params *sdram = (struct sdram_params *)params; - volatile tegra_pmc_t *pmc = pmc_get_regs(); - -#define pack(src, src_bits, dst, dst_bits) { \ - uint32_t mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \ - dst &= ~(mask << (0 ? dst_bits)); \ - dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \ -} - -#define s(param, src_bits, pmcreg, dst_bits) \ - pack(sdram->param, src_bits, pmc->pmcreg, dst_bits) - -#define c(value, pmcreg, dst_bits) \ - pack(value, (1 ? dst_bits) - (0 ? dst_bits) : 0, pmc->pmcreg, dst_bits) - -/* 32 bits version of s macro */ -#define s32(param, pmcreg) pmc->pmcreg = sdram->param - -/* 32 bits version c macro */ -#define c32(value, pmcreg) pmc->pmcreg = value - - //TODO: pkg1.1 (1.X - 3.X) reads them from MC. - // Patch carveout parameters. - /*sdram->McGeneralizedCarveout1Bom = 0; - sdram->McGeneralizedCarveout1BomHi = 0; - sdram->McGeneralizedCarveout1Size128kb = 0; - sdram->McGeneralizedCarveout1Access0 = 0; - sdram->McGeneralizedCarveout1Access1 = 0; - sdram->McGeneralizedCarveout1Access2 = 0; - sdram->McGeneralizedCarveout1Access3 = 0; - sdram->McGeneralizedCarveout1Access4 = 0; - sdram->McGeneralizedCarveout1ForceInternalAccess0 = 0; - sdram->McGeneralizedCarveout1ForceInternalAccess1 = 0; - sdram->McGeneralizedCarveout1ForceInternalAccess2 = 0; - sdram->McGeneralizedCarveout1ForceInternalAccess3 = 0; - sdram->McGeneralizedCarveout1ForceInternalAccess4 = 0; - sdram->McGeneralizedCarveout1Cfg0 = 0; - sdram->McGeneralizedCarveout2Bom = 0x80020000; - sdram->McGeneralizedCarveout2BomHi = 0; - sdram->McGeneralizedCarveout2Size128kb = 2; - sdram->McGeneralizedCarveout2Access0 = 0; - sdram->McGeneralizedCarveout2Access1 = 0; - sdram->McGeneralizedCarveout2Access2 = 0x3000000; - sdram->McGeneralizedCarveout2Access3 = 0; - sdram->McGeneralizedCarveout2Access4 = 0x300; - sdram->McGeneralizedCarveout2ForceInternalAccess0 = 0; - sdram->McGeneralizedCarveout2ForceInternalAccess1 = 0; - sdram->McGeneralizedCarveout2ForceInternalAccess2 = 0; - sdram->McGeneralizedCarveout2ForceInternalAccess3 = 0; - sdram->McGeneralizedCarveout2ForceInternalAccess4 = 0; - sdram->McGeneralizedCarveout2Cfg0 = 0x440167E; - sdram->McGeneralizedCarveout3Bom = 0; - sdram->McGeneralizedCarveout3BomHi = 0; - sdram->McGeneralizedCarveout3Size128kb = 0; - sdram->McGeneralizedCarveout3Access0 = 0; - sdram->McGeneralizedCarveout3Access1 = 0; - sdram->McGeneralizedCarveout3Access2 = 0x3000000; - sdram->McGeneralizedCarveout3Access3 = 0; - sdram->McGeneralizedCarveout3Access4 = 0x300; - sdram->McGeneralizedCarveout3ForceInternalAccess0 = 0; - sdram->McGeneralizedCarveout3ForceInternalAccess1 = 0; - sdram->McGeneralizedCarveout3ForceInternalAccess2 = 0; - sdram->McGeneralizedCarveout3ForceInternalAccess3 = 0; - sdram->McGeneralizedCarveout3ForceInternalAccess4 = 0; - sdram->McGeneralizedCarveout3Cfg0 = 0x4401E7E; - sdram->McGeneralizedCarveout4Bom = 0; - sdram->McGeneralizedCarveout4BomHi = 0; - sdram->McGeneralizedCarveout4Size128kb = 0; - sdram->McGeneralizedCarveout4Access0 = 0; - sdram->McGeneralizedCarveout4Access1 = 0; - sdram->McGeneralizedCarveout4Access2 = 0; - sdram->McGeneralizedCarveout4Access3 = 0; - sdram->McGeneralizedCarveout4Access4 = 0; - sdram->McGeneralizedCarveout4ForceInternalAccess0 = 0; - sdram->McGeneralizedCarveout4ForceInternalAccess1 = 0; - sdram->McGeneralizedCarveout4ForceInternalAccess2 = 0; - sdram->McGeneralizedCarveout4ForceInternalAccess3 = 0; - sdram->McGeneralizedCarveout4ForceInternalAccess4 = 0; - sdram->McGeneralizedCarveout4Cfg0 = 0x8F; - sdram->McGeneralizedCarveout5Bom = 0; - sdram->McGeneralizedCarveout5BomHi = 0; - sdram->McGeneralizedCarveout5Size128kb = 0; - sdram->McGeneralizedCarveout5Access0 = 0; - sdram->McGeneralizedCarveout5Access1 = 0; - sdram->McGeneralizedCarveout5Access2 = 0; - sdram->McGeneralizedCarveout5Access3 = 0; - sdram->McGeneralizedCarveout5Access4 = 0; - sdram->McGeneralizedCarveout5ForceInternalAccess0 = 0; - sdram->McGeneralizedCarveout5ForceInternalAccess1 = 0; - sdram->McGeneralizedCarveout5ForceInternalAccess2 = 0; - sdram->McGeneralizedCarveout5ForceInternalAccess3 = 0; - sdram->McGeneralizedCarveout5ForceInternalAccess4 = 0; - sdram->McGeneralizedCarveout5Cfg0 = 0x8F;*/ - - //TODO: this is 4.X+ behaviour which seems to work fine for < 4.X. - // Patch carveout parameters. - sdram->McGeneralizedCarveout1Cfg0 = 0; - sdram->McGeneralizedCarveout2Cfg0 = 0; - sdram->McGeneralizedCarveout3Cfg0 = 0; - sdram->McGeneralizedCarveout4Cfg0 = 0; - sdram->McGeneralizedCarveout5Cfg0 = 0; - - // Patch SDRAM parameters. - uint32_t t0 = sdram->EmcSwizzleRank0Byte0 << 5 >> 29 > sdram->EmcSwizzleRank0Byte0 << 1 >> 29; - uint32_t t1 = (t0 & 0xFFFFFFEF) | ((sdram->EmcSwizzleRank1Byte0 << 5 >> 29 > sdram->EmcSwizzleRank1Byte0 << 1 >> 29) << 4); - uint32_t t2 = (t1 & 0xFFFFFFFD) | ((sdram->EmcSwizzleRank0Byte1 << 5 >> 29 > sdram->EmcSwizzleRank0Byte1 << 1 >> 29) << 1); - uint32_t t3 = (t2 & 0xFFFFFFDF) | ((sdram->EmcSwizzleRank1Byte1 << 5 >> 29 > sdram->EmcSwizzleRank1Byte1 << 1 >> 29) << 5); - uint32_t t4 = (t3 & 0xFFFFFFFB) | ((sdram->EmcSwizzleRank0Byte2 << 5 >> 29 > sdram->EmcSwizzleRank0Byte2 << 1 >> 29) << 2); - uint32_t t5 = (t4 & 0xFFFFFFBF) | ((sdram->EmcSwizzleRank1Byte2 << 5 >> 29 > sdram->EmcSwizzleRank1Byte2 << 1 >> 29) << 6); - uint32_t t6 = (t5 & 0xFFFFFFF7) | ((sdram->EmcSwizzleRank0Byte3 << 5 >> 29 > sdram->EmcSwizzleRank0Byte3 << 1 >> 29) << 3); - uint32_t t7 = (t6 & 0xFFFFFF7F) | ((sdram->EmcSwizzleRank1Byte3 << 5 >> 29 > sdram->EmcSwizzleRank1Byte3 << 1 >> 29) << 7); - sdram->SwizzleRankByteEncode = t7; - sdram->EmcBctSpare2 = 0x40000DD8; - sdram->EmcBctSpare3 = t7; - - s(EmcClockSource, 7:0, scratch6, 15:8); - s(EmcClockSourceDll, 7:0, scratch6, 23:16); - s(EmcClockSource, 31:29, scratch6, 26:24); - s(EmcClockSourceDll, 31:29, scratch6, 29:27); - s(EmcClockSourceDll, 11:10, scratch6, 31:30); - s(ClkRstControllerPllmMisc2Override, 9:8, scratch7, 1:0); - s(ClkRstControllerPllmMisc2Override, 2:1, scratch7, 3:2); - s(EmcZqCalLpDdr4WarmBoot, 31:30, scratch7, 5:4); - s(EmcClockSource, 15:15, scratch7, 6:6); - s(EmcClockSource, 26:26, scratch7, 7:7); - s(EmcClockSource, 20:20, scratch7, 8:8); - s(EmcClockSource, 19:19, scratch7, 9:9); - s(ClkRstControllerPllmMisc2Override, 13:13, scratch7, 10:10); - s(ClkRstControllerPllmMisc2Override, 12:12, scratch7, 11:11); - s(ClkRstControllerPllmMisc2Override, 11:11, scratch7, 12:12); - s(ClkRstControllerPllmMisc2Override, 10:10, scratch7, 13:13); - s(ClkRstControllerPllmMisc2Override, 5:5, scratch7, 14:14); - s(ClkRstControllerPllmMisc2Override, 4:4, scratch7, 15:15); - s(ClkRstControllerPllmMisc2Override, 3:3, scratch7, 16:16); - s(ClkRstControllerPllmMisc2Override, 0:0, scratch7, 17:17); - s(EmcZqCalLpDdr4WarmBoot, 1:0, scratch7, 19:18); - s(EmcZqCalLpDdr4WarmBoot, 4:4, scratch7, 20:20); - s(EmcOdtWrite, 5:0, scratch7, 26:21); - s(EmcOdtWrite, 11:8, scratch7, 30:27); - s(EmcOdtWrite, 31:31, scratch7, 31:31); - s(EmcFdpdCtrlCmdNoRamp, 0:0, scratch13, 30:30); - s(EmcCfgPipeClk, 0:0, scratch13, 31:31); - s(McEmemArbMisc2, 0:0, scratch14, 30:30); - s(McDaCfg0, 0:0, scratch14, 31:31); - s(EmcQRst, 6:0, scratch15, 26:20); - s(EmcQRst, 20:16, scratch15, 31:27); - s(EmcPmacroCmdTxDrv, 5:0, scratch16, 25:20); - s(EmcPmacroCmdTxDrv, 13:8, scratch16, 31:26); - s(EmcPmacroAutocalCfg0, 2:0, scratch17, 22:20); - s(EmcPmacroAutocalCfg0, 10:8, scratch17, 25:23); - s(EmcPmacroAutocalCfg0, 18:16, scratch17, 28:26); - s(EmcPmacroAutocalCfg0, 26:24, scratch17, 31:29); - s(EmcPmacroAutocalCfg1, 2:0, scratch18, 22:20); - s(EmcPmacroAutocalCfg1, 10:8, scratch18, 25:23); - s(EmcPmacroAutocalCfg1, 18:16, scratch18, 28:26); - s(EmcPmacroAutocalCfg1, 26:24, scratch18, 31:29); - s(EmcPmacroAutocalCfg2, 2:0, scratch19, 22:20); - s(EmcPmacroAutocalCfg2, 10:8, scratch19, 25:23); - s(EmcPmacroAutocalCfg2, 18:16, scratch19, 28:26); - s(EmcPmacroAutocalCfg2, 26:24, scratch19, 31:29); - s32(EmcCfgRsv,scratch22); - s32(EmcAutoCalConfig, scratch23); - s32(EmcAutoCalVrefSel0, scratch24); - s32(EmcPmacroBrickCtrlRfu1, scratch25); - s32(EmcPmacroBrickCtrlRfu2, scratch26); - s32(EmcPmcScratch1, scratch27); - s32(EmcPmcScratch2, scratch28); - s32(EmcPmcScratch3, scratch29); - s32(McEmemArbDaTurns, scratch30); - s(EmcFbioSpare, 31:24, scratch58, 7:0); - s(EmcFbioSpare, 23:16, scratch58, 15:8); - s(EmcFbioSpare, 15:8, scratch58, 23:16); - s(EmcFbioSpare, 7:2, scratch58, 29:24); - s(EmcFbioSpare, 0:0, scratch58, 30:30); - s(EmcDllCfg0, 29:0, scratch59, 29:0); - s(EmcPmacroDdllBypass, 11:0, scratch60, 11:0); - s(EmcPmacroDdllBypass, 27:13, scratch60, 26:12); - s(EmcPmacroDdllBypass, 31:29, scratch60, 29:27); - s(McEmemArbMisc0, 14:0, scratch61, 14:0); - s(McEmemArbMisc0, 30:16, scratch61, 29:15); - s(EmcFdpdCtrlCmd, 16:0, scratch62, 16:0); - s(EmcFdpdCtrlCmd, 31:20, scratch62, 28:17); - s(EmcAutoCalConfig2, 27:0, scratch63, 27:0); - s(EmcBurstRefreshNum, 3:0, scratch63, 31:28); - s(EmcPmacroZctrl, 27:0, scratch64, 27:0); - s(EmcTppd, 3:0, scratch64, 31:28); - s(EmcCfgDigDll, 10:0, scratch65, 10:0); - s(EmcCfgDigDll, 25:12, scratch65, 24:11); - s(EmcCfgDigDll, 27:27, scratch65, 25:25); - s(EmcCfgDigDll, 31:30, scratch65, 27:26); - s(EmcR2r, 3:0, scratch65, 31:28); - s(EmcFdpdCtrlDq, 16:0, scratch66, 16:0); - s(EmcFdpdCtrlDq, 28:20, scratch66, 25:17); - s(EmcFdpdCtrlDq, 31:30, scratch66, 27:26); - s(EmcW2w, 3:0, scratch66, 31:28); - s(EmcPmacroTxPwrd4, 13:0, scratch67, 13:0); - s(EmcPmacroTxPwrd4, 29:16, scratch67, 27:14); - s(EmcPmacroCommonPadTxCtrl, 3:0, scratch67, 31:28); - s(EmcPmacroTxPwrd5, 13:0, scratch68, 13:0); - s(EmcPmacroTxPwrd5, 29:16, scratch68, 27:14); - s(EmcPmacroDdllPwrd0, 4:0, scratch69, 4:0); - s(EmcPmacroDdllPwrd0, 12:6, scratch69, 11:5); - s(EmcPmacroDdllPwrd0, 20:14, scratch69, 18:12); - s(EmcPmacroDdllPwrd0, 28:22, scratch69, 25:19); - s(EmcPmacroDdllPwrd0, 31:30, scratch69, 27:26); - s(EmcCfg, 4:4, scratch69, 31:31); - s(EmcPmacroDdllPwrd1, 4:0, scratch70, 4:0); - s(EmcPmacroDdllPwrd1, 12:6, scratch70, 11:5); - s(EmcPmacroDdllPwrd1, 20:14, scratch70, 18:12); - s(EmcPmacroDdllPwrd1, 28:22, scratch70, 25:19); - s(EmcPmacroDdllPwrd1, 31:30, scratch70, 27:26); - s(EmcCfg, 5:5, scratch70, 31:31); - s(EmcPmacroDdllPwrd2, 4:0, scratch71, 4:0); - s(EmcPmacroDdllPwrd2, 12:6, scratch71, 11:5); - s(EmcPmacroDdllPwrd2, 20:14, scratch71, 18:12); - s(EmcPmacroDdllPwrd2, 28:22, scratch71, 25:19); - s(EmcPmacroDdllPwrd2, 31:30, scratch71, 27:26); - s(EmcFbioCfg5, 23:20, scratch71, 31:28); - s(EmcPmacroIbVrefDq_0, 6:0, scratch72, 6:0); - s(EmcPmacroIbVrefDq_0, 14:8, scratch72, 13:7); - s(EmcPmacroIbVrefDq_0, 22:16, scratch72, 20:14); - s(EmcPmacroIbVrefDq_0, 30:24, scratch72, 27:21); - s(EmcFbioCfg5, 15:13, scratch72, 30:28); - s(EmcCfg, 6:6, scratch72, 31:31); - s(EmcPmacroIbVrefDq_1, 6:0, scratch73, 6:0); - s(EmcPmacroIbVrefDq_1, 14:8, scratch73, 13:7); - s(EmcPmacroIbVrefDq_1, 22:16, scratch73, 20:14); - s(EmcPmacroIbVrefDq_1, 30:24, scratch73, 27:21); - s(EmcCfg2, 5:3, scratch73, 30:28); - s(EmcCfg, 7:7, scratch73, 31:31); - s(EmcPmacroIbVrefDqs_0, 6:0, scratch74, 6:0); - s(EmcPmacroIbVrefDqs_0, 14:8, scratch74, 13:7); - s(EmcPmacroIbVrefDqs_0, 22:16, scratch74, 20:14); - s(EmcPmacroIbVrefDqs_0, 30:24, scratch74, 27:21); - s(EmcCfg, 17:16, scratch74, 29:28); - s(EmcFbioCfg5, 1:0, scratch74, 31:30); - s(EmcPmacroIbVrefDqs_1, 6:0, scratch75, 6:0); - s(EmcPmacroIbVrefDqs_1, 14:8, scratch75, 13:7); - s(EmcPmacroIbVrefDqs_1, 22:16, scratch75, 20:14); - s(EmcPmacroIbVrefDqs_1, 30:24, scratch75, 27:21); - s(EmcFbioCfg5, 3:2, scratch75, 29:28); - s(EmcCfg2, 27:26, scratch75, 31:30); - s(EmcPmacroDdllShortCmd_0, 6:0, scratch76, 6:0); - s(EmcPmacroDdllShortCmd_0, 14:8, scratch76, 13:7); - s(EmcPmacroDdllShortCmd_0, 22:16, scratch76, 20:14); - s(EmcPmacroDdllShortCmd_0, 30:24, scratch76, 27:21); - s(EmcPmacroCmdPadTxCtrl, 3:2, scratch76, 29:28); - s(EmcPmacroCmdPadTxCtrl, 7:6, scratch76, 31:30); - s(EmcPmacroDdllShortCmd_1, 6:0, scratch77, 6:0); - s(EmcPmacroDdllShortCmd_1, 14:8, scratch77, 13:7); - s(EmcPmacroDdllShortCmd_1, 22:16, scratch77, 20:14); - s(EmcPmacroDdllShortCmd_1, 30:24, scratch77, 27:21); - s(EmcPmacroCmdPadTxCtrl, 11:10, scratch77, 29:28); - s(EmcPmacroCmdPadTxCtrl, 15:14, scratch77, 31:30); - s(EmcAutoCalChannel, 5:0, scratch78, 5:0); - s(EmcAutoCalChannel, 11:8, scratch78, 9:6); - s(EmcAutoCalChannel, 27:16, scratch78, 21:10); - s(EmcAutoCalChannel, 31:29, scratch78, 24:22); - s(EmcConfigSampleDelay, 6:0, scratch78, 31:25); - s(EmcPmacroRxTerm, 5:0, scratch79, 5:0); - s(EmcPmacroRxTerm, 13:8, scratch79, 11:6); - s(EmcPmacroRxTerm, 21:16, scratch79, 17:12); - s(EmcPmacroRxTerm, 29:24, scratch79, 23:18); - s(EmcRc, 7:0, scratch79, 31:24); - s(EmcPmacroDqTxDrv, 5:0, scratch80, 5:0); - s(EmcPmacroDqTxDrv, 13:8, scratch80, 11:6); - s(EmcPmacroDqTxDrv, 21:16, scratch80, 17:12); - s(EmcPmacroDqTxDrv, 29:24, scratch80, 23:18); - s(EmcSelDpdCtrl, 5:2, scratch80, 27:24); - s(EmcSelDpdCtrl, 8:8, scratch80, 28:28); - s(EmcSelDpdCtrl, 18:16, scratch80, 31:29); - s(EmcPmacroCaTxDrv, 5:0, scratch81, 5:0); - s(EmcPmacroCaTxDrv, 13:8, scratch81, 11:6); - s(EmcPmacroCaTxDrv, 21:16, scratch81, 17:12); - s(EmcPmacroCaTxDrv, 29:24, scratch81, 23:18); - s(EmcObdly, 5:0, scratch81, 29:24); - s(EmcObdly, 29:28, scratch81, 31:30); - s(EmcZcalInterval, 23:10, scratch82, 13:0); - s(EmcZcalInterval, 9:0, scratch82, 23:14); - s(EmcPmacroCmdRxTermMode, 1:0, scratch82, 25:24); - s(EmcPmacroCmdRxTermMode, 5:4, scratch82, 27:26); - s(EmcPmacroCmdRxTermMode, 9:8, scratch82, 29:28); - s(EmcPmacroCmdRxTermMode, 13:12, scratch82, 31:30); - s(EmcDataBrlshft0, 23:0, scratch83, 23:0); - s(EmcPmacroDataRxTermMode, 1:0, scratch83, 25:24); - s(EmcPmacroDataRxTermMode, 5:4, scratch83, 27:26); - s(EmcPmacroDataRxTermMode, 9:8, scratch83, 29:28); - s(EmcPmacroDataRxTermMode, 13:12, scratch83, 31:30); - s(EmcDataBrlshft1, 23:0, scratch84, 23:0); - s(McEmemArbTimingRc, 7:0, scratch84, 31:24); - s(EmcDqsBrlshft0, 23:0, scratch85, 23:0); - s(McEmemArbRsv, 7:0, scratch85, 31:24); - s(EmcDqsBrlshft1, 23:0, scratch86, 23:0); - s(EmcCfgPipe2, 11:0, scratch87, 11:0); - s(EmcCfgPipe2, 27:16, scratch87, 23:12); - s(EmcCfgPipe1, 11:0, scratch88, 11:0); - s(EmcCfgPipe1, 27:16, scratch88, 23:12); - s(EmcPmacroCmdCtrl0, 5:0, scratch89, 5:0); - s(EmcPmacroCmdCtrl0, 13:8, scratch89, 11:6); - s(EmcPmacroCmdCtrl0, 21:16, scratch89, 17:12); - s(EmcPmacroCmdCtrl0, 29:24, scratch89, 23:18); - s(EmcPmacroCmdCtrl1, 5:0, scratch90, 5:0); - s(EmcPmacroCmdCtrl1, 13:8, scratch90, 11:6); - s(EmcPmacroCmdCtrl1, 21:16, scratch90, 17:12); - s(EmcPmacroCmdCtrl1, 29:24, scratch90, 23:18); - s(EmcRas, 6:0, scratch90, 30:24); - s(EmcCfg, 8:8, scratch90, 31:31); - s(EmcPmacroVttgenCtrl2, 23:0, scratch91, 23:0); - s(EmcW2p, 6:0, scratch91, 30:24); - s(EmcCfg, 9:9, scratch91, 31:31); - s(EmcPmacroCmdPadRxCtrl, 2:0, scratch92, 2:0); - s(EmcPmacroCmdPadRxCtrl, 5:4, scratch92, 4:3); - s(EmcPmacroCmdPadRxCtrl, 10:8, scratch92, 7:5); - s(EmcPmacroCmdPadRxCtrl, 22:12, scratch92, 18:8); - s(EmcPmacroCmdPadRxCtrl, 28:24, scratch92, 23:19); - s(EmcQSafe, 6:0, scratch92, 30:24); - s(EmcCfg, 18:18, scratch92, 31:31); - s(EmcPmacroDataPadRxCtrl, 2:0, scratch93, 2:0); - s(EmcPmacroDataPadRxCtrl, 5:4, scratch93, 4:3); - s(EmcPmacroDataPadRxCtrl, 10:8, scratch93, 7:5); - s(EmcPmacroDataPadRxCtrl, 22:12, scratch93, 18:8); - s(EmcPmacroDataPadRxCtrl, 28:24, scratch93, 23:19); - s(EmcRdv, 6:0, scratch93, 30:24); - s(EmcCfg, 21:21, scratch93, 31:31); - s(McEmemArbDaCovers, 23:0, scratch94, 23:0); - s(EmcRw2Pden, 6:0, scratch94, 30:24); - s(EmcCfg, 22:22, scratch94, 31:31); - s(EmcPmacroCmdCtrl2, 5:0, scratch95, 5:0); - s(EmcPmacroCmdCtrl2, 13:9, scratch95, 10:6); - s(EmcPmacroCmdCtrl2, 21:16, scratch95, 16:11); - s(EmcPmacroCmdCtrl2, 29:24, scratch95, 22:17); - s(EmcRfcPb, 8:0, scratch95, 31:23); - s(EmcPmacroQuseDdllRank0_0, 10:0, scratch96, 10:0); - s(EmcPmacroQuseDdllRank0_0, 26:16, scratch96, 21:11); - s(EmcCfgUpdate, 2:0, scratch96, 24:22); - s(EmcCfgUpdate, 10:8, scratch96, 27:25); - s(EmcCfgUpdate, 31:28, scratch96, 31:28); - s(EmcPmacroQuseDdllRank0_1, 10:0, scratch97, 10:0); - s(EmcPmacroQuseDdllRank0_1, 26:16, scratch97, 21:11); - s(EmcRfc, 9:0, scratch97, 31:22); - s(EmcPmacroQuseDdllRank0_2, 10:0, scratch98, 10:0); - s(EmcPmacroQuseDdllRank0_2, 26:16, scratch98, 21:11); - s(EmcTxsr, 9:0, scratch98, 31:22); - s(EmcPmacroQuseDdllRank0_3, 10:0, scratch99, 10:0); - s(EmcPmacroQuseDdllRank0_3, 26:16, scratch99, 21:11); - s(EmcMc2EmcQ, 2:0, scratch99, 24:22); - s(EmcMc2EmcQ, 10:8, scratch99, 27:25); - s(EmcMc2EmcQ, 27:24, scratch99, 31:28); - s(EmcPmacroQuseDdllRank0_4, 10:0, scratch100, 10:0); - s(EmcPmacroQuseDdllRank0_4, 26:16, scratch100, 21:11); - s(McEmemArbRing1Throttle, 4:0, scratch100, 26:22); - s(McEmemArbRing1Throttle, 20:16, scratch100, 31:27); - s(EmcPmacroQuseDdllRank0_5, 10:0, scratch101, 10:0); - s(EmcPmacroQuseDdllRank0_5, 26:16, scratch101, 21:11); - s(EmcPmacroQuseDdllRank1_0, 10:0, scratch102, 10:0); - s(EmcPmacroQuseDdllRank1_0, 26:16, scratch102, 21:11); - s(EmcAr2Pden, 8:0, scratch102, 30:22); - s(EmcCfg, 23:23, scratch102, 31:31); - s(EmcPmacroQuseDdllRank1_1, 10:0, scratch103, 10:0); - s(EmcPmacroQuseDdllRank1_1, 26:16, scratch103, 21:11); - s(EmcRfcSlr, 8:0, scratch103, 30:22); - s(EmcCfg, 24:24, scratch103, 31:31); - s(EmcPmacroQuseDdllRank1_2, 10:0, scratch104, 10:0); - s(EmcPmacroQuseDdllRank1_2, 26:16, scratch104, 21:11); - s(EmcIbdly, 6:0, scratch104, 28:22); - s(EmcIbdly, 29:28, scratch104, 30:29); - s(EmcCfg, 25:25, scratch104, 31:31); - s(EmcPmacroQuseDdllRank1_3, 10:0, scratch105, 10:0); - s(EmcPmacroQuseDdllRank1_3, 26:16, scratch105, 21:11); - s(McEmemArbTimingRFCPB, 8:0, scratch105, 30:22); - s(EmcCfg, 26:26, scratch105, 31:31); - s(EmcPmacroQuseDdllRank1_4, 10:0, scratch106, 10:0); - s(EmcPmacroQuseDdllRank1_4, 26:16, scratch106, 21:11); - s(EmcTfaw, 6:0, scratch106, 28:22); - s(EmcPmacroDataPadTxCtrl, 3:2, scratch106, 30:29); - s(EmcCfg, 28:28, scratch106, 31:31); - s(EmcPmacroQuseDdllRank1_5, 10:0, scratch107, 10:0); - s(EmcPmacroQuseDdllRank1_5, 26:16, scratch107, 21:11); - s(EmcTClkStable, 6:0, scratch107, 28:22); - s(EmcPmacroDataPadTxCtrl, 7:6, scratch107, 30:29); - s(EmcCfg, 29:29, scratch107, 31:31); - s(EmcPmacroObDdllLongDqRank0_0, 10:0, scratch108, 10:0); - s(EmcPmacroObDdllLongDqRank0_0, 26:16, scratch108, 21:11); - s(EmcPdex2Mrr, 6:0, scratch108, 28:22); - s(EmcPmacroDataPadTxCtrl, 11:10, scratch108, 30:29); - s(EmcCfg, 30:30, scratch108, 31:31); - s(EmcPmacroObDdllLongDqRank0_1, 10:0, scratch109, 10:0); - s(EmcPmacroObDdllLongDqRank0_1, 26:16, scratch109, 21:11); - s(EmcRdvMask, 6:0, scratch109, 28:22); - s(EmcPmacroDataPadTxCtrl, 15:14, scratch109, 30:29); - s(EmcCfg, 31:31, scratch109, 31:31); - s(EmcPmacroObDdllLongDqRank0_2, 10:0, scratch110, 10:0); - s(EmcPmacroObDdllLongDqRank0_2, 26:16, scratch110, 21:11); - s(EmcRdvEarlyMask, 6:0, scratch110, 28:22); - s(EmcFbioCfg5, 4:4, scratch110, 29:29); - s(EmcFbioCfg5, 8:8, scratch110, 30:30); - s(EmcFbioCfg5, 10:10, scratch110, 31:31); - s(EmcPmacroObDdllLongDqRank0_3, 10:0, scratch111, 10:0); - s(EmcPmacroObDdllLongDqRank0_3, 26:16, scratch111, 21:11); - s(EmcRdvEarly, 6:0, scratch111, 28:22); - s(EmcFbioCfg5, 12:12, scratch111, 29:29); - s(EmcFbioCfg5, 25:24, scratch111, 31:30); - s(EmcPmacroObDdllLongDqRank0_4, 10:0, scratch112, 10:0); - s(EmcPmacroObDdllLongDqRank0_4, 26:16, scratch112, 21:11); - s(EmcPmacroDdllShortCmd_2, 6:0, scratch112, 28:22); - s(EmcFbioCfg5, 28:26, scratch112, 31:29); - s(EmcPmacroObDdllLongDqRank0_5, 10:0, scratch113, 10:0); - s(EmcPmacroObDdllLongDqRank0_5, 26:16, scratch113, 21:11); - s(McEmemArbTimingRp, 6:0, scratch113, 28:22); - s(EmcFbioCfg5, 31:30, scratch113, 30:29); - s(EmcCfg2, 0:0, scratch113, 31:31); - s(EmcPmacroObDdllLongDqRank1_0, 10:0, scratch114, 10:0); - s(EmcPmacroObDdllLongDqRank1_0, 26:16, scratch114, 21:11); - s(McEmemArbTimingRas, 6:0, scratch114, 28:22); - s(EmcCfg2, 2:1, scratch114, 30:29); - s(EmcCfg2, 7:7, scratch114, 31:31); - s(EmcPmacroObDdllLongDqRank1_1, 10:0, scratch115, 10:0); - s(EmcPmacroObDdllLongDqRank1_1, 26:16, scratch115, 21:11); - s(McEmemArbTimingFaw, 6:0, scratch115, 28:22); - s(EmcCfg2, 11:10, scratch115, 30:29); - s(EmcCfg2, 14:14, scratch115, 31:31); - s(EmcPmacroObDdllLongDqRank1_2, 10:0, scratch123, 10:0); - s(EmcPmacroObDdllLongDqRank1_2, 26:16, scratch123, 21:11); - s(McEmemArbTimingRap2Pre, 6:0, scratch123, 28:22); - s(EmcCfg2, 16:15, scratch123, 30:29); - s(EmcCfg2, 20:20, scratch123, 31:31); - s(EmcPmacroObDdllLongDqRank1_3, 10:0, scratch124, 10:0); - s(EmcPmacroObDdllLongDqRank1_3, 26:16, scratch124, 21:11); - s(McEmemArbTimingWap2Pre, 6:0, scratch124, 28:22); - s(EmcCfg2, 24:22, scratch124, 31:29); - s(EmcPmacroObDdllLongDqRank1_4, 10:0, scratch125, 10:0); - s(EmcPmacroObDdllLongDqRank1_4, 26:16, scratch125, 21:11); - s(McEmemArbTimingR2W, 6:0, scratch125, 28:22); - s(EmcCfg2, 25:25, scratch125, 29:29); - s(EmcCfg2, 29:28, scratch125, 31:30); - s(EmcPmacroObDdllLongDqRank1_5, 10:0, scratch126, 10:0); - s(EmcPmacroObDdllLongDqRank1_5, 26:16, scratch126, 21:11); - s(McEmemArbTimingW2R, 6:0, scratch126, 28:22); - s(EmcCfg2, 31:30, scratch126, 30:29); - s(EmcCfgPipe, 0:0, scratch126, 31:31); - s(EmcPmacroObDdllLongDqsRank0_0, 10:0, scratch127, 10:0); - s(EmcPmacroObDdllLongDqsRank0_0, 26:16, scratch127, 21:11); - s(EmcRp, 5:0, scratch127, 27:22); - s(EmcCfgPipe, 4:1, scratch127, 31:28); - s(EmcPmacroObDdllLongDqsRank0_1, 10:0, scratch128, 10:0); - s(EmcPmacroObDdllLongDqsRank0_1, 26:16, scratch128, 21:11); - s(EmcR2w, 5:0, scratch128, 27:22); - s(EmcCfgPipe, 8:5, scratch128, 31:28); - s(EmcPmacroObDdllLongDqsRank0_2, 10:0, scratch129, 10:0); - s(EmcPmacroObDdllLongDqsRank0_2, 26:16, scratch129, 21:11); - s(EmcW2r, 5:0, scratch129, 27:22); - s(EmcCfgPipe, 11:9, scratch129, 30:28); - s(EmcCfgPipe, 16:16, scratch129, 31:31); - s(EmcPmacroObDdllLongDqsRank0_3, 10:0, scratch130, 10:0); - s(EmcPmacroObDdllLongDqsRank0_3, 26:16, scratch130, 21:11); - s(EmcR2p, 5:0, scratch130, 27:22); - s(EmcCfgPipe, 20:17, scratch130, 31:28); - s(EmcPmacroObDdllLongDqsRank0_4, 10:0, scratch131, 10:0); - s(EmcPmacroObDdllLongDqsRank0_4, 26:16, scratch131, 21:11); - s(EmcCcdmw, 5:0, scratch131, 27:22); - s(EmcCfgPipe, 24:21, scratch131, 31:28); - s(EmcPmacroObDdllLongDqsRank0_5, 10:0, scratch132, 10:0); - s(EmcPmacroObDdllLongDqsRank0_5, 26:16, scratch132, 21:11); - s(EmcRdRcd, 5:0, scratch132, 27:22); - s(EmcCfgPipe, 27:25, scratch132, 30:28); - s(EmcPmacroTxPwrd0, 0:0, scratch132, 31:31); - s(EmcPmacroObDdllLongDqsRank1_0, 10:0, scratch133, 10:0); - s(EmcPmacroObDdllLongDqsRank1_0, 26:16, scratch133, 21:11); - s(EmcWrRcd, 5:0, scratch133, 27:22); - s(EmcPmacroTxPwrd0, 4:1, scratch133, 31:28); - s(EmcPmacroObDdllLongDqsRank1_1, 10:0, scratch134, 10:0); - s(EmcPmacroObDdllLongDqsRank1_1, 26:16, scratch134, 21:11); - s(EmcWdv, 5:0, scratch134, 27:22); - s(EmcPmacroTxPwrd0, 8:5, scratch134, 31:28); - s(EmcPmacroObDdllLongDqsRank1_2, 10:0, scratch135, 10:0); - s(EmcPmacroObDdllLongDqsRank1_2, 26:16, scratch135, 21:11); - s(EmcQUse, 5:0, scratch135, 27:22); - s(EmcPmacroTxPwrd0, 12:9, scratch135, 31:28); - s(EmcPmacroObDdllLongDqsRank1_3, 10:0, scratch136, 10:0); - s(EmcPmacroObDdllLongDqsRank1_3, 26:16, scratch136, 21:11); - s(EmcPdEx2Wr, 5:0, scratch136, 27:22); - s(EmcPmacroTxPwrd0, 13:13, scratch136, 28:28); - s(EmcPmacroTxPwrd0, 18:16, scratch136, 31:29); - s(EmcPmacroObDdllLongDqsRank1_4, 10:0, scratch137, 10:0); - s(EmcPmacroObDdllLongDqsRank1_4, 26:16, scratch137, 21:11); - s(EmcPdEx2Rd, 5:0, scratch137, 27:22); - s(EmcPmacroTxPwrd0, 22:19, scratch137, 31:28); - s(EmcPmacroObDdllLongDqsRank1_5, 10:0, scratch138, 10:0); - s(EmcPmacroObDdllLongDqsRank1_5, 26:16, scratch138, 21:11); - s(EmcPdex2Cke, 5:0, scratch138, 27:22); - s(EmcPmacroTxPwrd0, 26:23, scratch138, 31:28); - s(EmcPmacroIbDdllLongDqsRank0_0, 10:0, scratch139, 10:0); - s(EmcPmacroIbDdllLongDqsRank0_0, 26:16, scratch139, 21:11); - s(EmcPChg2Pden, 5:0, scratch139, 27:22); - s(EmcPmacroTxPwrd0, 29:27, scratch139, 30:28); - s(EmcPmacroTxPwrd1, 0:0, scratch139, 31:31); - s(EmcPmacroIbDdllLongDqsRank0_1, 10:0, scratch140, 10:0); - s(EmcPmacroIbDdllLongDqsRank0_1, 26:16, scratch140, 21:11); - s(EmcAct2Pden, 5:0, scratch140, 27:22); - s(EmcPmacroTxPwrd1, 4:1, scratch140, 31:28); - s(EmcPmacroIbDdllLongDqsRank0_2, 10:0, scratch141, 10:0); - s(EmcPmacroIbDdllLongDqsRank0_2, 26:16, scratch141, 21:11); - s(EmcCke2Pden, 5:0, scratch141, 27:22); - s(EmcPmacroTxPwrd1, 8:5, scratch141, 31:28); - s(EmcPmacroIbDdllLongDqsRank0_3, 10:0, scratch142, 10:0); - s(EmcPmacroIbDdllLongDqsRank0_3, 26:16, scratch142, 21:11); - s(EmcTcke, 5:0, scratch142, 27:22); - s(EmcPmacroTxPwrd1, 12:9, scratch142, 31:28); - s(EmcPmacroIbDdllLongDqsRank1_0, 10:0, scratch143, 10:0); - s(EmcPmacroIbDdllLongDqsRank1_0, 26:16, scratch143, 21:11); - s(EmcTrpab, 5:0, scratch143, 27:22); - s(EmcPmacroTxPwrd1, 13:13, scratch143, 28:28); - s(EmcPmacroTxPwrd1, 18:16, scratch143, 31:29); - s(EmcPmacroIbDdllLongDqsRank1_1, 10:0, scratch144, 10:0); - s(EmcPmacroIbDdllLongDqsRank1_1, 26:16, scratch144, 21:11); - s(EmcClkenOverride, 3:1, scratch144, 24:22); - s(EmcClkenOverride, 8:6, scratch144, 27:25); - s(EmcPmacroTxPwrd1, 22:19, scratch144, 31:28); - s(EmcPmacroIbDdllLongDqsRank1_2, 10:0, scratch145, 10:0); - s(EmcPmacroIbDdllLongDqsRank1_2, 26:16, scratch145, 21:11); - s(EmcEInput, 5:0, scratch145, 27:22); - s(EmcPmacroTxPwrd1, 26:23, scratch145, 31:28); - s(EmcPmacroIbDdllLongDqsRank1_3, 10:0, scratch146, 10:0); - s(EmcPmacroIbDdllLongDqsRank1_3, 26:16, scratch146, 21:11); - s(EmcEInputDuration, 5:0, scratch146, 27:22); - s(EmcPmacroTxPwrd1, 29:27, scratch146, 30:28); - s(EmcPmacroTxPwrd2, 0:0, scratch146, 31:31); - s(EmcPmacroDdllLongCmd_0, 10:0, scratch147, 10:0); - s(EmcPmacroDdllLongCmd_0, 26:16, scratch147, 21:11); - s(EmcPutermExtra, 5:0, scratch147, 27:22); - s(EmcPmacroTxPwrd2, 4:1, scratch147, 31:28); - s(EmcPmacroDdllLongCmd_1, 10:0, scratch148, 10:0); - s(EmcPmacroDdllLongCmd_1, 26:16, scratch148, 21:11); - s(EmcTckesr, 5:0, scratch148, 27:22); - s(EmcPmacroTxPwrd2, 8:5, scratch148, 31:28); - s(EmcPmacroDdllLongCmd_2, 10:0, scratch149, 10:0); - s(EmcPmacroDdllLongCmd_2, 26:16, scratch149, 21:11); - s(EmcTpd, 5:0, scratch149, 27:22); - s(EmcPmacroTxPwrd2, 12:9, scratch149, 31:28); - s(EmcPmacroDdllLongCmd_3, 10:0, scratch150, 10:0); - s(EmcPmacroDdllLongCmd_3, 26:16, scratch150, 21:11); - s(EmcWdvMask, 5:0, scratch150, 27:22); - s(EmcPmacroTxPwrd2, 13:13, scratch150, 28:28); - s(EmcPmacroTxPwrd2, 18:16, scratch150, 31:29); - s(McEmemArbCfg, 8:0, scratch151, 8:0); - s(McEmemArbCfg, 20:16, scratch151, 13:9); - s(McEmemArbCfg, 31:24, scratch151, 21:14); - s(EmcWdvChk, 5:0, scratch151, 27:22); - s(EmcPmacroTxPwrd2, 22:19, scratch151, 31:28); - s(McEmemArbMisc1, 12:0, scratch152, 12:0); - s(McEmemArbMisc1, 25:21, scratch152, 17:13); - s(McEmemArbMisc1, 31:28, scratch152, 21:18); - s(EmcCmdBrlshft0, 5:0, scratch152, 27:22); - s(EmcPmacroTxPwrd2, 26:23, scratch152, 31:28); - s(EmcMrsWaitCnt2, 9:0, scratch153, 9:0); - s(EmcMrsWaitCnt2, 26:16, scratch153, 20:10); - s(EmcPmacroIbRxrt, 10:0, scratch153, 31:21); - s(EmcMrsWaitCnt, 9:0, scratch154, 9:0); - s(EmcMrsWaitCnt, 26:16, scratch154, 20:10); - s(EmcPmacroDdllLongCmd_4, 10:0, scratch154, 31:21); - s(EmcAutoCalInterval, 20:0, scratch155, 20:0); - s(McEmemArbOutstandingReq, 8:0, scratch155, 29:21); - s(McEmemArbOutstandingReq, 31:30, scratch155, 31:30); - s(McEmemArbRefpbHpCtrl, 6:0, scratch156, 6:0); - s(McEmemArbRefpbHpCtrl, 14:8, scratch156, 13:7); - s(McEmemArbRefpbHpCtrl, 22:16, scratch156, 20:14); - s(EmcCmdBrlshft1, 5:0, scratch156, 26:21); - s(EmcRrd, 4:0, scratch156, 31:27); - s(EmcQuseBrlshft0, 19:0, scratch157, 19:0); - s(EmcFbioCfg8, 27:16, scratch157, 31:20); - s(EmcQuseBrlshft1, 19:0, scratch158, 19:0); - s(EmcTxsrDll, 11:0, scratch158, 31:20); - s(EmcQuseBrlshft2, 19:0, scratch159, 19:0); - s(EmcTxdsrvttgen, 11:0, scratch159, 31:20); - s(EmcQuseBrlshft3, 19:0, scratch160, 19:0); - s(EmcPmacroVttgenCtrl0, 3:0, scratch160, 23:20); - s(EmcPmacroVttgenCtrl0, 11:8, scratch160, 27:24); - s(EmcPmacroVttgenCtrl0, 19:16, scratch160, 31:28); - s(EmcPmacroVttgenCtrl1, 19:0, scratch161, 19:0); - s(EmcCmdBrlshft2, 5:0, scratch161, 25:20); - s(EmcCmdBrlshft3, 5:0, scratch161, 31:26); - s(EmcAutoCalConfig3, 5:0, scratch162, 5:0); - s(EmcAutoCalConfig3, 13:8, scratch162, 11:6); - s(EmcAutoCalConfig3, 18:16, scratch162, 14:12); - s(EmcAutoCalConfig3, 22:20, scratch162, 17:15); - s(EmcTRefBw, 13:0, scratch162, 31:18); - s(EmcAutoCalConfig4, 5:0, scratch163, 5:0); - s(EmcAutoCalConfig4, 13:8, scratch163, 11:6); - s(EmcAutoCalConfig4, 18:16, scratch163, 14:12); - s(EmcAutoCalConfig4, 22:20, scratch163, 17:15); - s(EmcQpop, 6:0, scratch163, 24:18); - s(EmcQpop, 22:16, scratch163, 31:25); - s(EmcAutoCalConfig5, 5:0, scratch164, 5:0); - s(EmcAutoCalConfig5, 13:8, scratch164, 11:6); - s(EmcAutoCalConfig5, 18:16, scratch164, 14:12); - s(EmcAutoCalConfig5, 22:20, scratch164, 17:15); - s(EmcPmacroAutocalCfgCommon, 5:0, scratch164, 23:18); - s(EmcPmacroAutocalCfgCommon, 13:8, scratch164, 29:24); - s(EmcPmacroAutocalCfgCommon, 16:16, scratch164, 30:30); - s(EmcPmacroTxPwrd2, 27:27, scratch164, 31:31); - s(EmcAutoCalConfig6, 5:0, scratch165, 5:0); - s(EmcAutoCalConfig6, 13:8, scratch165, 11:6); - s(EmcAutoCalConfig6, 18:16, scratch165, 14:12); - s(EmcAutoCalConfig6, 22:20, scratch165, 17:15); - s(EmcWev, 5:0, scratch165, 23:18); - s(EmcWsv, 5:0, scratch165, 29:24); - s(EmcPmacroTxPwrd2, 29:28, scratch165, 31:30); - s(EmcAutoCalConfig7, 5:0, scratch166, 5:0); - s(EmcAutoCalConfig7, 13:8, scratch166, 11:6); - s(EmcAutoCalConfig7, 18:16, scratch166, 14:12); - s(EmcAutoCalConfig7, 22:20, scratch166, 17:15); - s(EmcCfg3, 2:0, scratch166, 20:18); - s(EmcCfg3, 6:4, scratch166, 23:21); - s(EmcQuseWidth, 3:0, scratch166, 27:24); - s(EmcQuseWidth, 29:28, scratch166, 29:28); - s(EmcPmacroTxPwrd3, 1:0, scratch166, 31:30); - s(EmcAutoCalConfig8, 5:0, scratch167, 5:0); - s(EmcAutoCalConfig8, 13:8, scratch167, 11:6); - s(EmcAutoCalConfig8, 18:16, scratch167, 14:12); - s(EmcAutoCalConfig8, 22:20, scratch167, 17:15); - s(EmcPmacroBgBiasCtrl0, 2:0, scratch167, 20:18); - s(EmcPmacroBgBiasCtrl0, 6:4, scratch167, 23:21); - s(McEmemArbTimingRcd, 5:0, scratch167, 29:24); - s(EmcPmacroTxPwrd3, 3:2, scratch167, 31:30); - s(EmcXm2CompPadCtrl2, 17:0, scratch168, 17:0); - s(McEmemArbTimingCcdmw, 5:0, scratch168, 23:18); - s(McEmemArbOverride, 27:27, scratch168, 24:24); - s(McEmemArbOverride, 26:26, scratch168, 25:25); - s(McEmemArbOverride, 16:16, scratch168, 26:26); - s(McEmemArbOverride, 10:10, scratch168, 27:27); - s(McEmemArbOverride, 4:4, scratch168, 28:28); - s(McEmemArbOverride, 3:3, scratch168, 29:29); - s(EmcPmacroTxPwrd3, 5:4, scratch168, 31:30); - s(EmcXm2CompPadCtrl3, 17:0, scratch169, 17:0); - s(EmcRext, 4:0, scratch169, 22:18); - s(EmcTClkStop, 4:0, scratch169, 27:23); - s(EmcPmacroTxPwrd3, 9:6, scratch169, 31:28); - s(EmcZcalWaitCnt, 10:0, scratch170, 10:0); - s(EmcZcalWaitCnt, 21:16, scratch170, 16:11); - s(EmcZcalWaitCnt, 31:31, scratch170, 17:17); - s(EmcWext, 4:0, scratch170, 22:18); - s(EmcRefctrl2, 0:0, scratch170, 23:23); - s(EmcRefctrl2, 26:24, scratch170, 26:24); - s(EmcRefctrl2, 31:31, scratch170, 27:27); - s(EmcPmacroTxPwrd3, 13:10, scratch170, 31:28); - s(EmcZcalMrwCmd, 7:0, scratch171, 7:0); - s(EmcZcalMrwCmd, 23:16, scratch171, 15:8); - s(EmcZcalMrwCmd, 31:30, scratch171, 17:16); - s(EmcWeDuration, 4:0, scratch171, 22:18); - s(EmcWsDuration, 4:0, scratch171, 27:23); - s(EmcPmacroTxPwrd3, 19:16, scratch171, 31:28); - s(EmcSwizzleRank0Byte0, 2:0, scratch172, 2:0); - s(EmcSwizzleRank0Byte0, 6:4, scratch172, 5:3); - s(EmcSwizzleRank0Byte0, 10:8, scratch172, 8:6); - s(EmcSwizzleRank0Byte0, 14:12, scratch172, 11:9); - s(EmcSwizzleRank0Byte0, 18:16, scratch172, 14:12); - s(EmcSwizzleRank0Byte0, 22:20, scratch172, 17:15); - s(EmcPutermWidth, 31:31, scratch172, 18:18); - s(EmcPutermWidth, 3:0, scratch172, 22:19); - s(McEmemArbTimingRrd, 4:0, scratch172, 27:23); - s(EmcPmacroTxPwrd3, 23:20, scratch172, 31:28); - s(EmcSwizzleRank0Byte1, 2:0, scratch173, 2:0); - s(EmcSwizzleRank0Byte1, 6:4, scratch173, 5:3); - s(EmcSwizzleRank0Byte1, 10:8, scratch173, 8:6); - s(EmcSwizzleRank0Byte1, 14:12, scratch173, 11:9); - s(EmcSwizzleRank0Byte1, 18:16, scratch173, 14:12); - s(EmcSwizzleRank0Byte1, 22:20, scratch173, 17:15); - s(McEmemArbTimingR2R, 4:0, scratch173, 22:18); - s(McEmemArbTimingW2W, 4:0, scratch173, 27:23); - s(EmcPmacroTxPwrd3, 27:24, scratch173, 31:28); - s(EmcSwizzleRank0Byte2, 2:0, scratch174, 2:0); - s(EmcSwizzleRank0Byte2, 6:4, scratch174, 5:3); - s(EmcSwizzleRank0Byte2, 10:8, scratch174, 8:6); - s(EmcSwizzleRank0Byte2, 14:12, scratch174, 11:9); - s(EmcSwizzleRank0Byte2, 18:16, scratch174, 14:12); - s(EmcSwizzleRank0Byte2, 22:20, scratch174, 17:15); - s(EmcPmacroTxPwrd3, 29:28, scratch174, 19:18); - s(EmcPmacroTxSelClkSrc0, 11:0, scratch174, 31:20); - s(EmcSwizzleRank0Byte3, 2:0, scratch175, 2:0); - s(EmcSwizzleRank0Byte3, 6:4, scratch175, 5:3); - s(EmcSwizzleRank0Byte3, 10:8, scratch175, 8:6); - s(EmcSwizzleRank0Byte3, 14:12, scratch175, 11:9); - s(EmcSwizzleRank0Byte3, 18:16, scratch175, 14:12); - s(EmcSwizzleRank0Byte3, 22:20, scratch175, 17:15); - s(EmcPmacroTxSelClkSrc0, 27:16, scratch175, 29:18); - s(EmcPmacroTxSelClkSrc1, 1:0, scratch175, 31:30); - s(EmcSwizzleRank1Byte0, 2:0, scratch176, 2:0); - s(EmcSwizzleRank1Byte0, 6:4, scratch176, 5:3); - s(EmcSwizzleRank1Byte0, 10:8, scratch176, 8:6); - s(EmcSwizzleRank1Byte0, 14:12, scratch176, 11:9); - s(EmcSwizzleRank1Byte0, 18:16, scratch176, 14:12); - s(EmcSwizzleRank1Byte0, 22:20, scratch176, 17:15); - s(EmcPmacroTxSelClkSrc1, 11:2, scratch176, 27:18); - s(EmcPmacroTxSelClkSrc1, 19:16, scratch176, 31:28); - s(EmcSwizzleRank1Byte1, 2:0, scratch177, 2:0); - s(EmcSwizzleRank1Byte1, 6:4, scratch177, 5:3); - s(EmcSwizzleRank1Byte1, 10:8, scratch177, 8:6); - s(EmcSwizzleRank1Byte1, 14:12, scratch177, 11:9); - s(EmcSwizzleRank1Byte1, 18:16, scratch177, 14:12); - s(EmcSwizzleRank1Byte1, 22:20, scratch177, 17:15); - s(EmcPmacroTxSelClkSrc1, 27:20, scratch177, 25:18); - s(EmcPmacroTxSelClkSrc3, 5:0, scratch177, 31:26); - s(EmcSwizzleRank1Byte2, 2:0, scratch178, 2:0); - s(EmcSwizzleRank1Byte2, 6:4, scratch178, 5:3); - s(EmcSwizzleRank1Byte2, 10:8, scratch178, 8:6); - s(EmcSwizzleRank1Byte2, 14:12, scratch178, 11:9); - s(EmcSwizzleRank1Byte2, 18:16, scratch178, 14:12); - s(EmcSwizzleRank1Byte2, 22:20, scratch178, 17:15); - s(EmcPmacroTxSelClkSrc3, 11:6, scratch178, 23:18); - s(EmcPmacroTxSelClkSrc3, 23:16, scratch178, 31:24); - s(EmcSwizzleRank1Byte3, 2:0, scratch179, 2:0); - s(EmcSwizzleRank1Byte3, 6:4, scratch179, 5:3); - s(EmcSwizzleRank1Byte3, 10:8, scratch179, 8:6); - s(EmcSwizzleRank1Byte3, 14:12, scratch179, 11:9); - s(EmcSwizzleRank1Byte3, 18:16, scratch179, 14:12); - s(EmcSwizzleRank1Byte3, 22:20, scratch179, 17:15); - s(EmcPmacroTxSelClkSrc3, 27:24, scratch179, 21:18); - s(EmcPmacroTxSelClkSrc2, 9:0, scratch179, 31:22); - s(EmcPmacroCmdBrickCtrlFdpd, 17:0, scratch180, 17:0); - s(EmcPmacroTxSelClkSrc2, 11:10, scratch180, 19:18); - s(EmcPmacroTxSelClkSrc2, 27:16, scratch180, 31:20); - s(EmcPmacroDataBrickCtrlFdpd, 17:0, scratch181, 17:0); - s(EmcPmacroTxSelClkSrc4, 11:0, scratch181, 29:18); - s(EmcPmacroTxSelClkSrc4, 17:16, scratch181, 31:30); - s(EmcFbioCfg7, 16:0, scratch182, 16:0); - s(McEmemArbRefpbBankCtrl, 6:0, scratch182, 23:17); - s(McEmemArbRefpbBankCtrl, 14:8, scratch182, 30:24); - s(McEmemArbRefpbBankCtrl, 31:31, scratch182, 31:31); - s(EmcDynSelfRefControl, 15:0, scratch183, 15:0); - s(EmcDynSelfRefControl, 31:31, scratch183, 16:16); - s(EmcPmacroTxSelClkSrc4, 27:18, scratch183, 26:17); - s(EmcPmacroTxSelClkSrc5, 4:0, scratch183, 31:27); - s(EmcDllCfg1, 16:0, scratch184, 16:0); - s(EmcPmacroTxSelClkSrc5, 11:5, scratch184, 23:17); - s(EmcPmacroTxSelClkSrc5, 23:16, scratch184, 31:24); - s(EmcPmacroPadCfgCtrl, 1:0, scratch185, 1:0); - s(EmcPmacroPadCfgCtrl, 6:5, scratch185, 3:2); - s(EmcPmacroPadCfgCtrl, 11:9, scratch185, 6:4); - s(EmcPmacroPadCfgCtrl, 13:13, scratch185, 7:7); - s(EmcPmacroPadCfgCtrl, 17:16, scratch185, 9:8); - s(EmcPmacroPadCfgCtrl, 21:20, scratch185, 11:10); - s(EmcPmacroPadCfgCtrl, 25:24, scratch185, 13:12); - s(EmcPmacroPadCfgCtrl, 30:28, scratch185, 16:14); - s(EmcPmacroTxSelClkSrc5, 27:24, scratch185, 20:17); - s(EmcPmacroCmdPadTxCtrl, 1:0, scratch185, 22:21); - s(EmcPmacroCmdPadTxCtrl, 5:4, scratch185, 24:23); - s(EmcPmacroCmdPadTxCtrl, 9:8, scratch185, 26:25); - s(EmcPmacroCmdPadTxCtrl, 13:12, scratch185, 28:27); - s(EmcPmacroCmdPadTxCtrl, 16:16, scratch185, 29:29); - s(EmcPmacroCmdPadTxCtrl, 21:20, scratch185, 31:30); - s(EmcRefresh, 15:0, scratch186, 15:0); - s(EmcCmdQ, 4:0, scratch186, 20:16); - s(EmcCmdQ, 10:8, scratch186, 23:21); - s(EmcCmdQ, 14:12, scratch186, 26:24); - s(EmcCmdQ, 28:24, scratch186, 31:27); - s(EmcAcpdControl, 15:0, scratch187, 15:0); - s(EmcAutoCalVrefSel1, 15:0, scratch187, 31:16); - s(EmcXm2CompPadCtrl, 1:0, scratch188, 1:0); - s(EmcXm2CompPadCtrl, 6:3, scratch188, 5:2); - s(EmcXm2CompPadCtrl, 9:9, scratch188, 6:6); - s(EmcXm2CompPadCtrl, 19:11, scratch188, 15:7); - s(EmcCfgDigDllPeriod, 15:0, scratch188, 31:16); - s(EmcCfgDigDll_1, 15:0, scratch189, 15:0); - s(EmcPreRefreshReqCnt, 15:0, scratch189, 31:16); - s(EmcPmacroCmdPadTxCtrl, 27:24, scratch190, 19:16); - s(EmcPmacroDataPadTxCtrl, 1:0, scratch190, 21:20); - s(EmcPmacroDataPadTxCtrl, 5:4, scratch190, 23:22); - s(EmcPmacroDataPadTxCtrl, 9:8, scratch190, 25:24); - s(EmcPmacroDataPadTxCtrl, 13:12, scratch190, 27:26); - s(EmcPmacroDataPadTxCtrl, 16:16, scratch190, 28:28); - s(EmcPmacroDataPadTxCtrl, 21:20, scratch190, 30:29); - s(EmcPmacroDataPadTxCtrl, 24:24, scratch190, 31:31); - s(EmcPmacroDataPadTxCtrl, 27:25, scratch191, 2:0); - - s(EmcPinGpio, 1:0, scratch8, 31:30); - s(EmcPinGpioEn, 1:0, scratch9, 31:30); - s(EmcDevSelect, 1:0, scratch10, 31:30); - s(EmcZcalWarmColdBootEnables, 1:0, scratch11, 31:30); - s(EmcCfgDigDllPeriodWarmBoot, 1:0, scratch12, 31:30); - s32(EmcBctSpare13, scratch31); - s32(EmcBctSpare12, scratch32); - s32(EmcBctSpare7, scratch33); - s32(EmcBctSpare6, scratch40); - s32(EmcBctSpare5, scratch42); - s32(EmcBctSpare4, scratch44); - s32(EmcBctSpare3, scratch45); - s32(EmcBctSpare2, scratch46); - s32(EmcBctSpare1, scratch47); - s32(EmcBctSpare0, scratch48); - s32(EmcBctSpare9, scratch50); - s32(EmcBctSpare8, scratch51); - s32(BootRomPatchData, scratch56); - s32(BootRomPatchControl, scratch57); - s(McClkenOverrideAllWarmBoot, 0:0, scratch58, 31:31); - s(EmcClkenOverrideAllWarmBoot, 0:0, scratch59, 30:30); - s(EmcMrsWarmBootEnable, 0:0, scratch59, 31:31); - s(ClearClk2Mc1, 0:0, scratch60, 30:30); - s(EmcWarmBootExtraModeRegWriteEnable, 0:0, scratch60, 31:31); - s(ClkRstControllerPllmMisc2OverrideEnable, 0:0, scratch61, 30:30); - s(EmcDbgWriteMux, 0:0, scratch61, 31:31); - s(EmcExtraRefreshNum, 2:0, scratch62, 31:29); - s(PmcIoDpd3ReqWait, 2:0, scratch68, 30:28); - s(AhbArbitrationXbarCtrlMemInitDone, 0:0, scratch68, 31:31); - s(MemoryType, 2:0, scratch69, 30:28); - s(PmcIoDpd4ReqWait, 2:0, scratch70, 30:28); - s(EmcTimingControlWait, 7:0, scratch86, 31:24); - s(EmcZcalWarmBootWait, 7:0, scratch87, 31:24); - s(WarmBootWait, 7:0, scratch88, 31:24); - s(EmcPinProgramWait, 7:0, scratch89, 31:24); - s(EmcAutoCalWait, 9:0, scratch101, 31:22); - s(SwizzleRankByteEncode, 15:0, scratch190, 15:0); - - switch (sdram->MemoryType) - { - case NvBootMemoryType_LpDdr2: - case NvBootMemoryType_LpDdr4: - s(EmcMrwLpddr2ZcalWarmBoot, 23:16, scratch5, 7:0); - s(EmcMrwLpddr2ZcalWarmBoot, 7:0, scratch5, 15:8); - s(EmcWarmBootMrwExtra, 23:16, scratch5, 23:16); - s(EmcWarmBootMrwExtra, 7:0, scratch5, 31:24); - s(EmcMrwLpddr2ZcalWarmBoot, 31:30, scratch6, 1:0); - s(EmcWarmBootMrwExtra, 31:30, scratch6, 3:2); - s(EmcMrwLpddr2ZcalWarmBoot, 27:26, scratch6, 5:4); - s(EmcWarmBootMrwExtra, 27:26, scratch6, 7:6); - s(EmcMrw6, 27:0, scratch8, 27:0); - s(EmcMrw6, 31:30, scratch8, 29:28); - s(EmcMrw8, 27:0, scratch9, 27:0); - s(EmcMrw8, 31:30, scratch9, 29:28); - s(EmcMrw9, 27:0, scratch10, 27:0); - s(EmcMrw9, 31:30, scratch10, 29:28); - s(EmcMrw10, 27:0, scratch11, 27:0); - s(EmcMrw10, 31:30, scratch11, 29:28); - s(EmcMrw12, 27:0, scratch12, 27:0); - s(EmcMrw12, 31:30, scratch12, 29:28); - s(EmcMrw13, 27:0, scratch13, 27:0); - s(EmcMrw13, 31:30, scratch13, 29:28); - s(EmcMrw14, 27:0, scratch14, 27:0); - s(EmcMrw14, 31:30, scratch14, 29:28); - s(EmcMrw1, 7:0, scratch15, 7:0); - s(EmcMrw1, 23:16, scratch15, 15:8); - s(EmcMrw1, 27:26, scratch15, 17:16); - s(EmcMrw1, 31:30, scratch15, 19:18); - s(EmcWarmBootMrwExtra, 7:0, scratch16, 7:0); - s(EmcWarmBootMrwExtra, 23:16, scratch16, 15:8); - s(EmcWarmBootMrwExtra, 27:26, scratch16, 17:16); - s(EmcWarmBootMrwExtra, 31:30, scratch16, 19:18); - s(EmcMrw2, 7:0, scratch17, 7:0); - s(EmcMrw2, 23:16, scratch17, 15:8); - s(EmcMrw2, 27:26, scratch17, 17:16); - s(EmcMrw2, 31:30, scratch17, 19:18); - s(EmcMrw3, 7:0, scratch18, 7:0); - s(EmcMrw3, 23:16, scratch18, 15:8); - s(EmcMrw3, 27:26, scratch18, 17:16); - s(EmcMrw3, 31:30, scratch18, 19:18); - s(EmcMrw4, 7:0, scratch19, 7:0); - s(EmcMrw4, 23:16, scratch19, 15:8); - s(EmcMrw4, 27:26, scratch19, 17:16); - s(EmcMrw4, 31:30, scratch19, 19:18); - break; - case NvBootMemoryType_Ddr3: - s(EmcMrs, 13:0, scratch5, 13:0); - s(EmcEmrs, 13:0, scratch5, 27:14); - s(EmcMrs, 21:20, scratch5, 29:28); - s(EmcMrs, 31:30, scratch5, 31:30); - s(EmcEmrs2, 13:0, scratch8, 13:0); - s(EmcEmrs3, 13:0, scratch8, 27:14); - s(EmcEmrs, 21:20, scratch8, 29:28); - s(EmcWarmBootMrsExtra, 13:0, scratch9, 13:0); - s(EmcEmrs, 31:30, scratch9, 15:14); - s(EmcEmrs2, 21:20, scratch9, 17:16); - s(EmcEmrs2, 31:30, scratch9, 19:18); - s(EmcEmrs3, 21:20, scratch9, 21:20); - s(EmcEmrs3, 31:30, scratch9, 23:22); - s(EmcWarmBootMrsExtra, 31:30, scratch9, 25:24); - s(EmcWarmBootMrsExtra, 21:20, scratch9, 27:26); - s(EmcZqCalDdr3WarmBoot, 31:30, scratch9, 29:28); - s(EmcMrs, 27:26, scratch10, 1:0); - s(EmcEmrs, 27:26, scratch10, 3:2); - s(EmcEmrs2, 27:26, scratch10, 5:4); - s(EmcEmrs3, 27:26, scratch10, 7:6); - s(EmcWarmBootMrsExtra, 27:27, scratch10, 8:8); - s(EmcWarmBootMrsExtra, 26:26, scratch10, 9:9); - s(EmcZqCalDdr3WarmBoot, 0:0, scratch10, 10:10); - s(EmcZqCalDdr3WarmBoot, 4:4, scratch10, 11:11); - break; - } - - s32(EmcCmdMappingByte, secure_scratch8); - s32(EmcPmacroBrickMapping0, secure_scratch9); - s32(EmcPmacroBrickMapping1, secure_scratch10); - s32(EmcPmacroBrickMapping2, secure_scratch11); - s32(McVideoProtectGpuOverride0, secure_scratch12); - s(EmcCmdMappingCmd0_0, 6:0, secure_scratch13, 6:0); - s(EmcCmdMappingCmd0_0, 14:8, secure_scratch13, 13:7); - s(EmcCmdMappingCmd0_0, 22:16, secure_scratch13, 20:14); - s(EmcCmdMappingCmd0_0, 30:24, secure_scratch13, 27:21); - s(McVideoProtectBomAdrHi, 1:0, secure_scratch13, 29:28); - s(McVideoProtectWriteAccess, 1:0, secure_scratch13, 31:30); - s(EmcCmdMappingCmd0_1, 6:0, secure_scratch14, 6:0); - s(EmcCmdMappingCmd0_1, 14:8, secure_scratch14, 13:7); - s(EmcCmdMappingCmd0_1, 22:16, secure_scratch14, 20:14); - s(EmcCmdMappingCmd0_1, 30:24, secure_scratch14, 27:21); - s(McSecCarveoutAdrHi, 1:0, secure_scratch14, 29:28); - s(McMtsCarveoutAdrHi, 1:0, secure_scratch14, 31:30); - s(EmcCmdMappingCmd1_0, 6:0, secure_scratch15, 6:0); - s(EmcCmdMappingCmd1_0, 14:8, secure_scratch15, 13:7); - s(EmcCmdMappingCmd1_0, 22:16, secure_scratch15, 20:14); - s(EmcCmdMappingCmd1_0, 30:24, secure_scratch15, 27:21); - s(McGeneralizedCarveout5BomHi, 1:0, secure_scratch15, 29:28); - s(McGeneralizedCarveout3BomHi, 1:0, secure_scratch15, 31:30); - s(EmcCmdMappingCmd1_1, 6:0, secure_scratch16, 6:0); - s(EmcCmdMappingCmd1_1, 14:8, secure_scratch16, 13:7); - s(EmcCmdMappingCmd1_1, 22:16, secure_scratch16, 20:14); - s(EmcCmdMappingCmd1_1, 30:24, secure_scratch16, 27:21); - s(McGeneralizedCarveout2BomHi, 1:0, secure_scratch16, 29:28); - s(McGeneralizedCarveout4BomHi, 1:0, secure_scratch16, 31:30); - s(EmcCmdMappingCmd2_0, 6:0, secure_scratch17, 6:0); - s(EmcCmdMappingCmd2_0, 14:8, secure_scratch17, 13:7); - s(EmcCmdMappingCmd2_0, 22:16, secure_scratch17, 20:14); - s(EmcCmdMappingCmd2_0, 30:24, secure_scratch17, 27:21); - s(McGeneralizedCarveout1BomHi, 1:0, secure_scratch17, 29:28); - s(EmcAdrCfg, 0:0, secure_scratch17, 30:30); - s(EmcFbioSpare, 1:1, secure_scratch17, 31:31); - s(EmcCmdMappingCmd2_1, 6:0, secure_scratch18, 6:0); - s(EmcCmdMappingCmd2_1, 14:8, secure_scratch18, 13:7); - s(EmcCmdMappingCmd2_1, 22:16, secure_scratch18, 20:14); - s(EmcCmdMappingCmd2_1, 30:24, secure_scratch18, 27:21); - s(EmcFbioCfg8, 15:15, secure_scratch18, 28:28); - s(McEmemAdrCfg, 0:0, secure_scratch18, 29:29); - s(McSecCarveoutProtectWriteAccess, 0:0, secure_scratch18, 30:30); - s(McMtsCarveoutRegCtrl, 0:0, secure_scratch18, 31:31); - s(EmcCmdMappingCmd3_0, 6:0, secure_scratch19, 6:0); - s(EmcCmdMappingCmd3_0, 14:8, secure_scratch19, 13:7); - s(EmcCmdMappingCmd3_0, 22:16, secure_scratch19, 20:14); - s(EmcCmdMappingCmd3_0, 30:24, secure_scratch19, 27:21); - s(McGeneralizedCarveout2Cfg0, 6:3, secure_scratch19, 31:28); - s(EmcCmdMappingCmd3_1, 6:0, secure_scratch20, 6:0); - s(EmcCmdMappingCmd3_1, 14:8, secure_scratch20, 13:7); - s(EmcCmdMappingCmd3_1, 22:16, secure_scratch20, 20:14); - s(EmcCmdMappingCmd3_1, 30:24, secure_scratch20, 27:21); - s(McGeneralizedCarveout2Cfg0, 10:7, secure_scratch20, 31:28); - s(McGeneralizedCarveout4Cfg0, 26:0, secure_scratch39, 26:0); - s(McGeneralizedCarveout2Cfg0, 17:14, secure_scratch39, 30:27); - s(McVideoProtectVprOverride, 0:0, secure_scratch39, 31:31); - s(McGeneralizedCarveout5Cfg0, 26:0, secure_scratch40, 26:0); - s(McGeneralizedCarveout2Cfg0, 21:18, secure_scratch40, 30:27); - s(McVideoProtectVprOverride, 1:1, secure_scratch40, 31:31); - s(EmcCmdMappingCmd0_2, 6:0, secure_scratch41, 6:0); - s(EmcCmdMappingCmd0_2, 14:8, secure_scratch41, 13:7); - s(EmcCmdMappingCmd0_2, 22:16, secure_scratch41, 20:14); - s(EmcCmdMappingCmd0_2, 27:24, secure_scratch41, 24:21); - s(McGeneralizedCarveout1Cfg0, 6:3, secure_scratch41, 28:25); - s(McGeneralizedCarveout2Cfg0, 13:11, secure_scratch41, 31:29); - s(EmcCmdMappingCmd1_2, 6:0, secure_scratch42, 6:0); - s(EmcCmdMappingCmd1_2, 14:8, secure_scratch42, 13:7); - s(EmcCmdMappingCmd1_2, 22:16, secure_scratch42, 20:14); - s(EmcCmdMappingCmd1_2, 27:24, secure_scratch42, 24:21); - s(McGeneralizedCarveout1Cfg0, 13:7, secure_scratch42, 31:25); - s(EmcCmdMappingCmd2_2, 6:0, secure_scratch43, 6:0); - s(EmcCmdMappingCmd2_2, 14:8, secure_scratch43, 13:7); - s(EmcCmdMappingCmd2_2, 22:16, secure_scratch43, 20:14); - s(EmcCmdMappingCmd2_2, 27:24, secure_scratch43, 24:21); - s(McGeneralizedCarveout1Cfg0, 17:14, secure_scratch43, 28:25); - s(McGeneralizedCarveout3Cfg0, 13:11, secure_scratch43, 31:29); - s(EmcCmdMappingCmd3_2, 6:0, secure_scratch44, 6:0); - s(EmcCmdMappingCmd3_2, 14:8, secure_scratch44, 13:7); - s(EmcCmdMappingCmd3_2, 22:16, secure_scratch44, 20:14); - s(EmcCmdMappingCmd3_2, 27:24, secure_scratch44, 24:21); - s(McGeneralizedCarveout1Cfg0, 21:18, secure_scratch44, 28:25); - s(McVideoProtectVprOverride, 3:2, secure_scratch44, 30:29); - s(McVideoProtectVprOverride, 6:6, secure_scratch44, 31:31); - s(McEmemAdrCfgChannelMask, 31:9, secure_scratch45, 22:0); - s(McEmemAdrCfgDev0, 2:0, secure_scratch45, 25:23); - s(McEmemAdrCfgDev0, 9:8, secure_scratch45, 27:26); - s(McEmemAdrCfgDev0, 19:16, secure_scratch45, 31:28); - s(McEmemAdrCfgBankMask0, 31:10, secure_scratch46, 21:0); - s(McEmemAdrCfgDev1, 2:0, secure_scratch46, 24:22); - s(McEmemAdrCfgDev1, 9:8, secure_scratch46, 26:25); - s(McEmemAdrCfgDev1, 19:16, secure_scratch46, 30:27); - s(McVideoProtectVprOverride, 7:7, secure_scratch46, 31:31); - s(McEmemAdrCfgBankMask1, 31:10, secure_scratch47, 21:0); - s(McGeneralizedCarveout3Cfg0, 10:3, secure_scratch47, 29:22); - s(McVideoProtectVprOverride, 9:8, secure_scratch47, 31:30); - s(McEmemAdrCfgBankMask2, 31:10, secure_scratch48, 21:0); - s(McGeneralizedCarveout3Cfg0, 21:14, secure_scratch48, 29:22); - s(McVideoProtectVprOverride, 11:11, secure_scratch48, 30:30); - s(McVideoProtectVprOverride, 14:14, secure_scratch48, 31:31); - s(McVideoProtectGpuOverride1, 15:0, secure_scratch49, 15:0); - s(McEmemCfg, 13:0, secure_scratch49, 29:16); - s(McEmemCfg, 31:31, secure_scratch49, 30:30); - s(McVideoProtectVprOverride, 15:15, secure_scratch49, 31:31); - s(McGeneralizedCarveout3Bom, 31:17, secure_scratch50, 14:0); - s(McGeneralizedCarveout1Bom, 31:17, secure_scratch50, 29:15); - s(McVideoProtectVprOverride, 18:17, secure_scratch50, 31:30); - s(McGeneralizedCarveout4Bom, 31:17, secure_scratch51, 14:0); - s(McGeneralizedCarveout2Bom, 31:17, secure_scratch51, 29:15); - s(McVideoProtectVprOverride, 20:19, secure_scratch51, 31:30); - s(McGeneralizedCarveout5Bom, 31:17, secure_scratch52, 14:0); - s(McVideoProtectBom, 31:20, secure_scratch52, 26:15); - s(McVideoProtectVprOverride, 23:21, secure_scratch52, 29:27); - s(McVideoProtectVprOverride, 26:26, secure_scratch52, 30:30); - s(McVideoProtectVprOverride, 29:29, secure_scratch52, 31:31); - s(McVideoProtectSizeMb, 11:0, secure_scratch53, 11:0); - s(McSecCarveoutBom, 31:20, secure_scratch53, 23:12); - s(McVideoProtectVprOverride, 31:30, secure_scratch53, 25:24); - s(McVideoProtectVprOverride1, 1:0, secure_scratch53, 27:26); - s(McVideoProtectVprOverride1, 7:4, secure_scratch53, 31:28); - s(McSecCarveoutSizeMb, 11:0, secure_scratch54, 11:0); - s(McMtsCarveoutBom, 31:20, secure_scratch54, 23:12); - s(McVideoProtectVprOverride1, 15:8, secure_scratch54, 31:24); - s(McMtsCarveoutSizeMb, 11:0, secure_scratch55, 11:0); - s(McGeneralizedCarveout4Size128kb, 11:0, secure_scratch55, 23:12); - s(McVideoProtectVprOverride1, 16:16, secure_scratch55, 24:24); - s(McGeneralizedCarveout2Cfg0, 2:0, secure_scratch55, 27:25); - s(McGeneralizedCarveout2Cfg0, 25:22, secure_scratch55, 31:28); - s(McGeneralizedCarveout3Size128kb, 11:0, secure_scratch56, 11:0); - s(McGeneralizedCarveout2Size128kb, 11:0, secure_scratch56, 23:12); - s(McGeneralizedCarveout2Cfg0, 26:26, secure_scratch56, 24:24); - s(McGeneralizedCarveout1Cfg0, 2:0, secure_scratch56, 27:25); - s(McGeneralizedCarveout1Cfg0, 25:22, secure_scratch56, 31:28); - s(McGeneralizedCarveout1Size128kb, 11:0, secure_scratch57, 11:0); - s(McGeneralizedCarveout5Size128kb, 11:0, secure_scratch57, 23:12); - s(McGeneralizedCarveout1Cfg0, 26:26, secure_scratch57, 24:24); - s(McGeneralizedCarveout3Cfg0, 2:0, secure_scratch57, 27:25); - s(McGeneralizedCarveout3Cfg0, 25:22, secure_scratch57, 31:28); - s(McGeneralizedCarveout3Cfg0, 26:26, secure_scratch58, 0:0); - - s32(McGeneralizedCarveout1Access0, secure_scratch59); - s32(McGeneralizedCarveout1Access1, secure_scratch60); - s32(McGeneralizedCarveout1Access2, secure_scratch61); - s32(McGeneralizedCarveout1Access3, secure_scratch62); - s32(McGeneralizedCarveout1Access4, secure_scratch63); - s32(McGeneralizedCarveout2Access0, secure_scratch64); - s32(McGeneralizedCarveout2Access1, secure_scratch65); - s32(McGeneralizedCarveout2Access2, secure_scratch66); - s32(McGeneralizedCarveout2Access3, secure_scratch67); - s32(McGeneralizedCarveout2Access4, secure_scratch68); - s32(McGeneralizedCarveout3Access0, secure_scratch69); - s32(McGeneralizedCarveout3Access1, secure_scratch70); - s32(McGeneralizedCarveout3Access2, secure_scratch71); - s32(McGeneralizedCarveout3Access3, secure_scratch72); - s32(McGeneralizedCarveout3Access4, secure_scratch73); - s32(McGeneralizedCarveout4Access0, secure_scratch74); - s32(McGeneralizedCarveout4Access1, secure_scratch75); - s32(McGeneralizedCarveout4Access2, secure_scratch76); - s32(McGeneralizedCarveout4Access3, secure_scratch77); - s32(McGeneralizedCarveout4Access4, secure_scratch78); - s32(McGeneralizedCarveout5Access0, secure_scratch79); - s32(McGeneralizedCarveout5Access1, secure_scratch80); - s32(McGeneralizedCarveout5Access2, secure_scratch81); - s32(McGeneralizedCarveout5Access3, secure_scratch82); - s32(McGeneralizedCarveout1ForceInternalAccess0, secure_scratch84); - s32(McGeneralizedCarveout1ForceInternalAccess1, secure_scratch85); - s32(McGeneralizedCarveout1ForceInternalAccess2, secure_scratch86); - s32(McGeneralizedCarveout1ForceInternalAccess3, secure_scratch87); - s32(McGeneralizedCarveout1ForceInternalAccess4, secure_scratch88); - s32(McGeneralizedCarveout2ForceInternalAccess0, secure_scratch89); - s32(McGeneralizedCarveout2ForceInternalAccess1, secure_scratch90); - s32(McGeneralizedCarveout2ForceInternalAccess2, secure_scratch91); - s32(McGeneralizedCarveout2ForceInternalAccess3, secure_scratch92); - s32(McGeneralizedCarveout2ForceInternalAccess4, secure_scratch93); - s32(McGeneralizedCarveout3ForceInternalAccess0, secure_scratch94); - s32(McGeneralizedCarveout3ForceInternalAccess1, secure_scratch95); - s32(McGeneralizedCarveout3ForceInternalAccess2, secure_scratch96); - s32(McGeneralizedCarveout3ForceInternalAccess3, secure_scratch97); - s32(McGeneralizedCarveout3ForceInternalAccess4, secure_scratch98); - s32(McGeneralizedCarveout4ForceInternalAccess0, secure_scratch99); - s32(McGeneralizedCarveout4ForceInternalAccess1, secure_scratch100); - s32(McGeneralizedCarveout4ForceInternalAccess2, secure_scratch101); - s32(McGeneralizedCarveout4ForceInternalAccess3, secure_scratch102); - s32(McGeneralizedCarveout4ForceInternalAccess4, secure_scratch103); - s32(McGeneralizedCarveout5ForceInternalAccess0, secure_scratch104); - s32(McGeneralizedCarveout5ForceInternalAccess1, secure_scratch105); - s32(McGeneralizedCarveout5ForceInternalAccess2, secure_scratch106); - s32(McGeneralizedCarveout5ForceInternalAccess3, secure_scratch107); - - c32(0, scratch2); - s(PllMInputDivider, 7:0, scratch2, 7:0); - s(PllMFeedbackDivider, 7:0, scratch2, 15:8); - s(PllMPostDivider, 4:0, scratch2, 20:16); - s(PllMKVCO, 0:0, scratch2, 21:21); - s(PllMKCP, 1:0, scratch2, 23:22); - - c32(0, scratch35); - s(PllMSetupControl, 15:0, scratch35, 15:0); - - c32(0, scratch3); - s(PllMInputDivider, 7:0, scratch3, 7:0); - c(0x3e, scratch3, 15:8); - c(0, scratch3, 20:16); - s(PllMKVCO, 0:0, scratch3, 21:21); - s(PllMKCP, 1:0, scratch3, 23:22); - - c32(0, scratch36); - s(PllMSetupControl, 23:0, scratch36, 23:0); - - c32(0, scratch4); - s(PllMStableTime, 9:0, scratch4, 9:0); -} diff --git a/fusee/fusee-primary/src/sdram_lz.inl b/fusee/fusee-primary/src/sdram_lz.inl index f8f46fbd4..b202ad092 100644 --- a/fusee/fusee-primary/src/sdram_lz.inl +++ b/fusee/fusee-primary/src/sdram_lz.inl @@ -1,5 +1,6 @@ /* * Copyright (c) 2018 naehrwert + * Copyright (c) 2018-2020 Atmosphère-NX * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -14,7 +15,7 @@ * along with this program. If not, see . */ -static const uint8_t _dram_cfg_lz[1262] = { +static const uint8_t sdram_params_erista_lz[1262] = { 0x17, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x2C, 0x17, 0x04, 0x09, 0x00, 0x17, 0x04, 0x04, 0x17, 0x08, 0x08, 0x17, 0x10, 0x10, 0x00, 0x00, 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, @@ -122,3 +123,212 @@ static const uint8_t _dram_cfg_lz[1262] = { 0xAC, 0x38, 0x07, 0x17, 0x0D, 0x8E, 0x68, 0xA3, 0x72, 0x17, 0x83, 0x10, 0x8E, 0x68 }; + +static const uint8_t sdram_params_mariko_lz[1727] = { + 0x19, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, + 0x00, 0x2C, 0x19, 0x04, 0x09, 0x00, 0x19, 0x04, 0x04, 0x19, 0x08, 0x08, + 0x19, 0x10, 0x10, 0x19, 0x20, 0x20, 0x19, 0x40, 0x40, 0x19, 0x2A, 0x2A, + 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x19, 0x04, 0x04, 0x19, 0x09, + 0x14, 0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x19, 0x06, 0x0E, + 0x88, 0x19, 0x04, 0x04, 0x00, 0x20, 0x12, 0x19, 0x0A, 0x0C, 0x19, 0x06, + 0x08, 0x00, 0x00, 0xBC, 0xBC, 0xC5, 0xB3, 0x3C, 0x9E, 0x00, 0x00, 0x02, + 0x03, 0xE0, 0xC1, 0x04, 0x04, 0x04, 0x04, 0x19, 0x04, 0x04, 0x19, 0x04, + 0x04, 0x3F, 0x3F, 0x3F, 0x3F, 0x19, 0x04, 0x04, 0x19, 0x04, 0x04, 0x19, + 0x04, 0x38, 0x04, 0x08, 0x00, 0x00, 0x50, 0x50, 0x50, 0x00, 0xA1, 0x01, + 0x00, 0x00, 0x30, 0x19, 0x04, 0x39, 0x10, 0x00, 0x16, 0x00, 0x10, 0x90, + 0x19, 0x06, 0x81, 0x00, 0x19, 0x07, 0x74, 0x03, 0x19, 0x04, 0x04, 0x00, + 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x3A, 0x00, + 0x00, 0x00, 0x1D, 0x19, 0x0B, 0x81, 0x14, 0x09, 0x00, 0x00, 0x00, 0x04, + 0x19, 0x0B, 0x10, 0x0B, 0x19, 0x07, 0x28, 0x08, 0x19, 0x07, 0x0C, 0x19, + 0x04, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x15, 0x19, 0x07, 0x08, 0x1B, 0x19, + 0x07, 0x28, 0x20, 0x00, 0x00, 0x00, 0x06, 0x19, 0x04, 0x04, 0x19, 0x07, + 0x08, 0x19, 0x04, 0x64, 0x19, 0x04, 0x18, 0x19, 0x04, 0x30, 0x19, 0x04, + 0x10, 0x19, 0x08, 0x81, 0x00, 0x19, 0x04, 0x10, 0x19, 0x04, 0x4C, 0x0E, + 0x00, 0x00, 0x00, 0x05, 0x19, 0x07, 0x1C, 0x19, 0x09, 0x82, 0x24, 0x19, + 0x07, 0x6C, 0x19, 0x07, 0x83, 0x57, 0x80, 0x19, 0x04, 0x0A, 0x12, 0x00, + 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x1A, 0x00, 0x00, 0x00, 0x16, 0x19, + 0x07, 0x0C, 0x0A, 0x19, 0x04, 0x48, 0x19, 0x07, 0x61, 0xC1, 0x19, 0x07, + 0x50, 0x19, 0x04, 0x04, 0x19, 0x04, 0x13, 0x19, 0x04, 0x1C, 0x19, 0x04, + 0x08, 0x14, 0x19, 0x07, 0x60, 0x19, 0x08, 0x54, 0x3B, 0x19, 0x04, 0x04, + 0x19, 0x07, 0x14, 0x19, 0x04, 0x04, 0x04, 0x19, 0x07, 0x81, 0x6C, 0x19, + 0x0C, 0x0C, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91, 0x3F, 0x3A, + 0x19, 0x04, 0x5A, 0xF3, 0x0C, 0x04, 0x05, 0x1B, 0x06, 0x02, 0x03, 0x07, + 0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A, 0x24, 0x0B, 0x1E, + 0x0D, 0x0C, 0x26, 0x26, 0x03, 0x02, 0x1B, 0x1C, 0x23, 0x03, 0x04, 0x07, + 0x05, 0x06, 0x25, 0x25, 0x02, 0x0A, 0x0B, 0x1D, 0x0D, 0x08, 0x0C, 0x09, + 0x1E, 0x24, 0x26, 0x26, 0x08, 0x24, 0x06, 0x07, 0x9A, 0x19, 0x05, 0x83, + 0x3F, 0xFF, 0x00, 0xFF, 0x19, 0x10, 0x84, 0x00, 0x04, 0x00, 0x01, 0x88, + 0x00, 0x00, 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0xA0, 0x70, 0xCB, 0xFA, 0xE4, 0xD3, 0xFE, 0x19, 0x82, 0x3A, + 0x90, 0x38, 0x9C, 0x19, 0x84, 0x6F, 0xD2, 0x18, 0x19, 0x82, 0x60, 0xB1, + 0x28, 0x19, 0x85, 0x44, 0xD2, 0x18, 0x19, 0x83, 0x48, 0xB1, 0x28 +}; + +static const uint32_t sdram_params_index_table_erista[28] = { + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, +}; + +static const uint32_t sdram_params_index_table_mariko[28] = { + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0, + 1, + 2, + 3, + 4, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 6, + 8, + 9, + 0xA, + 7, + 6, + 0xB, + 0xB, + 0xB, +}; diff --git a/fusee/fusee-primary/src/sdram_param_t210.h b/fusee/fusee-primary/src/sdram_param_t210.h deleted file mode 100644 index 328ee5109..000000000 --- a/fusee/fusee-primary/src/sdram_param_t210.h +++ /dev/null @@ -1,933 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - * See file CREDITS for list of people who contributed to this - * project. - */ - -/** - * Defines the SDRAM parameter structure. - * - * Note that PLLM is used by EMC. - */ - -#ifndef _SDRAM_PARAM_T210_H_ -#define _SDRAM_PARAM_T210_H_ - -#include - -#define MEMORY_TYPE_NONE 0 -#define MEMORY_TYPE_DDR 0 -#define MEMORY_TYPE_LPDDR 0 -#define MEMORY_TYPE_DDR2 0 -#define MEMORY_TYPE_LPDDR2 1 -#define MEMORY_TYPE_DDR3 2 -#define MEMORY_TYPE_LPDDR4 3 - -/** - * Defines the SDRAM parameter structure - */ -typedef struct _sdram_params -{ - /* Specifies the type of memory device */ - uint32_t memory_type; - - /* MC/EMC clock source configuration */ - - /* Specifies the M value for PllM */ - uint32_t pllm_input_divider; - /* Specifies the N value for PllM */ - uint32_t pllm_feedback_divider; - /* Specifies the time to wait for PLLM to lock (in microseconds) */ - uint32_t pllm_stable_time; - /* Specifies misc. control bits */ - uint32_t pllm_setup_control; - /* Specifies the P value for PLLM */ - uint32_t pllm_post_divider; - /* Specifies value for Charge Pump Gain Control */ - uint32_t pllm_kcp; - /* Specifies VCO gain */ - uint32_t pllm_kvco; - /* Spare BCT param */ - uint32_t emc_bct_spare0; - /* Spare BCT param */ - uint32_t emc_bct_spare1; - /* Spare BCT param */ - uint32_t emc_bct_spare2; - /* Spare BCT param */ - uint32_t emc_bct_spare3; - /* Spare BCT param */ - uint32_t emc_bct_spare4; - /* Spare BCT param */ - uint32_t emc_bct_spare5; - /* Spare BCT param */ - uint32_t emc_bct_spare6; - /* Spare BCT param */ - uint32_t emc_bct_spare7; - /* Spare BCT param */ - uint32_t emc_bct_spare8; - /* Spare BCT param */ - uint32_t emc_bct_spare9; - /* Spare BCT param */ - uint32_t emc_bct_spare10; - /* Spare BCT param */ - uint32_t emc_bct_spare11; - /* Spare BCT param */ - uint32_t emc_bct_spare12; - /* Spare BCT param */ - uint32_t emc_bct_spare13; - - /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ - uint32_t emc_clock_source; - uint32_t emc_clock_source_dll; - - /* Defines possible override for PLLLM_MISC2 */ - uint32_t clk_rst_pllm_misc20_override; - /* enables override for PLLLM_MISC2 */ - uint32_t clk_rst_pllm_misc20_override_enable; - /* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */ - uint32_t clear_clock2_mc1; - - /* Auto-calibration of EMC pads */ - - /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ - uint32_t emc_auto_cal_interval; - /* - * Specifies the value for EMC_AUTO_CAL_CONFIG - * Note: Trigger bits are set by the SDRAM code. - */ - uint32_t emc_auto_cal_config; - - /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ - uint32_t emc_auto_cal_config2; - - /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ - uint32_t emc_auto_cal_config3; - - uint32_t emc_auto_cal_config4; - uint32_t emc_auto_cal_config5; - uint32_t emc_auto_cal_config6; - uint32_t emc_auto_cal_config7; - uint32_t emc_auto_cal_config8; - /* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */ - uint32_t emc_auto_cal_vref_sel0; - uint32_t emc_auto_cal_vref_sel1; - - /* Specifies the value for EMC_AUTO_CAL_CHANNEL */ - uint32_t emc_auto_cal_channel; - - /* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */ - uint32_t emc_pmacro_auto_cal_cfg0; - uint32_t emc_pmacro_auto_cal_cfg1; - uint32_t emc_pmacro_auto_cal_cfg2; - - uint32_t emc_pmacro_rx_term; - uint32_t emc_pmacro_dq_tx_drive; - uint32_t emc_pmacro_ca_tx_drive; - uint32_t emc_pmacro_cmd_tx_drive; - uint32_t emc_pmacro_auto_cal_common; - uint32_t emc_pmacro_zcrtl; - - /* - * Specifies the time for the calibration - * to stabilize (in microseconds) - */ - uint32_t emc_auto_cal_wait; - - uint32_t emc_xm2_comp_pad_ctrl; - uint32_t emc_xm2_comp_pad_ctrl2; - uint32_t emc_xm2_comp_pad_ctrl3; - - /* - * DRAM size information - * Specifies the value for EMC_ADR_CFG - */ - uint32_t emc_adr_cfg; - - /* - * Specifies the time to wait after asserting pin - * CKE (in microseconds) - */ - uint32_t emc_pin_program_wait; - /* Specifies the extra delay before/after pin RESET/CKE command */ - uint32_t emc_pin_extra_wait; - - uint32_t emc_pin_gpio_enable; - uint32_t emc_pin_gpio; - - /* - * Specifies the extra delay after the first writing - * of EMC_TIMING_CONTROL - */ - uint32_t emc_timing_control_wait; - - /* Timing parameters required for the SDRAM */ - - /* Specifies the value for EMC_RC */ - uint32_t emc_rc; - /* Specifies the value for EMC_RFC */ - uint32_t emc_rfc; - - uint32_t emc_rfc_pb; - uint32_t emc_ref_ctrl2; - - /* Specifies the value for EMC_RFC_SLR */ - uint32_t emc_rfc_slr; - /* Specifies the value for EMC_RAS */ - uint32_t emc_ras; - /* Specifies the value for EMC_RP */ - uint32_t emc_rp; - /* Specifies the value for EMC_R2R */ - uint32_t emc_r2r; - /* Specifies the value for EMC_W2W */ - uint32_t emc_w2w; - /* Specifies the value for EMC_R2W */ - uint32_t emc_r2w; - /* Specifies the value for EMC_W2R */ - uint32_t emc_w2r; - /* Specifies the value for EMC_R2P */ - uint32_t emc_r2p; - /* Specifies the value for EMC_W2P */ - uint32_t emc_w2p; - /* Specifies the value for EMC_RD_RCD */ - - uint32_t emc_tppd; - uint32_t emc_ccdmw; - - uint32_t emc_rd_rcd; - /* Specifies the value for EMC_WR_RCD */ - uint32_t emc_wr_rcd; - /* Specifies the value for EMC_RRD */ - uint32_t emc_rrd; - /* Specifies the value for EMC_REXT */ - uint32_t emc_rext; - /* Specifies the value for EMC_WEXT */ - uint32_t emc_wext; - /* Specifies the value for EMC_WDV */ - uint32_t emc_wdv; - - uint32_t emc_wdv_chk; - uint32_t emc_wsv; - uint32_t emc_wev; - - /* Specifies the value for EMC_WDV_MASK */ - uint32_t emc_wdv_mask; - - uint32_t emc_ws_duration; - uint32_t emc_we_duration; - - /* Specifies the value for EMC_QUSE */ - uint32_t emc_quse; - /* Specifies the value for EMC_QUSE_WIDTH */ - uint32_t emc_quse_width; - /* Specifies the value for EMC_IBDLY */ - uint32_t emc_ibdly; - - uint32_t emc_obdly; - - /* Specifies the value for EMC_EINPUT */ - uint32_t emc_einput; - /* Specifies the value for EMC_EINPUT_DURATION */ - uint32_t emc_einput_duration; - /* Specifies the value for EMC_PUTERM_EXTRA */ - uint32_t emc_puterm_extra; - /* Specifies the value for EMC_PUTERM_WIDTH */ - uint32_t emc_puterm_width; - - uint32_t emc_qrst; - uint32_t emc_qsafe; - uint32_t emc_rdv; - uint32_t emc_rdv_mask; - - uint32_t emc_rdv_early; - uint32_t emc_rdv_early_mask; - - /* Specifies the value for EMC_QPOP */ - uint32_t emc_qpop; - - /* Specifies the value for EMC_REFRESH */ - uint32_t emc_refresh; - /* Specifies the value for EMC_BURST_REFRESH_NUM */ - uint32_t emc_burst_refresh_num; - /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ - uint32_t emc_prerefresh_req_cnt; - /* Specifies the value for EMC_PDEX2WR */ - uint32_t emc_pdex2wr; - /* Specifies the value for EMC_PDEX2RD */ - uint32_t emc_pdex2rd; - /* Specifies the value for EMC_PCHG2PDEN */ - uint32_t emc_pchg2pden; - /* Specifies the value for EMC_ACT2PDEN */ - uint32_t emc_act2pden; - /* Specifies the value for EMC_AR2PDEN */ - uint32_t emc_ar2pden; - /* Specifies the value for EMC_RW2PDEN */ - uint32_t emc_rw2pden; - - uint32_t emc_cke2pden; - uint32_t emc_pdex2che; - uint32_t emc_pdex2mrr; - - /* Specifies the value for EMC_TXSR */ - uint32_t emc_txsr; - /* Specifies the value for EMC_TXSRDLL */ - uint32_t emc_txsr_dll; - /* Specifies the value for EMC_TCKE */ - uint32_t emc_tcke; - /* Specifies the value for EMC_TCKESR */ - uint32_t emc_tckesr; - /* Specifies the value for EMC_TPD */ - uint32_t emc_tpd; - /* Specifies the value for EMC_TFAW */ - uint32_t emc_tfaw; - /* Specifies the value for EMC_TRPAB */ - uint32_t emc_trpab; - /* Specifies the value for EMC_TCLKSTABLE */ - uint32_t emc_tclkstable; - /* Specifies the value for EMC_TCLKSTOP */ - uint32_t emc_tclkstop; - /* Specifies the value for EMC_TREFBW */ - uint32_t emc_trefbw; - - /* FBIO configuration values */ - - /* Specifies the value for EMC_FBIO_CFG5 */ - uint32_t emc_fbio_cfg5; - /* Specifies the value for EMC_FBIO_CFG7 */ - uint32_t emc_fbio_cfg7; - uint32_t emc_fbio_cfg8; - - /* Command mapping for CMD brick 0 */ - uint32_t emc_cmd_mapping_cmd0_0; - uint32_t emc_cmd_mapping_cmd0_1; - uint32_t emc_cmd_mapping_cmd0_2; - uint32_t emc_cmd_mapping_cmd1_0; - uint32_t emc_cmd_mapping_cmd1_1; - uint32_t emc_cmd_mapping_cmd1_2; - uint32_t emc_cmd_mapping_cmd2_0; - uint32_t emc_cmd_mapping_cmd2_1; - uint32_t emc_cmd_mapping_cmd2_2; - uint32_t emc_cmd_mapping_cmd3_0; - uint32_t emc_cmd_mapping_cmd3_1; - uint32_t emc_cmd_mapping_cmd3_2; - uint32_t emc_cmd_mapping_byte; - - /* Specifies the value for EMC_FBIO_SPARE */ - uint32_t emc_fbio_spare; - - /* Specifies the value for EMC_CFG_RSV */ - uint32_t emc_cfg_rsv; - - /* MRS command values */ - - /* Specifies the value for EMC_MRS */ - uint32_t emc_mrs; - /* Specifies the MP0 command to initialize mode registers */ - uint32_t emc_emrs; - /* Specifies the MP2 command to initialize mode registers */ - uint32_t emc_emrs2; - /* Specifies the MP3 command to initialize mode registers */ - uint32_t emc_emrs3; - /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ - uint32_t emc_mrw1; - /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ - uint32_t emc_mrw2; - /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ - uint32_t emc_mrw3; - /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ - uint32_t emc_mrw4; - - /* Specifies the programming to LPDDR4 Mode Register 3 at cold boot */ - uint32_t emc_mrw6; - /* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */ - uint32_t emc_mrw8; - /* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */ - uint32_t emc_mrw9; - /* Specifies the programming to LPDDR4 Mode Register 12 at cold boot */ - uint32_t emc_mrw10; - /* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */ - uint32_t emc_mrw12; - /* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */ - uint32_t emc_mrw13; - /* Specifies the programming to LPDDR4 Mode Register 22 at cold boot */ - uint32_t emc_mrw14; - - /* - * Specifies the programming to extra LPDDR2 Mode Register - * at cold boot - */ - uint32_t emc_mrw_extra; - /* - * Specifies the programming to extra LPDDR2 Mode Register - * at warm boot - */ - uint32_t emc_warm_boot_mrw_extra; - /* - * Specify the enable of extra Mode Register programming at - * warm boot - */ - uint32_t emc_warm_boot_extramode_reg_write_enable; - /* - * Specify the enable of extra Mode Register programming at - * cold boot - */ - uint32_t emc_extramode_reg_write_enable; - - /* Specifies the EMC_MRW reset command value */ - uint32_t emc_mrw_reset_command; - /* Specifies the EMC Reset wait time (in microseconds) */ - uint32_t emc_mrw_reset_ninit_wait; - /* Specifies the value for EMC_MRS_WAIT_CNT */ - uint32_t emc_mrs_wait_cnt; - /* Specifies the value for EMC_MRS_WAIT_CNT2 */ - uint32_t emc_mrs_wait_cnt2; - - /* EMC miscellaneous configurations */ - - /* Specifies the value for EMC_CFG */ - uint32_t emc_cfg; - /* Specifies the value for EMC_CFG_2 */ - uint32_t emc_cfg2; - /* Specifies the pipe bypass controls */ - uint32_t emc_cfg_pipe; - - uint32_t emc_cfg_pipe_clk; - uint32_t emc_fdpd_ctrl_cmd_no_ramp; - uint32_t emc_cfg_update; - - /* Specifies the value for EMC_DBG */ - uint32_t emc_dbg; - - uint32_t emc_dbg_write_mux; - - /* Specifies the value for EMC_CMDQ */ - uint32_t emc_cmd_q; - /* Specifies the value for EMC_MC2EMCQ */ - uint32_t emc_mc2emc_q; - /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ - uint32_t emc_dyn_self_ref_control; - - /* Specifies the value for MEM_INIT_DONE */ - uint32_t ahb_arbitration_xbar_ctrl_meminit_done; - - /* Specifies the value for EMC_CFG_DIG_DLL */ - uint32_t emc_cfg_dig_dll; - uint32_t emc_cfg_dig_dll_1; - - /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ - uint32_t emc_cfg_dig_dll_period; - /* Specifies the value of *DEV_SELECTN of various EMC registers */ - uint32_t emc_dev_select; - - /* Specifies the value for EMC_SEL_DPD_CTRL */ - uint32_t emc_sel_dpd_ctrl; - - /* Pads trimmer delays */ - uint32_t emc_fdpd_ctrl_dq; - uint32_t emc_fdpd_ctrl_cmd; - uint32_t emc_pmacro_ib_vref_dq_0; - uint32_t emc_pmacro_ib_vref_dq_1; - uint32_t emc_pmacro_ib_vref_dqs_0; - uint32_t emc_pmacro_ib_vref_dqs_1; - uint32_t emc_pmacro_ib_rxrt; - uint32_t emc_cfg_pipe1; - uint32_t emc_cfg_pipe2; - - /* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */ - uint32_t emc_pmacro_quse_ddll_rank0_0; - uint32_t emc_pmacro_quse_ddll_rank0_1; - uint32_t emc_pmacro_quse_ddll_rank0_2; - uint32_t emc_pmacro_quse_ddll_rank0_3; - uint32_t emc_pmacro_quse_ddll_rank0_4; - uint32_t emc_pmacro_quse_ddll_rank0_5; - uint32_t emc_pmacro_quse_ddll_rank1_0; - uint32_t emc_pmacro_quse_ddll_rank1_1; - uint32_t emc_pmacro_quse_ddll_rank1_2; - uint32_t emc_pmacro_quse_ddll_rank1_3; - uint32_t emc_pmacro_quse_ddll_rank1_4; - uint32_t emc_pmacro_quse_ddll_rank1_5; - - uint32_t emc_pmacro_ob_ddll_long_dq_rank0_0; - uint32_t emc_pmacro_ob_ddll_long_dq_rank0_1; - uint32_t emc_pmacro_ob_ddll_long_dq_rank0_2; - uint32_t emc_pmacro_ob_ddll_long_dq_rank0_3; - uint32_t emc_pmacro_ob_ddll_long_dq_rank0_4; - uint32_t emc_pmacro_ob_ddll_long_dq_rank0_5; - uint32_t emc_pmacro_ob_ddll_long_dq_rank1_0; - uint32_t emc_pmacro_ob_ddll_long_dq_rank1_1; - uint32_t emc_pmacro_ob_ddll_long_dq_rank1_2; - uint32_t emc_pmacro_ob_ddll_long_dq_rank1_3; - uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4; - uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5; - - uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5; - - uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_0; - uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_1; - uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_2; - uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_3; - uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_0; - uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_1; - uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_2; - uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_3; - - uint32_t emc_pmacro_ddll_long_cmd_0; - uint32_t emc_pmacro_ddll_long_cmd_1; - uint32_t emc_pmacro_ddll_long_cmd_2; - uint32_t emc_pmacro_ddll_long_cmd_3; - uint32_t emc_pmacro_ddll_long_cmd_4; - uint32_t emc_pmacro_ddll_short_cmd_0; - uint32_t emc_pmacro_ddll_short_cmd_1; - uint32_t emc_pmacro_ddll_short_cmd_2; - - /* - * Specifies the delay after asserting CKE pin during a WarmBoot0 - * sequence (in microseconds) - */ - uint32_t warm_boot_wait; - - /* Specifies the value for EMC_ODT_WRITE */ - uint32_t emc_odt_write; - - /* Periodic ZQ calibration */ - - /* - * Specifies the value for EMC_ZCAL_INTERVAL - * Value 0 disables ZQ calibration - */ - uint32_t emc_zcal_interval; - /* Specifies the value for EMC_ZCAL_WAIT_CNT */ - uint32_t emc_zcal_wait_cnt; - /* Specifies the value for EMC_ZCAL_MRW_CMD */ - uint32_t emc_zcal_mrw_cmd; - - /* DRAM initialization sequence flow control */ - - /* Specifies the MRS command value for resetting DLL */ - uint32_t emc_mrs_reset_dll; - /* Specifies the command for ZQ initialization of device 0 */ - uint32_t emc_zcal_init_dev0; - /* Specifies the command for ZQ initialization of device 1 */ - uint32_t emc_zcal_init_dev1; - /* - * Specifies the wait time after programming a ZQ initialization - * command (in microseconds) - */ - uint32_t emc_zcal_init_wait; - /* - * Specifies the enable for ZQ calibration at cold boot [bit 0] - * and warm boot [bit 1] - */ - uint32_t emc_zcal_warm_cold_boot_enables; - - /* - * Specifies the MRW command to LPDDR2 for ZQ calibration - * on warmboot - */ - /* Is issued to both devices separately */ - uint32_t emc_mrw_lpddr2zcal_warm_boot; - /* - * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot - * Is issued to both devices separately - */ - uint32_t emc_zqcal_ddr3_warm_boot; - - uint32_t emc_zqcal_lpddr4_warm_boot; - - /* - * Specifies the wait time for ZQ calibration on warmboot - * (in microseconds) - */ - uint32_t emc_zcal_warm_boot_wait; - /* - * Specifies the enable for DRAM Mode Register programming - * at warm boot - */ - uint32_t emc_mrs_warm_boot_enable; - /* - * Specifies the wait time after sending an MRS DLL reset command - * in microseconds) - */ - uint32_t emc_mrs_reset_dll_wait; - /* Specifies the extra MRS command to initialize mode registers */ - uint32_t emc_mrs_extra; - /* Specifies the extra MRS command at warm boot */ - uint32_t emc_warm_boot_mrs_extra; - /* Specifies the EMRS command to enable the DDR2 DLL */ - uint32_t emc_emrs_ddr2_dll_enable; - /* Specifies the MRS command to reset the DDR2 DLL */ - uint32_t emc_mrs_ddr2_dll_reset; - /* Specifies the EMRS command to set OCD calibration */ - uint32_t emc_emrs_ddr2_ocd_calib; - /* - * Specifies the wait between initializing DDR and setting OCD - * calibration (in microseconds) - */ - uint32_t emc_ddr2_wait; - /* Specifies the value for EMC_CLKEN_OVERRIDE */ - uint32_t emc_clken_override; - /* - * Specifies LOG2 of the extra refresh numbers after booting - * Program 0 to disable - */ - uint32_t emc_extra_refresh_num; - /* Specifies the master override for all EMC clocks */ - uint32_t emc_clken_override_allwarm_boot; - /* Specifies the master override for all MC clocks */ - uint32_t mc_clken_override_allwarm_boot; - /* Specifies digital dll period, choosing between 4 to 64 ms */ - uint32_t emc_cfg_dig_dll_period_warm_boot; - - /* Pad controls */ - - /* Specifies the value for PMC_VDDP_SEL */ - uint32_t pmc_vddp_sel; - /* Specifies the wait time after programming PMC_VDDP_SEL */ - uint32_t pmc_vddp_sel_wait; - /* Specifies the value for PMC_DDR_PWR */ - uint32_t pmc_ddr_pwr; - /* Specifies the value for PMC_DDR_CFG */ - uint32_t pmc_ddr_cfg; - /* Specifies the value for PMC_IO_DPD3_REQ */ - uint32_t pmc_io_dpd3_req; - /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ - uint32_t pmc_io_dpd3_req_wait; - - uint32_t pmc_io_dpd4_req_wait; - - /* Specifies the value for PMC_REG_SHORT */ - uint32_t pmc_reg_short; - /* Specifies the value for PMC_NO_IOPOWER */ - uint32_t pmc_no_io_power; - - uint32_t pmc_ddr_ctrl_wait; - uint32_t pmc_ddr_ctrl; - - /* Specifies the value for EMC_ACPD_CONTROL */ - uint32_t emc_acpd_control; - - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ - uint32_t emc_swizzle_rank0_byte0; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ - uint32_t emc_swizzle_rank0_byte1; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ - uint32_t emc_swizzle_rank0_byte2; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ - uint32_t emc_swizzle_rank0_byte3; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ - uint32_t emc_swizzle_rank1_byte0; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ - uint32_t emc_swizzle_rank1_byte1; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ - uint32_t emc_swizzle_rank1_byte2; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ - uint32_t emc_swizzle_rank1_byte3; - - /* Specifies the value for EMC_TXDSRVTTGEN */ - uint32_t emc_txdsrvttgen; - - /* Specifies the value for EMC_DATA_BRLSHFT_0 */ - uint32_t emc_data_brlshft0; - uint32_t emc_data_brlshft1; - - uint32_t emc_dqs_brlshft0; - uint32_t emc_dqs_brlshft1; - - uint32_t emc_cmd_brlshft0; - uint32_t emc_cmd_brlshft1; - uint32_t emc_cmd_brlshft2; - uint32_t emc_cmd_brlshft3; - - uint32_t emc_quse_brlshft0; - uint32_t emc_quse_brlshft1; - uint32_t emc_quse_brlshft2; - uint32_t emc_quse_brlshft3; - - uint32_t emc_dll_cfg0; - uint32_t emc_dll_cfg1; - - uint32_t emc_pmc_scratch1; - uint32_t emc_pmc_scratch2; - uint32_t emc_pmc_scratch3; - - uint32_t emc_pmacro_pad_cfg_ctrl; - - uint32_t emc_pmacro_vttgen_ctrl0; - uint32_t emc_pmacro_vttgen_ctrl1; - uint32_t emc_pmacro_vttgen_ctrl2; - - uint32_t emc_pmacro_brick_ctrl_rfu1; - uint32_t emc_pmacro_cmd_brick_ctrl_fdpd; - uint32_t emc_pmacro_brick_ctrl_rfu2; - uint32_t emc_pmacro_data_brick_ctrl_fdpd; - uint32_t emc_pmacro_bg_bias_ctrl0; - uint32_t emc_pmacro_data_pad_rx_ctrl; - uint32_t emc_pmacro_cmd_pad_rx_ctrl; - uint32_t emc_pmacro_data_rx_term_mode; - uint32_t emc_pmacro_cmd_rx_term_mode; - uint32_t emc_pmacro_data_pad_tx_ctrl; - uint32_t emc_pmacro_common_pad_tx_ctrl; - uint32_t emc_pmacro_cmd_pad_tx_ctrl; - uint32_t emc_cfg3; - - uint32_t emc_pmacro_tx_pwrd0; - uint32_t emc_pmacro_tx_pwrd1; - uint32_t emc_pmacro_tx_pwrd2; - uint32_t emc_pmacro_tx_pwrd3; - uint32_t emc_pmacro_tx_pwrd4; - uint32_t emc_pmacro_tx_pwrd5; - - uint32_t emc_config_sample_delay; - - uint32_t emc_pmacro_brick_mapping0; - uint32_t emc_pmacro_brick_mapping1; - uint32_t emc_pmacro_brick_mapping2; - - uint32_t emc_pmacro_tx_sel_clk_src0; - uint32_t emc_pmacro_tx_sel_clk_src1; - uint32_t emc_pmacro_tx_sel_clk_src2; - uint32_t emc_pmacro_tx_sel_clk_src3; - uint32_t emc_pmacro_tx_sel_clk_src4; - uint32_t emc_pmacro_tx_sel_clk_src5; - - uint32_t emc_pmacro_ddll_bypass; - - uint32_t emc_pmacro_ddll_pwrd0; - uint32_t emc_pmacro_ddll_pwrd1; - uint32_t emc_pmacro_ddll_pwrd2; - - uint32_t emc_pmacro_cmd_ctrl0; - uint32_t emc_pmacro_cmd_ctrl1; - uint32_t emc_pmacro_cmd_ctrl2; - - /* DRAM size information */ - - /* Specifies the value for MC_EMEM_ADR_CFG */ - uint32_t mc_emem_adr_cfg; - /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ - uint32_t mc_emem_adr_cfg_dev0; - /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ - uint32_t mc_emem_adr_cfg_dev1; - - uint32_t mc_emem_adr_cfg_channel_mask; - - /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */ - uint32_t mc_emem_adr_cfg_bank_mask0; - /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ - uint32_t mc_emem_adr_cfg_bank_mask1; - /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ - uint32_t mc_emem_adr_cfg_bank_mask2; - - /* - * Specifies the value for MC_EMEM_CFG which holds the external memory - * size (in KBytes) - */ - uint32_t mc_emem_cfg; - - /* MC arbitration configuration */ - - /* Specifies the value for MC_EMEM_ARB_CFG */ - uint32_t mc_emem_arb_cfg; - /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ - uint32_t mc_emem_arb_outstanding_req; - - uint32_t emc_emem_arb_refpb_hp_ctrl; - uint32_t emc_emem_arb_refpb_bank_ctrl; - - /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ - uint32_t mc_emem_arb_timing_rcd; - /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ - uint32_t mc_emem_arb_timing_rp; - /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ - uint32_t mc_emem_arb_timing_rc; - /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ - uint32_t mc_emem_arb_timing_ras; - /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ - uint32_t mc_emem_arb_timing_faw; - /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ - uint32_t mc_emem_arb_timing_rrd; - /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ - uint32_t mc_emem_arb_timing_rap2pre; - /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ - uint32_t mc_emem_arb_timing_wap2pre; - /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ - uint32_t mc_emem_arb_timing_r2r; - /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ - uint32_t mc_emem_arb_timing_w2w; - /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ - uint32_t mc_emem_arb_timing_r2w; - /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ - uint32_t mc_emem_arb_timing_w2r; - - uint32_t mc_emem_arb_timing_rfcpb; - - /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ - uint32_t mc_emem_arb_da_turns; - /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ - uint32_t mc_emem_arb_da_covers; - /* Specifies the value for MC_EMEM_ARB_MISC0 */ - uint32_t mc_emem_arb_misc0; - /* Specifies the value for MC_EMEM_ARB_MISC1 */ - uint32_t mc_emem_arb_misc1; - uint32_t mc_emem_arb_misc2; - - /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ - uint32_t mc_emem_arb_ring1_throttle; - /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ - uint32_t mc_emem_arb_override; - /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ - uint32_t mc_emem_arb_override1; - /* Specifies the value for MC_EMEM_ARB_RSV */ - uint32_t mc_emem_arb_rsv; - - uint32_t mc_da_cfg0; - uint32_t mc_emem_arb_timing_ccdmw; - - /* Specifies the value for MC_CLKEN_OVERRIDE */ - uint32_t mc_clken_override; - - /* Specifies the value for MC_STAT_CONTROL */ - uint32_t mc_stat_control; - /* Specifies the value for MC_VIDEO_PROTECT_BOM */ - uint32_t mc_video_protect_bom; - /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ - uint32_t mc_video_protect_bom_adr_hi; - /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ - uint32_t mc_video_protect_size_mb; - /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ - uint32_t mc_video_protect_vpr_override; - /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ - uint32_t mc_video_protect_vpr_override1; - /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ - uint32_t mc_video_protect_gpu_override0; - /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ - uint32_t mc_video_protect_gpu_override1; - /* Specifies the value for MC_SEC_CARVEOUT_BOM */ - uint32_t mc_sec_carveout_bom; - /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ - uint32_t mc_sec_carveout_adr_hi; - /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ - uint32_t mc_sec_carveout_size_mb; - /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */ - uint32_t mc_video_protect_write_access; - /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */ - uint32_t mc_sec_carveout_protect_write_access; - - uint32_t mc_generalized_carveout1_bom; - uint32_t mc_generalized_carveout1_bom_hi; - uint32_t mc_generalized_carveout1_size_128kb; - uint32_t mc_generalized_carveout1_access0; - uint32_t mc_generalized_carveout1_access1; - uint32_t mc_generalized_carveout1_access2; - uint32_t mc_generalized_carveout1_access3; - uint32_t mc_generalized_carveout1_access4; - uint32_t mc_generalized_carveout1_force_internal_access0; - uint32_t mc_generalized_carveout1_force_internal_access1; - uint32_t mc_generalized_carveout1_force_internal_access2; - uint32_t mc_generalized_carveout1_force_internal_access3; - uint32_t mc_generalized_carveout1_force_internal_access4; - uint32_t mc_generalized_carveout1_cfg0; - - uint32_t mc_generalized_carveout2_bom; - uint32_t mc_generalized_carveout2_bom_hi; - uint32_t mc_generalized_carveout2_size_128kb; - uint32_t mc_generalized_carveout2_access0; - uint32_t mc_generalized_carveout2_access1; - uint32_t mc_generalized_carveout2_access2; - uint32_t mc_generalized_carveout2_access3; - uint32_t mc_generalized_carveout2_access4; - uint32_t mc_generalized_carveout2_force_internal_access0; - uint32_t mc_generalized_carveout2_force_internal_access1; - uint32_t mc_generalized_carveout2_force_internal_access2; - uint32_t mc_generalized_carveout2_force_internal_access3; - uint32_t mc_generalized_carveout2_force_internal_access4; - uint32_t mc_generalized_carveout2_cfg0; - - uint32_t mc_generalized_carveout3_bom; - uint32_t mc_generalized_carveout3_bom_hi; - uint32_t mc_generalized_carveout3_size_128kb; - uint32_t mc_generalized_carveout3_access0; - uint32_t mc_generalized_carveout3_access1; - uint32_t mc_generalized_carveout3_access2; - uint32_t mc_generalized_carveout3_access3; - uint32_t mc_generalized_carveout3_access4; - uint32_t mc_generalized_carveout3_force_internal_access0; - uint32_t mc_generalized_carveout3_force_internal_access1; - uint32_t mc_generalized_carveout3_force_internal_access2; - uint32_t mc_generalized_carveout3_force_internal_access3; - uint32_t mc_generalized_carveout3_force_internal_access4; - uint32_t mc_generalized_carveout3_cfg0; - - uint32_t mc_generalized_carveout4_bom; - uint32_t mc_generalized_carveout4_bom_hi; - uint32_t mc_generalized_carveout4_size_128kb; - uint32_t mc_generalized_carveout4_access0; - uint32_t mc_generalized_carveout4_access1; - uint32_t mc_generalized_carveout4_access2; - uint32_t mc_generalized_carveout4_access3; - uint32_t mc_generalized_carveout4_access4; - uint32_t mc_generalized_carveout4_force_internal_access0; - uint32_t mc_generalized_carveout4_force_internal_access1; - uint32_t mc_generalized_carveout4_force_internal_access2; - uint32_t mc_generalized_carveout4_force_internal_access3; - uint32_t mc_generalized_carveout4_force_internal_access4; - uint32_t mc_generalized_carveout4_cfg0; - - uint32_t mc_generalized_carveout5_bom; - uint32_t mc_generalized_carveout5_bom_hi; - uint32_t mc_generalized_carveout5_size_128kb; - uint32_t mc_generalized_carveout5_access0; - uint32_t mc_generalized_carveout5_access1; - uint32_t mc_generalized_carveout5_access2; - uint32_t mc_generalized_carveout5_access3; - uint32_t mc_generalized_carveout5_access4; - uint32_t mc_generalized_carveout5_force_internal_access0; - uint32_t mc_generalized_carveout5_force_internal_access1; - uint32_t mc_generalized_carveout5_force_internal_access2; - uint32_t mc_generalized_carveout5_force_internal_access3; - uint32_t mc_generalized_carveout5_force_internal_access4; - uint32_t mc_generalized_carveout5_cfg0; - - /* Specifies enable for CA training */ - uint32_t emc_ca_training_enable; - /* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */ - uint32_t swizzle_rank_byte_encode; - /* Specifies enable and offset for patched boot rom write */ - uint32_t boot_rom_patch_control; - /* Specifies data for patched boot rom write */ - uint32_t boot_rom_patch_data; - - /* Specifies the value for MC_MTS_CARVEOUT_BOM */ - uint32_t mc_mts_carveout_bom; - /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ - uint32_t mc_mts_carveout_adr_hi; - /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ - uint32_t mc_mts_carveout_size_mb; - /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ - uint32_t mc_mts_carveout_reg_ctrl; -} sdram_params_t; - -#endif diff --git a/fusee/fusee-primary/src/sdram_param_t210_lp0.h b/fusee/fusee-primary/src/sdram_param_t210_lp0.h deleted file mode 100644 index 0a1d41840..000000000 --- a/fusee/fusee-primary/src/sdram_param_t210_lp0.h +++ /dev/null @@ -1,964 +0,0 @@ -/* - * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved. - * Copyright 2014 Google Inc. - * Copyright (c) 2018 CTCaer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -/** - * Defines the SDRAM parameter structure. - * - * Note that PLLM is used by EMC. The field names are in camel case to ease - * directly converting BCT config files (*.cfg) into C structure. - */ - -#ifndef __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ -#define __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ - -#include - -enum -{ - /* Specifies the memory type to be undefined */ - NvBootMemoryType_None = 0, - - /* Specifies the memory type to be DDR SDRAM */ - NvBootMemoryType_Ddr = 0, - - /* Specifies the memory type to be LPDDR SDRAM */ - NvBootMemoryType_LpDdr = 0, - - /* Specifies the memory type to be DDR2 SDRAM */ - NvBootMemoryType_Ddr2 = 0, - - /* Specifies the memory type to be LPDDR2 SDRAM */ - NvBootMemoryType_LpDdr2, - - /* Specifies the memory type to be DDR3 SDRAM */ - NvBootMemoryType_Ddr3, - - /* Specifies the memory type to be LPDDR4 SDRAM */ - NvBootMemoryType_LpDdr4, - - NvBootMemoryType_Num, - - /* Specifies an entry in the ram_code table that's not in use */ - NvBootMemoryType_Unused = 0X7FFFFFF, -}; - -/** - * Defines the SDRAM parameter structure - */ -struct sdram_params -{ - - /* Specifies the type of memory device */ - uint32_t MemoryType; - - /* MC/EMC clock source configuration */ - - /* Specifies the M value for PllM */ - uint32_t PllMInputDivider; - /* Specifies the N value for PllM */ - uint32_t PllMFeedbackDivider; - /* Specifies the time to wait for PLLM to lock (in microseconds) */ - uint32_t PllMStableTime; - /* Specifies misc. control bits */ - uint32_t PllMSetupControl; - /* Specifies the P value for PLLM */ - uint32_t PllMPostDivider; - /* Specifies value for Charge Pump Gain Control */ - uint32_t PllMKCP; - /* Specifies VCO gain */ - uint32_t PllMKVCO; - /* Spare BCT param */ - uint32_t EmcBctSpare0; - /* Spare BCT param */ - uint32_t EmcBctSpare1; - /* Spare BCT param */ - uint32_t EmcBctSpare2; - /* Spare BCT param */ - uint32_t EmcBctSpare3; - /* Spare BCT param */ - uint32_t EmcBctSpare4; - /* Spare BCT param */ - uint32_t EmcBctSpare5; - /* Spare BCT param */ - uint32_t EmcBctSpare6; - /* Spare BCT param */ - uint32_t EmcBctSpare7; - /* Spare BCT param */ - uint32_t EmcBctSpare8; - /* Spare BCT param */ - uint32_t EmcBctSpare9; - /* Spare BCT param */ - uint32_t EmcBctSpare10; - /* Spare BCT param */ - uint32_t EmcBctSpare11; - /* Spare BCT param */ - uint32_t EmcBctSpare12; - /* Spare BCT param */ - uint32_t EmcBctSpare13; - - /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ - uint32_t EmcClockSource; - uint32_t EmcClockSourceDll; - - /* Defines possible override for PLLLM_MISC2 */ - uint32_t ClkRstControllerPllmMisc2Override; - /* enables override for PLLLM_MISC2 */ - uint32_t ClkRstControllerPllmMisc2OverrideEnable; - /* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */ - uint32_t ClearClk2Mc1; - - /* Auto-calibration of EMC pads */ - - /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ - uint32_t EmcAutoCalInterval; - /* - * Specifies the value for EMC_AUTO_CAL_CONFIG - * Note: Trigger bits are set by the SDRAM code. - */ - uint32_t EmcAutoCalConfig; - - /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ - uint32_t EmcAutoCalConfig2; - - /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ - uint32_t EmcAutoCalConfig3; - - /* Specifies the values for EMC_AUTO_CAL_CONFIG4-8 */ - uint32_t EmcAutoCalConfig4; - uint32_t EmcAutoCalConfig5; - uint32_t EmcAutoCalConfig6; - uint32_t EmcAutoCalConfig7; - uint32_t EmcAutoCalConfig8; - - /* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */ - uint32_t EmcAutoCalVrefSel0; - uint32_t EmcAutoCalVrefSel1; - - /* Specifies the value for EMC_AUTO_CAL_CHANNEL */ - uint32_t EmcAutoCalChannel; - - /* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */ - uint32_t EmcPmacroAutocalCfg0; - uint32_t EmcPmacroAutocalCfg1; - uint32_t EmcPmacroAutocalCfg2; - uint32_t EmcPmacroRxTerm; - uint32_t EmcPmacroDqTxDrv; - uint32_t EmcPmacroCaTxDrv; - uint32_t EmcPmacroCmdTxDrv; - uint32_t EmcPmacroAutocalCfgCommon; - uint32_t EmcPmacroZctrl; - - /* - * Specifies the time for the calibration - * to stabilize (in microseconds) - */ - uint32_t EmcAutoCalWait; - - uint32_t EmcXm2CompPadCtrl; - uint32_t EmcXm2CompPadCtrl2; - uint32_t EmcXm2CompPadCtrl3; - - /* - * DRAM size information - * Specifies the value for EMC_ADR_CFG - */ - uint32_t EmcAdrCfg; - - /* - * Specifies the time to wait after asserting pin - * CKE (in microseconds) - */ - uint32_t EmcPinProgramWait; - /* Specifies the extra delay before/after pin RESET/CKE command */ - uint32_t EmcPinExtraWait; - - uint32_t EmcPinGpioEn; - uint32_t EmcPinGpio; - - /* - * Specifies the extra delay after the first writing - * of EMC_TIMING_CONTROL - */ - uint32_t EmcTimingControlWait; - - /* Timing parameters required for the SDRAM */ - - /* Specifies the value for EMC_RC */ - uint32_t EmcRc; - /* Specifies the value for EMC_RFC */ - uint32_t EmcRfc; - /* Specifies the value for EMC_RFC_PB */ - uint32_t EmcRfcPb; - /* Specifies the value for EMC_RFC_CTRL2 */ - uint32_t EmcRefctrl2; - /* Specifies the value for EMC_RFC_SLR */ - uint32_t EmcRfcSlr; - /* Specifies the value for EMC_RAS */ - uint32_t EmcRas; - /* Specifies the value for EMC_RP */ - uint32_t EmcRp; - /* Specifies the value for EMC_R2R */ - uint32_t EmcR2r; - /* Specifies the value for EMC_W2W */ - uint32_t EmcW2w; - /* Specifies the value for EMC_R2W */ - uint32_t EmcR2w; - /* Specifies the value for EMC_W2R */ - uint32_t EmcW2r; - /* Specifies the value for EMC_R2P */ - uint32_t EmcR2p; - /* Specifies the value for EMC_W2P */ - uint32_t EmcW2p; - - uint32_t EmcTppd; - uint32_t EmcCcdmw; - - /* Specifies the value for EMC_RD_RCD */ - uint32_t EmcRdRcd; - /* Specifies the value for EMC_WR_RCD */ - uint32_t EmcWrRcd; - /* Specifies the value for EMC_RRD */ - uint32_t EmcRrd; - /* Specifies the value for EMC_REXT */ - uint32_t EmcRext; - /* Specifies the value for EMC_WEXT */ - uint32_t EmcWext; - /* Specifies the value for EMC_WDV */ - uint32_t EmcWdv; - - uint32_t EmcWdvChk; - uint32_t EmcWsv; - uint32_t EmcWev; - - /* Specifies the value for EMC_WDV_MASK */ - uint32_t EmcWdvMask; - - uint32_t EmcWsDuration; - uint32_t EmcWeDuration; - - /* Specifies the value for EMC_QUSE */ - uint32_t EmcQUse; - /* Specifies the value for EMC_QUSE_WIDTH */ - uint32_t EmcQuseWidth; - /* Specifies the value for EMC_IBDLY */ - uint32_t EmcIbdly; - /* Specifies the value for EMC_OBDLY */ - uint32_t EmcObdly; - /* Specifies the value for EMC_EINPUT */ - uint32_t EmcEInput; - /* Specifies the value for EMC_EINPUT_DURATION */ - uint32_t EmcEInputDuration; - /* Specifies the value for EMC_PUTERM_EXTRA */ - uint32_t EmcPutermExtra; - /* Specifies the value for EMC_PUTERM_WIDTH */ - uint32_t EmcPutermWidth; - /* Specifies the value for EMC_PUTERM_ADJ */ - ////uint32_t EmcPutermAdj; - - /* Specifies the value for EMC_QRST */ - uint32_t EmcQRst; - /* Specifies the value for EMC_QSAFE */ - uint32_t EmcQSafe; - /* Specifies the value for EMC_RDV */ - uint32_t EmcRdv; - /* Specifies the value for EMC_RDV_MASK */ - uint32_t EmcRdvMask; - /* Specifies the value for EMC_RDV_EARLY */ - uint32_t EmcRdvEarly; - /* Specifies the value for EMC_RDV_EARLY_MASK */ - uint32_t EmcRdvEarlyMask; - /* Specifies the value for EMC_QPOP */ - uint32_t EmcQpop; - - /* Specifies the value for EMC_REFRESH */ - uint32_t EmcRefresh; - /* Specifies the value for EMC_BURST_REFRESH_NUM */ - uint32_t EmcBurstRefreshNum; - /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ - uint32_t EmcPreRefreshReqCnt; - /* Specifies the value for EMC_PDEX2WR */ - uint32_t EmcPdEx2Wr; - /* Specifies the value for EMC_PDEX2RD */ - uint32_t EmcPdEx2Rd; - /* Specifies the value for EMC_PCHG2PDEN */ - uint32_t EmcPChg2Pden; - /* Specifies the value for EMC_ACT2PDEN */ - uint32_t EmcAct2Pden; - /* Specifies the value for EMC_AR2PDEN */ - uint32_t EmcAr2Pden; - /* Specifies the value for EMC_RW2PDEN */ - uint32_t EmcRw2Pden; - /* Specifies the value for EMC_CKE2PDEN */ - uint32_t EmcCke2Pden; - /* Specifies the value for EMC_PDEX2CKE */ - uint32_t EmcPdex2Cke; - /* Specifies the value for EMC_PDEX2MRR */ - uint32_t EmcPdex2Mrr; - /* Specifies the value for EMC_TXSR */ - uint32_t EmcTxsr; - /* Specifies the value for EMC_TXSRDLL */ - uint32_t EmcTxsrDll; - /* Specifies the value for EMC_TCKE */ - uint32_t EmcTcke; - /* Specifies the value for EMC_TCKESR */ - uint32_t EmcTckesr; - /* Specifies the value for EMC_TPD */ - uint32_t EmcTpd; - /* Specifies the value for EMC_TFAW */ - uint32_t EmcTfaw; - /* Specifies the value for EMC_TRPAB */ - uint32_t EmcTrpab; - /* Specifies the value for EMC_TCLKSTABLE */ - uint32_t EmcTClkStable; - /* Specifies the value for EMC_TCLKSTOP */ - uint32_t EmcTClkStop; - /* Specifies the value for EMC_TREFBW */ - uint32_t EmcTRefBw; - - /* FBIO configuration values */ - - /* Specifies the value for EMC_FBIO_CFG5 */ - uint32_t EmcFbioCfg5; - /* Specifies the value for EMC_FBIO_CFG7 */ - uint32_t EmcFbioCfg7; - /* Specifies the value for EMC_FBIO_CFG8 */ - uint32_t EmcFbioCfg8; - - /* Command mapping for CMD brick 0 */ - uint32_t EmcCmdMappingCmd0_0; - uint32_t EmcCmdMappingCmd0_1; - uint32_t EmcCmdMappingCmd0_2; - uint32_t EmcCmdMappingCmd1_0; - uint32_t EmcCmdMappingCmd1_1; - uint32_t EmcCmdMappingCmd1_2; - uint32_t EmcCmdMappingCmd2_0; - uint32_t EmcCmdMappingCmd2_1; - uint32_t EmcCmdMappingCmd2_2; - uint32_t EmcCmdMappingCmd3_0; - uint32_t EmcCmdMappingCmd3_1; - uint32_t EmcCmdMappingCmd3_2; - uint32_t EmcCmdMappingByte; - - /* Specifies the value for EMC_FBIO_SPARE */ - uint32_t EmcFbioSpare; - - /* Specifies the value for EMC_CFG_RSV */ - uint32_t EmcCfgRsv; - - /* MRS command values */ - - /* Specifies the value for EMC_MRS */ - uint32_t EmcMrs; - /* Specifies the MP0 command to initialize mode registers */ - uint32_t EmcEmrs; - /* Specifies the MP2 command to initialize mode registers */ - uint32_t EmcEmrs2; - /* Specifies the MP3 command to initialize mode registers */ - uint32_t EmcEmrs3; - /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ - uint32_t EmcMrw1; - /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ - uint32_t EmcMrw2; - /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ - uint32_t EmcMrw3; - /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ - uint32_t EmcMrw4; - /* Specifies the programming to LPDDR2 Mode Register 3? at cold boot */ - uint32_t EmcMrw6; - /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ - uint32_t EmcMrw8; - /* Specifies the programming to LPDDR2 Mode Register 11? at cold boot */ - uint32_t EmcMrw9; - /* Specifies the programming to LPDDR2 Mode Register 12 at cold boot */ - uint32_t EmcMrw10; - /* Specifies the programming to LPDDR2 Mode Register 14 at cold boot */ - uint32_t EmcMrw12; - /* Specifies the programming to LPDDR2 Mode Register 14? at cold boot */ - uint32_t EmcMrw13; - /* Specifies the programming to LPDDR2 Mode Register 22 at cold boot */ - uint32_t EmcMrw14; - /* - * Specifies the programming to extra LPDDR2 Mode Register - * at cold boot - */ - uint32_t EmcMrwExtra; - /* - * Specifies the programming to extra LPDDR2 Mode Register - * at warm boot - */ - uint32_t EmcWarmBootMrwExtra; - /* - * Specify the enable of extra Mode Register programming at - * warm boot - */ - uint32_t EmcWarmBootExtraModeRegWriteEnable; - /* - * Specify the enable of extra Mode Register programming at - * cold boot - */ - uint32_t EmcExtraModeRegWriteEnable; - - /* Specifies the EMC_MRW reset command value */ - uint32_t EmcMrwResetCommand; - /* Specifies the EMC Reset wait time (in microseconds) */ - uint32_t EmcMrwResetNInitWait; - /* Specifies the value for EMC_MRS_WAIT_CNT */ - uint32_t EmcMrsWaitCnt; - /* Specifies the value for EMC_MRS_WAIT_CNT2 */ - uint32_t EmcMrsWaitCnt2; - - /* EMC miscellaneous configurations */ - - /* Specifies the value for EMC_CFG */ - uint32_t EmcCfg; - /* Specifies the value for EMC_CFG_2 */ - uint32_t EmcCfg2; - /* Specifies the pipe bypass controls */ - uint32_t EmcCfgPipe; - uint32_t EmcCfgPipeClk; - uint32_t EmcFdpdCtrlCmdNoRamp; - uint32_t EmcCfgUpdate; - - /* Specifies the value for EMC_DBG */ - uint32_t EmcDbg; - uint32_t EmcDbgWriteMux; - - /* Specifies the value for EMC_CMDQ */ - uint32_t EmcCmdQ; - /* Specifies the value for EMC_MC2EMCQ */ - uint32_t EmcMc2EmcQ; - /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ - uint32_t EmcDynSelfRefControl; - - /* Specifies the value for MEM_INIT_DONE */ - uint32_t AhbArbitrationXbarCtrlMemInitDone; - - /* Specifies the value for EMC_CFG_DIG_DLL */ - uint32_t EmcCfgDigDll; - uint32_t EmcCfgDigDll_1; - /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ - uint32_t EmcCfgDigDllPeriod; - /* Specifies the value of *DEV_SELECTN of various EMC registers */ - uint32_t EmcDevSelect; - - /* Specifies the value for EMC_SEL_DPD_CTRL */ - uint32_t EmcSelDpdCtrl; - - /* Pads trimmer delays */ - uint32_t EmcFdpdCtrlDq; - uint32_t EmcFdpdCtrlCmd; - uint32_t EmcPmacroIbVrefDq_0; - uint32_t EmcPmacroIbVrefDq_1; - uint32_t EmcPmacroIbVrefDqs_0; - uint32_t EmcPmacroIbVrefDqs_1; - uint32_t EmcPmacroIbRxrt; - uint32_t EmcCfgPipe1; - uint32_t EmcCfgPipe2; - - /* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */ - uint32_t EmcPmacroQuseDdllRank0_0; - uint32_t EmcPmacroQuseDdllRank0_1; - uint32_t EmcPmacroQuseDdllRank0_2; - uint32_t EmcPmacroQuseDdllRank0_3; - uint32_t EmcPmacroQuseDdllRank0_4; - uint32_t EmcPmacroQuseDdllRank0_5; - uint32_t EmcPmacroQuseDdllRank1_0; - uint32_t EmcPmacroQuseDdllRank1_1; - uint32_t EmcPmacroQuseDdllRank1_2; - uint32_t EmcPmacroQuseDdllRank1_3; - uint32_t EmcPmacroQuseDdllRank1_4; - uint32_t EmcPmacroQuseDdllRank1_5; - - uint32_t EmcPmacroObDdllLongDqRank0_0; - uint32_t EmcPmacroObDdllLongDqRank0_1; - uint32_t EmcPmacroObDdllLongDqRank0_2; - uint32_t EmcPmacroObDdllLongDqRank0_3; - uint32_t EmcPmacroObDdllLongDqRank0_4; - uint32_t EmcPmacroObDdllLongDqRank0_5; - uint32_t EmcPmacroObDdllLongDqRank1_0; - uint32_t EmcPmacroObDdllLongDqRank1_1; - uint32_t EmcPmacroObDdllLongDqRank1_2; - uint32_t EmcPmacroObDdllLongDqRank1_3; - uint32_t EmcPmacroObDdllLongDqRank1_4; - uint32_t EmcPmacroObDdllLongDqRank1_5; - - uint32_t EmcPmacroObDdllLongDqsRank0_0; - uint32_t EmcPmacroObDdllLongDqsRank0_1; - uint32_t EmcPmacroObDdllLongDqsRank0_2; - uint32_t EmcPmacroObDdllLongDqsRank0_3; - uint32_t EmcPmacroObDdllLongDqsRank0_4; - uint32_t EmcPmacroObDdllLongDqsRank0_5; - uint32_t EmcPmacroObDdllLongDqsRank1_0; - uint32_t EmcPmacroObDdllLongDqsRank1_1; - uint32_t EmcPmacroObDdllLongDqsRank1_2; - uint32_t EmcPmacroObDdllLongDqsRank1_3; - uint32_t EmcPmacroObDdllLongDqsRank1_4; - uint32_t EmcPmacroObDdllLongDqsRank1_5; - - uint32_t EmcPmacroIbDdllLongDqsRank0_0; - uint32_t EmcPmacroIbDdllLongDqsRank0_1; - uint32_t EmcPmacroIbDdllLongDqsRank0_2; - uint32_t EmcPmacroIbDdllLongDqsRank0_3; - uint32_t EmcPmacroIbDdllLongDqsRank1_0; - uint32_t EmcPmacroIbDdllLongDqsRank1_1; - uint32_t EmcPmacroIbDdllLongDqsRank1_2; - uint32_t EmcPmacroIbDdllLongDqsRank1_3; - - uint32_t EmcPmacroDdllLongCmd_0; - uint32_t EmcPmacroDdllLongCmd_1; - uint32_t EmcPmacroDdllLongCmd_2; - uint32_t EmcPmacroDdllLongCmd_3; - uint32_t EmcPmacroDdllLongCmd_4; - uint32_t EmcPmacroDdllShortCmd_0; - uint32_t EmcPmacroDdllShortCmd_1; - uint32_t EmcPmacroDdllShortCmd_2; - - /* - * Specifies the delay after asserting CKE pin during a WarmBoot0 - * sequence (in microseconds) - */ - uint32_t WarmBootWait; - - /* Specifies the value for EMC_ODT_WRITE */ - uint32_t EmcOdtWrite; - - /* Periodic ZQ calibration */ - - /* - * Specifies the value for EMC_ZCAL_INTERVAL - * Value 0 disables ZQ calibration - */ - uint32_t EmcZcalInterval; - /* Specifies the value for EMC_ZCAL_WAIT_CNT */ - uint32_t EmcZcalWaitCnt; - /* Specifies the value for EMC_ZCAL_MRW_CMD */ - uint32_t EmcZcalMrwCmd; - - /* DRAM initialization sequence flow control */ - - /* Specifies the MRS command value for resetting DLL */ - uint32_t EmcMrsResetDll; - /* Specifies the command for ZQ initialization of device 0 */ - uint32_t EmcZcalInitDev0; - /* Specifies the command for ZQ initialization of device 1 */ - uint32_t EmcZcalInitDev1; - /* - * Specifies the wait time after programming a ZQ initialization - * command (in microseconds) - */ - uint32_t EmcZcalInitWait; - /* - * Specifies the enable for ZQ calibration at cold boot [bit 0] - * and warm boot [bit 1] - */ - uint32_t EmcZcalWarmColdBootEnables; - - /* - * Specifies the MRW command to LPDDR2 for ZQ calibration - * on warmboot - */ - /* Is issued to both devices separately */ - uint32_t EmcMrwLpddr2ZcalWarmBoot; - /* - * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot - * Is issued to both devices separately - */ - uint32_t EmcZqCalDdr3WarmBoot; - uint32_t EmcZqCalLpDdr4WarmBoot; - /* - * Specifies the wait time for ZQ calibration on warmboot - * (in microseconds) - */ - uint32_t EmcZcalWarmBootWait; - /* - * Specifies the enable for DRAM Mode Register programming - * at warm boot - */ - uint32_t EmcMrsWarmBootEnable; - /* - * Specifies the wait time after sending an MRS DLL reset command - * in microseconds) - */ - uint32_t EmcMrsResetDllWait; - /* Specifies the extra MRS command to initialize mode registers */ - uint32_t EmcMrsExtra; - /* Specifies the extra MRS command at warm boot */ - uint32_t EmcWarmBootMrsExtra; - /* Specifies the EMRS command to enable the DDR2 DLL */ - uint32_t EmcEmrsDdr2DllEnable; - /* Specifies the MRS command to reset the DDR2 DLL */ - uint32_t EmcMrsDdr2DllReset; - /* Specifies the EMRS command to set OCD calibration */ - uint32_t EmcEmrsDdr2OcdCalib; - /* - * Specifies the wait between initializing DDR and setting OCD - * calibration (in microseconds) - */ - uint32_t EmcDdr2Wait; - /* Specifies the value for EMC_CLKEN_OVERRIDE */ - uint32_t EmcClkenOverride; - - /* - * Specifies LOG2 of the extra refresh numbers after booting - * Program 0 to disable - */ - uint32_t EmcExtraRefreshNum; - /* Specifies the master override for all EMC clocks */ - uint32_t EmcClkenOverrideAllWarmBoot; - /* Specifies the master override for all MC clocks */ - uint32_t McClkenOverrideAllWarmBoot; - /* Specifies digital dll period, choosing between 4 to 64 ms */ - uint32_t EmcCfgDigDllPeriodWarmBoot; - - /* Pad controls */ - - /* Specifies the value for PMC_VDDP_SEL */ - uint32_t PmcVddpSel; - /* Specifies the wait time after programming PMC_VDDP_SEL */ - uint32_t PmcVddpSelWait; - /* Specifies the value for PMC_DDR_PWR */ - uint32_t PmcDdrPwr; - /* Specifies the value for PMC_DDR_CFG */ - uint32_t PmcDdrCfg; - /* Specifies the value for PMC_IO_DPD3_REQ */ - uint32_t PmcIoDpd3Req; - /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ - uint32_t PmcIoDpd3ReqWait; - uint32_t PmcIoDpd4ReqWait; - - /* Specifies the value for PMC_REG_SHORT */ - uint32_t PmcRegShort; - /* Specifies the value for PMC_NO_IOPOWER */ - uint32_t PmcNoIoPower; - - uint32_t PmcDdrCntrlWait; - uint32_t PmcDdrCntrl; - - /* Specifies the value for EMC_ACPD_CONTROL */ - uint32_t EmcAcpdControl; - - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */ - ////uint32_t EmcSwizzleRank0ByteCfg; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ - uint32_t EmcSwizzleRank0Byte0; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ - uint32_t EmcSwizzleRank0Byte1; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ - uint32_t EmcSwizzleRank0Byte2; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ - uint32_t EmcSwizzleRank0Byte3; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */ - ////uint32_t EmcSwizzleRank1ByteCfg; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ - uint32_t EmcSwizzleRank1Byte0; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ - uint32_t EmcSwizzleRank1Byte1; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ - uint32_t EmcSwizzleRank1Byte2; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ - uint32_t EmcSwizzleRank1Byte3; - - /* Specifies the value for EMC_TXDSRVTTGEN */ - uint32_t EmcTxdsrvttgen; - - /* Specifies the value for EMC_DATA_BRLSHFT_0 */ - uint32_t EmcDataBrlshft0; - uint32_t EmcDataBrlshft1; - - uint32_t EmcDqsBrlshft0; - uint32_t EmcDqsBrlshft1; - - uint32_t EmcCmdBrlshft0; - uint32_t EmcCmdBrlshft1; - uint32_t EmcCmdBrlshft2; - uint32_t EmcCmdBrlshft3; - - uint32_t EmcQuseBrlshft0; - uint32_t EmcQuseBrlshft1; - uint32_t EmcQuseBrlshft2; - uint32_t EmcQuseBrlshft3; - - uint32_t EmcDllCfg0; - uint32_t EmcDllCfg1; - - uint32_t EmcPmcScratch1; - uint32_t EmcPmcScratch2; - uint32_t EmcPmcScratch3; - - uint32_t EmcPmacroPadCfgCtrl; - - uint32_t EmcPmacroVttgenCtrl0; - uint32_t EmcPmacroVttgenCtrl1; - uint32_t EmcPmacroVttgenCtrl2; - - uint32_t EmcPmacroBrickCtrlRfu1; - uint32_t EmcPmacroCmdBrickCtrlFdpd; - uint32_t EmcPmacroBrickCtrlRfu2; - uint32_t EmcPmacroDataBrickCtrlFdpd; - uint32_t EmcPmacroBgBiasCtrl0; - uint32_t EmcPmacroDataPadRxCtrl; - uint32_t EmcPmacroCmdPadRxCtrl; - uint32_t EmcPmacroDataRxTermMode; - uint32_t EmcPmacroCmdRxTermMode; - uint32_t EmcPmacroDataPadTxCtrl; - uint32_t EmcPmacroCommonPadTxCtrl; - uint32_t EmcPmacroCmdPadTxCtrl; - uint32_t EmcCfg3; - - uint32_t EmcPmacroTxPwrd0; - uint32_t EmcPmacroTxPwrd1; - uint32_t EmcPmacroTxPwrd2; - uint32_t EmcPmacroTxPwrd3; - uint32_t EmcPmacroTxPwrd4; - uint32_t EmcPmacroTxPwrd5; - - uint32_t EmcConfigSampleDelay; - - uint32_t EmcPmacroBrickMapping0; - uint32_t EmcPmacroBrickMapping1; - uint32_t EmcPmacroBrickMapping2; - - uint32_t EmcPmacroTxSelClkSrc0; - uint32_t EmcPmacroTxSelClkSrc1; - uint32_t EmcPmacroTxSelClkSrc2; - uint32_t EmcPmacroTxSelClkSrc3; - uint32_t EmcPmacroTxSelClkSrc4; - uint32_t EmcPmacroTxSelClkSrc5; - - uint32_t EmcPmacroDdllBypass; - - uint32_t EmcPmacroDdllPwrd0; - uint32_t EmcPmacroDdllPwrd1; - uint32_t EmcPmacroDdllPwrd2; - - uint32_t EmcPmacroCmdCtrl0; - uint32_t EmcPmacroCmdCtrl1; - uint32_t EmcPmacroCmdCtrl2; - - /* DRAM size information */ - - /* Specifies the value for MC_EMEM_ADR_CFG */ - uint32_t McEmemAdrCfg; - /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ - uint32_t McEmemAdrCfgDev0; - /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ - uint32_t McEmemAdrCfgDev1; - uint32_t McEmemAdrCfgChannelMask; - - /* Specifies the value for MC_EMEM_BANK_SWIZZLECfg0 */ - uint32_t McEmemAdrCfgBankMask0; - /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ - uint32_t McEmemAdrCfgBankMask1; - /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ - uint32_t McEmemAdrCfgBankMask2; - - /* - * Specifies the value for MC_EMEM_CFG which holds the external memory - * size (in KBytes) - */ - uint32_t McEmemCfg; - - /* MC arbitration configuration */ - - /* Specifies the value for MC_EMEM_ARB_CFG */ - uint32_t McEmemArbCfg; - /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ - uint32_t McEmemArbOutstandingReq; - - uint32_t McEmemArbRefpbHpCtrl; - uint32_t McEmemArbRefpbBankCtrl; - - /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ - uint32_t McEmemArbTimingRcd; - /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ - uint32_t McEmemArbTimingRp; - /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ - uint32_t McEmemArbTimingRc; - /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ - uint32_t McEmemArbTimingRas; - /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ - uint32_t McEmemArbTimingFaw; - /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ - uint32_t McEmemArbTimingRrd; - /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ - uint32_t McEmemArbTimingRap2Pre; - /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ - uint32_t McEmemArbTimingWap2Pre; - /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ - uint32_t McEmemArbTimingR2R; - /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ - uint32_t McEmemArbTimingW2W; - /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ - uint32_t McEmemArbTimingR2W; - /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ - uint32_t McEmemArbTimingW2R; - - uint32_t McEmemArbTimingRFCPB; - - /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ - uint32_t McEmemArbDaTurns; - /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ - uint32_t McEmemArbDaCovers; - /* Specifies the value for MC_EMEM_ARB_MISC0 */ - uint32_t McEmemArbMisc0; - /* Specifies the value for MC_EMEM_ARB_MISC1 */ - uint32_t McEmemArbMisc1; - uint32_t McEmemArbMisc2; - - /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ - uint32_t McEmemArbRing1Throttle; - /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ - uint32_t McEmemArbOverride; - /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ - uint32_t McEmemArbOverride1; - /* Specifies the value for MC_EMEM_ARB_RSV */ - uint32_t McEmemArbRsv; - - uint32_t McDaCfg0; - uint32_t McEmemArbTimingCcdmw; - - /* Specifies the value for MC_CLKEN_OVERRIDE */ - uint32_t McClkenOverride; - - /* Specifies the value for MC_STAT_CONTROL */ - uint32_t McStatControl; - - /* Specifies the value for MC_VIDEO_PROTECT_BOM */ - uint32_t McVideoProtectBom; - /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ - uint32_t McVideoProtectBomAdrHi; - /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ - uint32_t McVideoProtectSizeMb; - /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ - uint32_t McVideoProtectVprOverride; - /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ - uint32_t McVideoProtectVprOverride1; - /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ - uint32_t McVideoProtectGpuOverride0; - /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ - uint32_t McVideoProtectGpuOverride1; - /* Specifies the value for MC_SEC_CARVEOUT_BOM */ - uint32_t McSecCarveoutBom; - /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ - uint32_t McSecCarveoutAdrHi; - /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ - uint32_t McSecCarveoutSizeMb; - /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL. - VIDEO_PROTECT_WRITEAccess */ - uint32_t McVideoProtectWriteAccess; - /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL. - SEC_CARVEOUT_WRITEAccess */ - uint32_t McSecCarveoutProtectWriteAccess; - - /* Write-Protect Regions (WPR) */ - uint32_t McGeneralizedCarveout1Bom; - uint32_t McGeneralizedCarveout1BomHi; - uint32_t McGeneralizedCarveout1Size128kb; - uint32_t McGeneralizedCarveout1Access0; - uint32_t McGeneralizedCarveout1Access1; - uint32_t McGeneralizedCarveout1Access2; - uint32_t McGeneralizedCarveout1Access3; - uint32_t McGeneralizedCarveout1Access4; - uint32_t McGeneralizedCarveout1ForceInternalAccess0; - uint32_t McGeneralizedCarveout1ForceInternalAccess1; - uint32_t McGeneralizedCarveout1ForceInternalAccess2; - uint32_t McGeneralizedCarveout1ForceInternalAccess3; - uint32_t McGeneralizedCarveout1ForceInternalAccess4; - uint32_t McGeneralizedCarveout1Cfg0; - - uint32_t McGeneralizedCarveout2Bom; - uint32_t McGeneralizedCarveout2BomHi; - uint32_t McGeneralizedCarveout2Size128kb; - uint32_t McGeneralizedCarveout2Access0; - uint32_t McGeneralizedCarveout2Access1; - uint32_t McGeneralizedCarveout2Access2; - uint32_t McGeneralizedCarveout2Access3; - uint32_t McGeneralizedCarveout2Access4; - uint32_t McGeneralizedCarveout2ForceInternalAccess0; - uint32_t McGeneralizedCarveout2ForceInternalAccess1; - uint32_t McGeneralizedCarveout2ForceInternalAccess2; - uint32_t McGeneralizedCarveout2ForceInternalAccess3; - uint32_t McGeneralizedCarveout2ForceInternalAccess4; - uint32_t McGeneralizedCarveout2Cfg0; - - uint32_t McGeneralizedCarveout3Bom; - uint32_t McGeneralizedCarveout3BomHi; - uint32_t McGeneralizedCarveout3Size128kb; - uint32_t McGeneralizedCarveout3Access0; - uint32_t McGeneralizedCarveout3Access1; - uint32_t McGeneralizedCarveout3Access2; - uint32_t McGeneralizedCarveout3Access3; - uint32_t McGeneralizedCarveout3Access4; - uint32_t McGeneralizedCarveout3ForceInternalAccess0; - uint32_t McGeneralizedCarveout3ForceInternalAccess1; - uint32_t McGeneralizedCarveout3ForceInternalAccess2; - uint32_t McGeneralizedCarveout3ForceInternalAccess3; - uint32_t McGeneralizedCarveout3ForceInternalAccess4; - uint32_t McGeneralizedCarveout3Cfg0; - - uint32_t McGeneralizedCarveout4Bom; - uint32_t McGeneralizedCarveout4BomHi; - uint32_t McGeneralizedCarveout4Size128kb; - uint32_t McGeneralizedCarveout4Access0; - uint32_t McGeneralizedCarveout4Access1; - uint32_t McGeneralizedCarveout4Access2; - uint32_t McGeneralizedCarveout4Access3; - uint32_t McGeneralizedCarveout4Access4; - uint32_t McGeneralizedCarveout4ForceInternalAccess0; - uint32_t McGeneralizedCarveout4ForceInternalAccess1; - uint32_t McGeneralizedCarveout4ForceInternalAccess2; - uint32_t McGeneralizedCarveout4ForceInternalAccess3; - uint32_t McGeneralizedCarveout4ForceInternalAccess4; - uint32_t McGeneralizedCarveout4Cfg0; - - uint32_t McGeneralizedCarveout5Bom; - uint32_t McGeneralizedCarveout5BomHi; - uint32_t McGeneralizedCarveout5Size128kb; - uint32_t McGeneralizedCarveout5Access0; - uint32_t McGeneralizedCarveout5Access1; - uint32_t McGeneralizedCarveout5Access2; - uint32_t McGeneralizedCarveout5Access3; - uint32_t McGeneralizedCarveout5Access4; - uint32_t McGeneralizedCarveout5ForceInternalAccess0; - uint32_t McGeneralizedCarveout5ForceInternalAccess1; - uint32_t McGeneralizedCarveout5ForceInternalAccess2; - uint32_t McGeneralizedCarveout5ForceInternalAccess3; - uint32_t McGeneralizedCarveout5ForceInternalAccess4; - uint32_t McGeneralizedCarveout5Cfg0; - - /* Specifies enable for CA training */ - uint32_t EmcCaTrainingEnable; - - /* Set if bit 6 select is greater than bit 7 select; uses aremc. - spec packet SWIZZLE_BIT6_GT_BIT7 */ - uint32_t SwizzleRankByteEncode; - /* Specifies enable and offset for patched boot ROM write */ - uint32_t BootRomPatchControl; - /* Specifies data for patched boot ROM write */ - uint32_t BootRomPatchData; - - /* Specifies the value for MC_MTS_CARVEOUT_BOM */ - uint32_t McMtsCarveoutBom; - /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ - uint32_t McMtsCarveoutAdrHi; - /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ - uint32_t McMtsCarveoutSizeMb; - /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ - uint32_t McMtsCarveoutRegCtrl; - - /* End */ -}; - -#endif /* __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ */ diff --git a/fusee/fusee-primary/src/sdram_params.h b/fusee/fusee-primary/src/sdram_params.h new file mode 100644 index 000000000..72e34d4bd --- /dev/null +++ b/fusee/fusee-primary/src/sdram_params.h @@ -0,0 +1,1041 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2020 Atmosphère-NX + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef FUSEE_SDRAM_PARAMS_H_ +#define FUSEE_SDRAM_PARAMS_H_ + +#include + +typedef enum { + NvBootMemoryType_None = 0, + NvBootMemoryType_Ddr = 0, + NvBootMemoryType_LpDdr = 0, + NvBootMemoryType_Ddr2 = 0, + NvBootMemoryType_LpDdr2, + NvBootMemoryType_Ddr3, + NvBootMemoryType_LpDdr4, + NvBootMemoryType_Num, + NvBootMemoryType_Unused = 0X7FFFFFF, +} NvBootMemoryType; + +typedef struct { + NvBootMemoryType MemoryType; + uint32_t PllMInputDivider; + uint32_t PllMFeedbackDivider; + uint32_t PllMStableTime; + uint32_t PllMSetupControl; + uint32_t PllMPostDivider; + uint32_t PllMKCP; + uint32_t PllMKVCO; + uint32_t EmcBctSpare0; + uint32_t EmcBctSpare1; + uint32_t EmcBctSpare2; + uint32_t EmcBctSpare3; + uint32_t EmcBctSpare4; + uint32_t EmcBctSpare5; + uint32_t EmcBctSpare6; + uint32_t EmcBctSpare7; + uint32_t EmcBctSpare8; + uint32_t EmcBctSpare9; + uint32_t EmcBctSpare10; + uint32_t EmcBctSpare11; + uint32_t EmcBctSpare12; + uint32_t EmcBctSpare13; + uint32_t EmcClockSource; + uint32_t EmcClockSourceDll; + uint32_t ClkRstControllerPllmMisc2Override; + uint32_t ClkRstControllerPllmMisc2OverrideEnable; + uint32_t ClearClk2Mc1; + uint32_t EmcAutoCalInterval; + uint32_t EmcAutoCalConfig; + uint32_t EmcAutoCalConfig2; + uint32_t EmcAutoCalConfig3; + uint32_t EmcAutoCalConfig4; + uint32_t EmcAutoCalConfig5; + uint32_t EmcAutoCalConfig6; + uint32_t EmcAutoCalConfig7; + uint32_t EmcAutoCalConfig8; + uint32_t EmcAutoCalVrefSel0; + uint32_t EmcAutoCalVrefSel1; + uint32_t EmcAutoCalChannel; + uint32_t EmcPmacroAutocalCfg0; + uint32_t EmcPmacroAutocalCfg1; + uint32_t EmcPmacroAutocalCfg2; + uint32_t EmcPmacroRxTerm; + uint32_t EmcPmacroDqTxDrv; + uint32_t EmcPmacroCaTxDrv; + uint32_t EmcPmacroCmdTxDrv; + uint32_t EmcPmacroAutocalCfgCommon; + uint32_t EmcPmacroZctrl; + uint32_t EmcAutoCalWait; + uint32_t EmcXm2CompPadCtrl; + uint32_t EmcXm2CompPadCtrl2; + uint32_t EmcXm2CompPadCtrl3; + uint32_t EmcAdrCfg; + uint32_t EmcPinProgramWait; + uint32_t EmcPinExtraWait; + uint32_t EmcPinGpioEn; + uint32_t EmcPinGpio; + uint32_t EmcTimingControlWait; + uint32_t EmcRc; + uint32_t EmcRfc; + uint32_t EmcRfcPb; + uint32_t EmcRefctrl2; + uint32_t EmcRfcSlr; + uint32_t EmcRas; + uint32_t EmcRp; + uint32_t EmcR2r; + uint32_t EmcW2w; + uint32_t EmcR2w; + uint32_t EmcW2r; + uint32_t EmcR2p; + uint32_t EmcW2p; + uint32_t EmcTppd; + uint32_t EmcCcdmw; + uint32_t EmcRdRcd; + uint32_t EmcWrRcd; + uint32_t EmcRrd; + uint32_t EmcRext; + uint32_t EmcWext; + uint32_t EmcWdv; + uint32_t EmcWdvChk; + uint32_t EmcWsv; + uint32_t EmcWev; + uint32_t EmcWdvMask; + uint32_t EmcWsDuration; + uint32_t EmcWeDuration; + uint32_t EmcQUse; + uint32_t EmcQuseWidth; + uint32_t EmcIbdly; + uint32_t EmcObdly; + uint32_t EmcEInput; + uint32_t EmcEInputDuration; + uint32_t EmcPutermExtra; + uint32_t EmcPutermWidth; + uint32_t EmcQRst; + uint32_t EmcQSafe; + uint32_t EmcRdv; + uint32_t EmcRdvMask; + uint32_t EmcRdvEarly; + uint32_t EmcRdvEarlyMask; + uint32_t EmcQpop; + uint32_t EmcRefresh; + uint32_t EmcBurstRefreshNum; + uint32_t EmcPreRefreshReqCnt; + uint32_t EmcPdEx2Wr; + uint32_t EmcPdEx2Rd; + uint32_t EmcPChg2Pden; + uint32_t EmcAct2Pden; + uint32_t EmcAr2Pden; + uint32_t EmcRw2Pden; + uint32_t EmcCke2Pden; + uint32_t EmcPdex2Cke; + uint32_t EmcPdex2Mrr; + uint32_t EmcTxsr; + uint32_t EmcTxsrDll; + uint32_t EmcTcke; + uint32_t EmcTckesr; + uint32_t EmcTpd; + uint32_t EmcTfaw; + uint32_t EmcTrpab; + uint32_t EmcTClkStable; + uint32_t EmcTClkStop; + uint32_t EmcTRefBw; + uint32_t EmcFbioCfg5; + uint32_t EmcFbioCfg7; + uint32_t EmcFbioCfg8; + uint32_t EmcCmdMappingCmd0_0; + uint32_t EmcCmdMappingCmd0_1; + uint32_t EmcCmdMappingCmd0_2; + uint32_t EmcCmdMappingCmd1_0; + uint32_t EmcCmdMappingCmd1_1; + uint32_t EmcCmdMappingCmd1_2; + uint32_t EmcCmdMappingCmd2_0; + uint32_t EmcCmdMappingCmd2_1; + uint32_t EmcCmdMappingCmd2_2; + uint32_t EmcCmdMappingCmd3_0; + uint32_t EmcCmdMappingCmd3_1; + uint32_t EmcCmdMappingCmd3_2; + uint32_t EmcCmdMappingByte; + uint32_t EmcFbioSpare; + uint32_t EmcCfgRsv; + uint32_t EmcMrs; + uint32_t EmcEmrs; + uint32_t EmcEmrs2; + uint32_t EmcEmrs3; + uint32_t EmcMrw1; + uint32_t EmcMrw2; + uint32_t EmcMrw3; + uint32_t EmcMrw4; + uint32_t EmcMrw6; + uint32_t EmcMrw8; + uint32_t EmcMrw9; + uint32_t EmcMrw10; + uint32_t EmcMrw12; + uint32_t EmcMrw13; + uint32_t EmcMrw14; + uint32_t EmcMrwExtra; + uint32_t EmcWarmBootMrwExtra; + uint32_t EmcWarmBootExtraModeRegWriteEnable; + uint32_t EmcExtraModeRegWriteEnable; + uint32_t EmcMrwResetCommand; + uint32_t EmcMrwResetNInitWait; + uint32_t EmcMrsWaitCnt; + uint32_t EmcMrsWaitCnt2; + uint32_t EmcCfg; + uint32_t EmcCfg2; + uint32_t EmcCfgPipe; + uint32_t EmcCfgPipeClk; + uint32_t EmcFdpdCtrlCmdNoRamp; + uint32_t EmcCfgUpdate; + uint32_t EmcDbg; + uint32_t EmcDbgWriteMux; + uint32_t EmcCmdQ; + uint32_t EmcMc2EmcQ; + uint32_t EmcDynSelfRefControl; + uint32_t AhbArbitrationXbarCtrlMemInitDone; + uint32_t EmcCfgDigDll; + uint32_t EmcCfgDigDll_1; + uint32_t EmcCfgDigDllPeriod; + uint32_t EmcDevSelect; + uint32_t EmcSelDpdCtrl; + uint32_t EmcFdpdCtrlDq; + uint32_t EmcFdpdCtrlCmd; + uint32_t EmcPmacroIbVrefDq_0; + uint32_t EmcPmacroIbVrefDq_1; + uint32_t EmcPmacroIbVrefDqs_0; + uint32_t EmcPmacroIbVrefDqs_1; + uint32_t EmcPmacroIbRxrt; + uint32_t EmcCfgPipe1; + uint32_t EmcCfgPipe2; + uint32_t EmcPmacroQuseDdllRank0_0; + uint32_t EmcPmacroQuseDdllRank0_1; + uint32_t EmcPmacroQuseDdllRank0_2; + uint32_t EmcPmacroQuseDdllRank0_3; + uint32_t EmcPmacroQuseDdllRank0_4; + uint32_t EmcPmacroQuseDdllRank0_5; + uint32_t EmcPmacroQuseDdllRank1_0; + uint32_t EmcPmacroQuseDdllRank1_1; + uint32_t EmcPmacroQuseDdllRank1_2; + uint32_t EmcPmacroQuseDdllRank1_3; + uint32_t EmcPmacroQuseDdllRank1_4; + uint32_t EmcPmacroQuseDdllRank1_5; + uint32_t EmcPmacroObDdllLongDqRank0_0; + uint32_t EmcPmacroObDdllLongDqRank0_1; + uint32_t EmcPmacroObDdllLongDqRank0_2; + uint32_t EmcPmacroObDdllLongDqRank0_3; + uint32_t EmcPmacroObDdllLongDqRank0_4; + uint32_t EmcPmacroObDdllLongDqRank0_5; + uint32_t EmcPmacroObDdllLongDqRank1_0; + uint32_t EmcPmacroObDdllLongDqRank1_1; + uint32_t EmcPmacroObDdllLongDqRank1_2; + uint32_t EmcPmacroObDdllLongDqRank1_3; + uint32_t EmcPmacroObDdllLongDqRank1_4; + uint32_t EmcPmacroObDdllLongDqRank1_5; + uint32_t EmcPmacroObDdllLongDqsRank0_0; + uint32_t EmcPmacroObDdllLongDqsRank0_1; + uint32_t EmcPmacroObDdllLongDqsRank0_2; + uint32_t EmcPmacroObDdllLongDqsRank0_3; + uint32_t EmcPmacroObDdllLongDqsRank0_4; + uint32_t EmcPmacroObDdllLongDqsRank0_5; + uint32_t EmcPmacroObDdllLongDqsRank1_0; + uint32_t EmcPmacroObDdllLongDqsRank1_1; + uint32_t EmcPmacroObDdllLongDqsRank1_2; + uint32_t EmcPmacroObDdllLongDqsRank1_3; + uint32_t EmcPmacroObDdllLongDqsRank1_4; + uint32_t EmcPmacroObDdllLongDqsRank1_5; + uint32_t EmcPmacroIbDdllLongDqsRank0_0; + uint32_t EmcPmacroIbDdllLongDqsRank0_1; + uint32_t EmcPmacroIbDdllLongDqsRank0_2; + uint32_t EmcPmacroIbDdllLongDqsRank0_3; + uint32_t EmcPmacroIbDdllLongDqsRank1_0; + uint32_t EmcPmacroIbDdllLongDqsRank1_1; + uint32_t EmcPmacroIbDdllLongDqsRank1_2; + uint32_t EmcPmacroIbDdllLongDqsRank1_3; + uint32_t EmcPmacroDdllLongCmd_0; + uint32_t EmcPmacroDdllLongCmd_1; + uint32_t EmcPmacroDdllLongCmd_2; + uint32_t EmcPmacroDdllLongCmd_3; + uint32_t EmcPmacroDdllLongCmd_4; + uint32_t EmcPmacroDdllShortCmd_0; + uint32_t EmcPmacroDdllShortCmd_1; + uint32_t EmcPmacroDdllShortCmd_2; + uint32_t WarmBootWait; + uint32_t EmcOdtWrite; + uint32_t EmcZcalInterval; + uint32_t EmcZcalWaitCnt; + uint32_t EmcZcalMrwCmd; + uint32_t EmcMrsResetDll; + uint32_t EmcZcalInitDev0; + uint32_t EmcZcalInitDev1; + uint32_t EmcZcalInitWait; + uint32_t EmcZcalWarmColdBootEnables; + uint32_t EmcMrwLpddr2ZcalWarmBoot; + uint32_t EmcZqCalDdr3WarmBoot; + uint32_t EmcZqCalLpDdr4WarmBoot; + uint32_t EmcZcalWarmBootWait; + uint32_t EmcMrsWarmBootEnable; + uint32_t EmcMrsResetDllWait; + uint32_t EmcMrsExtra; + uint32_t EmcWarmBootMrsExtra; + uint32_t EmcEmrsDdr2DllEnable; + uint32_t EmcMrsDdr2DllReset; + uint32_t EmcEmrsDdr2OcdCalib; + uint32_t EmcDdr2Wait; + uint32_t EmcClkenOverride; + uint32_t EmcExtraRefreshNum; + uint32_t EmcClkenOverrideAllWarmBoot; + uint32_t McClkenOverrideAllWarmBoot; + uint32_t EmcCfgDigDllPeriodWarmBoot; + uint32_t PmcVddpSel; + uint32_t PmcVddpSelWait; + uint32_t PmcDdrPwr; + uint32_t PmcDdrCfg; + uint32_t PmcIoDpd3Req; + uint32_t PmcIoDpd3ReqWait; + uint32_t PmcIoDpd4ReqWait; + uint32_t PmcRegShort; + uint32_t PmcNoIoPower; + uint32_t PmcDdrCntrlWait; + uint32_t PmcDdrCntrl; + uint32_t EmcAcpdControl; + uint32_t EmcSwizzleRank0Byte0; + uint32_t EmcSwizzleRank0Byte1; + uint32_t EmcSwizzleRank0Byte2; + uint32_t EmcSwizzleRank0Byte3; + uint32_t EmcSwizzleRank1Byte0; + uint32_t EmcSwizzleRank1Byte1; + uint32_t EmcSwizzleRank1Byte2; + uint32_t EmcSwizzleRank1Byte3; + uint32_t EmcTxdsrvttgen; + uint32_t EmcDataBrlshft0; + uint32_t EmcDataBrlshft1; + uint32_t EmcDqsBrlshft0; + uint32_t EmcDqsBrlshft1; + uint32_t EmcCmdBrlshft0; + uint32_t EmcCmdBrlshft1; + uint32_t EmcCmdBrlshft2; + uint32_t EmcCmdBrlshft3; + uint32_t EmcQuseBrlshft0; + uint32_t EmcQuseBrlshft1; + uint32_t EmcQuseBrlshft2; + uint32_t EmcQuseBrlshft3; + uint32_t EmcDllCfg0; + uint32_t EmcDllCfg1; + uint32_t EmcPmcScratch1; + uint32_t EmcPmcScratch2; + uint32_t EmcPmcScratch3; + uint32_t EmcPmacroPadCfgCtrl; + uint32_t EmcPmacroVttgenCtrl0; + uint32_t EmcPmacroVttgenCtrl1; + uint32_t EmcPmacroVttgenCtrl2; + uint32_t EmcPmacroBrickCtrlRfu1; + uint32_t EmcPmacroCmdBrickCtrlFdpd; + uint32_t EmcPmacroBrickCtrlRfu2; + uint32_t EmcPmacroDataBrickCtrlFdpd; + uint32_t EmcPmacroBgBiasCtrl0; + uint32_t EmcPmacroDataPadRxCtrl; + uint32_t EmcPmacroCmdPadRxCtrl; + uint32_t EmcPmacroDataRxTermMode; + uint32_t EmcPmacroCmdRxTermMode; + uint32_t EmcPmacroDataPadTxCtrl; + uint32_t EmcPmacroCommonPadTxCtrl; + uint32_t EmcPmacroCmdPadTxCtrl; + uint32_t EmcCfg3; + uint32_t EmcPmacroTxPwrd0; + uint32_t EmcPmacroTxPwrd1; + uint32_t EmcPmacroTxPwrd2; + uint32_t EmcPmacroTxPwrd3; + uint32_t EmcPmacroTxPwrd4; + uint32_t EmcPmacroTxPwrd5; + uint32_t EmcConfigSampleDelay; + uint32_t EmcPmacroBrickMapping0; + uint32_t EmcPmacroBrickMapping1; + uint32_t EmcPmacroBrickMapping2; + uint32_t EmcPmacroTxSelClkSrc0; + uint32_t EmcPmacroTxSelClkSrc1; + uint32_t EmcPmacroTxSelClkSrc2; + uint32_t EmcPmacroTxSelClkSrc3; + uint32_t EmcPmacroTxSelClkSrc4; + uint32_t EmcPmacroTxSelClkSrc5; + uint32_t EmcPmacroDdllBypass; + uint32_t EmcPmacroDdllPwrd0; + uint32_t EmcPmacroDdllPwrd1; + uint32_t EmcPmacroDdllPwrd2; + uint32_t EmcPmacroCmdCtrl0; + uint32_t EmcPmacroCmdCtrl1; + uint32_t EmcPmacroCmdCtrl2; + uint32_t McEmemAdrCfg; + uint32_t McEmemAdrCfgDev0; + uint32_t McEmemAdrCfgDev1; + uint32_t McEmemAdrCfgChannelMask; + uint32_t McEmemAdrCfgBankMask0; + uint32_t McEmemAdrCfgBankMask1; + uint32_t McEmemAdrCfgBankMask2; + uint32_t McEmemCfg; + uint32_t McEmemArbCfg; + uint32_t McEmemArbOutstandingReq; + uint32_t McEmemArbRefpbHpCtrl; + uint32_t McEmemArbRefpbBankCtrl; + uint32_t McEmemArbTimingRcd; + uint32_t McEmemArbTimingRp; + uint32_t McEmemArbTimingRc; + uint32_t McEmemArbTimingRas; + uint32_t McEmemArbTimingFaw; + uint32_t McEmemArbTimingRrd; + uint32_t McEmemArbTimingRap2Pre; + uint32_t McEmemArbTimingWap2Pre; + uint32_t McEmemArbTimingR2R; + uint32_t McEmemArbTimingW2W; + uint32_t McEmemArbTimingR2W; + uint32_t McEmemArbTimingW2R; + uint32_t McEmemArbTimingRFCPB; + uint32_t McEmemArbDaTurns; + uint32_t McEmemArbDaCovers; + uint32_t McEmemArbMisc0; + uint32_t McEmemArbMisc1; + uint32_t McEmemArbMisc2; + uint32_t McEmemArbRing1Throttle; + uint32_t McEmemArbOverride; + uint32_t McEmemArbOverride1; + uint32_t McEmemArbRsv; + uint32_t McDaCfg0; + uint32_t McEmemArbTimingCcdmw; + uint32_t McClkenOverride; + uint32_t McStatControl; + uint32_t McVideoProtectBom; + uint32_t McVideoProtectBomAdrHi; + uint32_t McVideoProtectSizeMb; + uint32_t McVideoProtectVprOverride; + uint32_t McVideoProtectVprOverride1; + uint32_t McVideoProtectGpuOverride0; + uint32_t McVideoProtectGpuOverride1; + uint32_t McSecCarveoutBom; + uint32_t McSecCarveoutAdrHi; + uint32_t McSecCarveoutSizeMb; + uint32_t McVideoProtectWriteAccess; + uint32_t McSecCarveoutProtectWriteAccess; + uint32_t McGeneralizedCarveout1Bom; + uint32_t McGeneralizedCarveout1BomHi; + uint32_t McGeneralizedCarveout1Size128kb; + uint32_t McGeneralizedCarveout1Access0; + uint32_t McGeneralizedCarveout1Access1; + uint32_t McGeneralizedCarveout1Access2; + uint32_t McGeneralizedCarveout1Access3; + uint32_t McGeneralizedCarveout1Access4; + uint32_t McGeneralizedCarveout1ForceInternalAccess0; + uint32_t McGeneralizedCarveout1ForceInternalAccess1; + uint32_t McGeneralizedCarveout1ForceInternalAccess2; + uint32_t McGeneralizedCarveout1ForceInternalAccess3; + uint32_t McGeneralizedCarveout1ForceInternalAccess4; + uint32_t McGeneralizedCarveout1Cfg0; + uint32_t McGeneralizedCarveout2Bom; + uint32_t McGeneralizedCarveout2BomHi; + uint32_t McGeneralizedCarveout2Size128kb; + uint32_t McGeneralizedCarveout2Access0; + uint32_t McGeneralizedCarveout2Access1; + uint32_t McGeneralizedCarveout2Access2; + uint32_t McGeneralizedCarveout2Access3; + uint32_t McGeneralizedCarveout2Access4; + uint32_t McGeneralizedCarveout2ForceInternalAccess0; + uint32_t McGeneralizedCarveout2ForceInternalAccess1; + uint32_t McGeneralizedCarveout2ForceInternalAccess2; + uint32_t McGeneralizedCarveout2ForceInternalAccess3; + uint32_t McGeneralizedCarveout2ForceInternalAccess4; + uint32_t McGeneralizedCarveout2Cfg0; + uint32_t McGeneralizedCarveout3Bom; + uint32_t McGeneralizedCarveout3BomHi; + uint32_t McGeneralizedCarveout3Size128kb; + uint32_t McGeneralizedCarveout3Access0; + uint32_t McGeneralizedCarveout3Access1; + uint32_t McGeneralizedCarveout3Access2; + uint32_t McGeneralizedCarveout3Access3; + uint32_t McGeneralizedCarveout3Access4; + uint32_t McGeneralizedCarveout3ForceInternalAccess0; + uint32_t McGeneralizedCarveout3ForceInternalAccess1; + uint32_t McGeneralizedCarveout3ForceInternalAccess2; + uint32_t McGeneralizedCarveout3ForceInternalAccess3; + uint32_t McGeneralizedCarveout3ForceInternalAccess4; + uint32_t McGeneralizedCarveout3Cfg0; + uint32_t McGeneralizedCarveout4Bom; + uint32_t McGeneralizedCarveout4BomHi; + uint32_t McGeneralizedCarveout4Size128kb; + uint32_t McGeneralizedCarveout4Access0; + uint32_t McGeneralizedCarveout4Access1; + uint32_t McGeneralizedCarveout4Access2; + uint32_t McGeneralizedCarveout4Access3; + uint32_t McGeneralizedCarveout4Access4; + uint32_t McGeneralizedCarveout4ForceInternalAccess0; + uint32_t McGeneralizedCarveout4ForceInternalAccess1; + uint32_t McGeneralizedCarveout4ForceInternalAccess2; + uint32_t McGeneralizedCarveout4ForceInternalAccess3; + uint32_t McGeneralizedCarveout4ForceInternalAccess4; + uint32_t McGeneralizedCarveout4Cfg0; + uint32_t McGeneralizedCarveout5Bom; + uint32_t McGeneralizedCarveout5BomHi; + uint32_t McGeneralizedCarveout5Size128kb; + uint32_t McGeneralizedCarveout5Access0; + uint32_t McGeneralizedCarveout5Access1; + uint32_t McGeneralizedCarveout5Access2; + uint32_t McGeneralizedCarveout5Access3; + uint32_t McGeneralizedCarveout5Access4; + uint32_t McGeneralizedCarveout5ForceInternalAccess0; + uint32_t McGeneralizedCarveout5ForceInternalAccess1; + uint32_t McGeneralizedCarveout5ForceInternalAccess2; + uint32_t McGeneralizedCarveout5ForceInternalAccess3; + uint32_t McGeneralizedCarveout5ForceInternalAccess4; + uint32_t McGeneralizedCarveout5Cfg0; + uint32_t EmcCaTrainingEnable; + uint32_t SwizzleRankByteEncode; + uint32_t BootRomPatchControl; + uint32_t BootRomPatchData; + uint32_t McMtsCarveoutBom; + uint32_t McMtsCarveoutAdrHi; + uint32_t McMtsCarveoutSizeMb; + uint32_t McMtsCarveoutRegCtrl; +} sdram_params_erista_t; + +typedef struct { + NvBootMemoryType MemoryType; + uint32_t PllMInputDivider; + uint32_t PllMFeedbackDivider; + uint32_t PllMStableTime; + uint32_t PllMSetupControl; + uint32_t PllMPostDivider; + uint32_t PllMKCP; + uint32_t PllMKVCO; + uint32_t EmcBctSpare0; + uint32_t EmcBctSpare1; + uint32_t EmcBctSpare2; + uint32_t EmcBctSpare3; + uint32_t EmcBctSpare4; + uint32_t EmcBctSpare5; + uint32_t EmcBctSpare6; + uint32_t EmcBctSpare7; + uint32_t EmcBctSpare8; + uint32_t EmcBctSpare9; + uint32_t EmcBctSpare10; + uint32_t EmcBctSpare11; + uint32_t EmcBctSpare12; + uint32_t EmcBctSpare13; + uint32_t EmcBctSpareSecure0; + uint32_t EmcBctSpareSecure1; + uint32_t EmcBctSpareSecure2; + uint32_t EmcBctSpareSecure3; + uint32_t EmcBctSpareSecure4; + uint32_t EmcBctSpareSecure5; + uint32_t EmcBctSpareSecure6; + uint32_t EmcBctSpareSecure7; + uint32_t EmcBctSpareSecure8; + uint32_t EmcBctSpareSecure9; + uint32_t EmcBctSpareSecure10; + uint32_t EmcBctSpareSecure11; + uint32_t EmcBctSpareSecure12; + uint32_t EmcBctSpareSecure13; + uint32_t EmcBctSpareSecure14; + uint32_t EmcBctSpareSecure15; + uint32_t EmcBctSpareSecure16; + uint32_t EmcBctSpareSecure17; + uint32_t EmcBctSpareSecure18; + uint32_t EmcBctSpareSecure19; + uint32_t EmcBctSpareSecure20; + uint32_t EmcBctSpareSecure21; + uint32_t EmcBctSpareSecure22; + uint32_t EmcBctSpareSecure23; + uint32_t EmcClockSource; + uint32_t EmcClockSourceDll; + uint32_t ClkRstControllerPllmMisc2Override; + uint32_t ClkRstControllerPllmMisc2OverrideEnable; + uint32_t ClearClk2Mc1; + uint32_t EmcAutoCalInterval; + uint32_t EmcAutoCalConfig; + uint32_t EmcAutoCalConfig2; + uint32_t EmcAutoCalConfig3; + uint32_t EmcAutoCalConfig4; + uint32_t EmcAutoCalConfig5; + uint32_t EmcAutoCalConfig6; + uint32_t EmcAutoCalConfig7; + uint32_t EmcAutoCalConfig8; + uint32_t EmcAutoCalConfig9; + uint32_t EmcAutoCalVrefSel0; + uint32_t EmcAutoCalVrefSel1; + uint32_t EmcAutoCalChannel; + uint32_t EmcPmacroAutocalCfg0; + uint32_t EmcPmacroAutocalCfg1; + uint32_t EmcPmacroAutocalCfg2; + uint32_t EmcPmacroRxTerm; + uint32_t EmcPmacroDqTxDrv; + uint32_t EmcPmacroCaTxDrv; + uint32_t EmcPmacroCmdTxDrv; + uint32_t EmcPmacroAutocalCfgCommon; + uint32_t EmcPmacroZctrl; + uint32_t EmcAutoCalWait; + uint32_t EmcXm2CompPadCtrl; + uint32_t EmcXm2CompPadCtrl2; + uint32_t EmcXm2CompPadCtrl3; + uint32_t EmcAdrCfg; + uint32_t EmcPinProgramWait; + uint32_t EmcPinExtraWait; + uint32_t EmcPinGpioEn; + uint32_t EmcPinGpio; + uint32_t EmcTimingControlWait; + uint32_t EmcRc; + uint32_t EmcRfc; + uint32_t EmcRfcPb; + uint32_t EmcRefctrl2; + uint32_t EmcRfcSlr; + uint32_t EmcRas; + uint32_t EmcRp; + uint32_t EmcR2r; + uint32_t EmcW2w; + uint32_t EmcR2w; + uint32_t EmcW2r; + uint32_t EmcR2p; + uint32_t EmcW2p; + uint32_t EmcTppd; + uint32_t EmcTrtm; + uint32_t EmcTwtm; + uint32_t EmcTratm; + uint32_t EmcTwatm; + uint32_t EmcTr2ref; + uint32_t EmcCcdmw; + uint32_t EmcRdRcd; + uint32_t EmcWrRcd; + uint32_t EmcRrd; + uint32_t EmcRext; + uint32_t EmcWext; + uint32_t EmcWdv; + uint32_t EmcWdvChk; + uint32_t EmcWsv; + uint32_t EmcWev; + uint32_t EmcWdvMask; + uint32_t EmcWsDuration; + uint32_t EmcWeDuration; + uint32_t EmcQUse; + uint32_t EmcQuseWidth; + uint32_t EmcIbdly; + uint32_t EmcObdly; + uint32_t EmcEInput; + uint32_t EmcEInputDuration; + uint32_t EmcPutermExtra; + uint32_t EmcPutermWidth; + uint32_t EmcQRst; + uint32_t EmcQSafe; + uint32_t EmcRdv; + uint32_t EmcRdvMask; + uint32_t EmcRdvEarly; + uint32_t EmcRdvEarlyMask; + uint32_t EmcQpop; + uint32_t EmcRefresh; + uint32_t EmcBurstRefreshNum; + uint32_t EmcPreRefreshReqCnt; + uint32_t EmcPdEx2Wr; + uint32_t EmcPdEx2Rd; + uint32_t EmcPChg2Pden; + uint32_t EmcAct2Pden; + uint32_t EmcAr2Pden; + uint32_t EmcRw2Pden; + uint32_t EmcCke2Pden; + uint32_t EmcPdex2Cke; + uint32_t EmcPdex2Mrr; + uint32_t EmcTxsr; + uint32_t EmcTxsrDll; + uint32_t EmcTcke; + uint32_t EmcTckesr; + uint32_t EmcTpd; + uint32_t EmcTfaw; + uint32_t EmcTrpab; + uint32_t EmcTClkStable; + uint32_t EmcTClkStop; + uint32_t EmcTRefBw; + uint32_t EmcFbioCfg5; + uint32_t EmcFbioCfg7; + uint32_t EmcFbioCfg8; + uint32_t EmcCmdMappingCmd0_0; + uint32_t EmcCmdMappingCmd0_1; + uint32_t EmcCmdMappingCmd0_2; + uint32_t EmcCmdMappingCmd1_0; + uint32_t EmcCmdMappingCmd1_1; + uint32_t EmcCmdMappingCmd1_2; + uint32_t EmcCmdMappingCmd2_0; + uint32_t EmcCmdMappingCmd2_1; + uint32_t EmcCmdMappingCmd2_2; + uint32_t EmcCmdMappingCmd3_0; + uint32_t EmcCmdMappingCmd3_1; + uint32_t EmcCmdMappingCmd3_2; + uint32_t EmcCmdMappingByte; + uint32_t EmcFbioSpare; + uint32_t EmcCfgRsv; + uint32_t EmcMrs; + uint32_t EmcEmrs; + uint32_t EmcEmrs2; + uint32_t EmcEmrs3; + uint32_t EmcMrw1; + uint32_t EmcMrw2; + uint32_t EmcMrw3; + uint32_t EmcMrw4; + uint32_t EmcMrw6; + uint32_t EmcMrw8; + uint32_t EmcMrw9; + uint32_t EmcMrw10; + uint32_t EmcMrw12; + uint32_t EmcMrw13; + uint32_t EmcMrw14; + uint32_t EmcMrwExtra; + uint32_t EmcWarmBootMrwExtra; + uint32_t EmcWarmBootExtraModeRegWriteEnable; + uint32_t EmcExtraModeRegWriteEnable; + uint32_t EmcMrwResetCommand; + uint32_t EmcMrwResetNInitWait; + uint32_t EmcMrsWaitCnt; + uint32_t EmcMrsWaitCnt2; + uint32_t EmcCfg; + uint32_t EmcCfg2; + uint32_t EmcCfgPipe; + uint32_t EmcCfgPipeClk; + uint32_t EmcFdpdCtrlCmdNoRamp; + uint32_t EmcCfgUpdate; + uint32_t EmcDbg; + uint32_t EmcDbgWriteMux; + uint32_t EmcCmdQ; + uint32_t EmcMc2EmcQ; + uint32_t EmcDynSelfRefControl; + uint32_t AhbArbitrationXbarCtrlMemInitDone; + uint32_t EmcCfgDigDll; + uint32_t EmcCfgDigDll_1; + uint32_t EmcCfgDigDllPeriod; + uint32_t EmcDevSelect; + uint32_t EmcSelDpdCtrl; + uint32_t EmcFdpdCtrlDq; + uint32_t EmcFdpdCtrlCmd; + uint32_t EmcPmacroIbVrefDq_0; + uint32_t EmcPmacroIbVrefDq_1; + uint32_t EmcPmacroIbVrefDqs_0; + uint32_t EmcPmacroIbVrefDqs_1; + uint32_t EmcPmacroIbRxrt; + uint32_t EmcCfgPipe1; + uint32_t EmcCfgPipe2; + uint32_t EmcPmacroQuseDdllRank0_0; + uint32_t EmcPmacroQuseDdllRank0_1; + uint32_t EmcPmacroQuseDdllRank0_2; + uint32_t EmcPmacroQuseDdllRank0_3; + uint32_t EmcPmacroQuseDdllRank0_4; + uint32_t EmcPmacroQuseDdllRank0_5; + uint32_t EmcPmacroQuseDdllRank1_0; + uint32_t EmcPmacroQuseDdllRank1_1; + uint32_t EmcPmacroQuseDdllRank1_2; + uint32_t EmcPmacroQuseDdllRank1_3; + uint32_t EmcPmacroQuseDdllRank1_4; + uint32_t EmcPmacroQuseDdllRank1_5; + uint32_t EmcPmacroObDdllLongDqRank0_0; + uint32_t EmcPmacroObDdllLongDqRank0_1; + uint32_t EmcPmacroObDdllLongDqRank0_2; + uint32_t EmcPmacroObDdllLongDqRank0_3; + uint32_t EmcPmacroObDdllLongDqRank0_4; + uint32_t EmcPmacroObDdllLongDqRank0_5; + uint32_t EmcPmacroObDdllLongDqRank1_0; + uint32_t EmcPmacroObDdllLongDqRank1_1; + uint32_t EmcPmacroObDdllLongDqRank1_2; + uint32_t EmcPmacroObDdllLongDqRank1_3; + uint32_t EmcPmacroObDdllLongDqRank1_4; + uint32_t EmcPmacroObDdllLongDqRank1_5; + uint32_t EmcPmacroObDdllLongDqsRank0_0; + uint32_t EmcPmacroObDdllLongDqsRank0_1; + uint32_t EmcPmacroObDdllLongDqsRank0_2; + uint32_t EmcPmacroObDdllLongDqsRank0_3; + uint32_t EmcPmacroObDdllLongDqsRank0_4; + uint32_t EmcPmacroObDdllLongDqsRank0_5; + uint32_t EmcPmacroObDdllLongDqsRank1_0; + uint32_t EmcPmacroObDdllLongDqsRank1_1; + uint32_t EmcPmacroObDdllLongDqsRank1_2; + uint32_t EmcPmacroObDdllLongDqsRank1_3; + uint32_t EmcPmacroObDdllLongDqsRank1_4; + uint32_t EmcPmacroObDdllLongDqsRank1_5; + uint32_t EmcPmacroIbDdllLongDqsRank0_0; + uint32_t EmcPmacroIbDdllLongDqsRank0_1; + uint32_t EmcPmacroIbDdllLongDqsRank0_2; + uint32_t EmcPmacroIbDdllLongDqsRank0_3; + uint32_t EmcPmacroIbDdllLongDqsRank1_0; + uint32_t EmcPmacroIbDdllLongDqsRank1_1; + uint32_t EmcPmacroIbDdllLongDqsRank1_2; + uint32_t EmcPmacroIbDdllLongDqsRank1_3; + uint32_t EmcPmacroDdllLongCmd_0; + uint32_t EmcPmacroDdllLongCmd_1; + uint32_t EmcPmacroDdllLongCmd_2; + uint32_t EmcPmacroDdllLongCmd_3; + uint32_t EmcPmacroDdllLongCmd_4; + uint32_t EmcPmacroDdllShortCmd_0; + uint32_t EmcPmacroDdllShortCmd_1; + uint32_t EmcPmacroDdllShortCmd_2; + uint32_t EmcPmacroDdllPeriodicOffset; + uint32_t WarmBootWait; + uint32_t EmcOdtWrite; + uint32_t EmcZcalInterval; + uint32_t EmcZcalWaitCnt; + uint32_t EmcZcalMrwCmd; + uint32_t EmcMrsResetDll; + uint32_t EmcZcalInitDev0; + uint32_t EmcZcalInitDev1; + uint32_t EmcZcalInitWait; + uint32_t EmcZcalWarmColdBootEnables; + uint32_t EmcMrwLpddr2ZcalWarmBoot; + uint32_t EmcZqCalDdr3WarmBoot; + uint32_t EmcZqCalLpDdr4WarmBoot; + uint32_t EmcZcalWarmBootWait; + uint32_t EmcMrsWarmBootEnable; + uint32_t EmcMrsResetDllWait; + uint32_t EmcMrsExtra; + uint32_t EmcWarmBootMrsExtra; + uint32_t EmcEmrsDdr2DllEnable; + uint32_t EmcMrsDdr2DllReset; + uint32_t EmcEmrsDdr2OcdCalib; + uint32_t EmcDdr2Wait; + uint32_t EmcClkenOverride; + uint32_t EmcExtraRefreshNum; + uint32_t EmcClkenOverrideAllWarmBoot; + uint32_t McClkenOverrideAllWarmBoot; + uint32_t EmcCfgDigDllPeriodWarmBoot; + uint32_t PmcVddpSel; + uint32_t PmcVddpSelWait; + uint32_t PmcDdrCfg; + uint32_t PmcIoDpd3Req; + uint32_t PmcIoDpd3ReqWait; + uint32_t PmcIoDpd4ReqWait; + uint32_t PmcRegShort; + uint32_t PmcNoIoPower; + uint32_t PmcDdrCntrlWait; + uint32_t PmcDdrCntrl; + uint32_t EmcAcpdControl; + uint32_t EmcSwizzleRank0Byte0; + uint32_t EmcSwizzleRank0Byte1; + uint32_t EmcSwizzleRank0Byte2; + uint32_t EmcSwizzleRank0Byte3; + uint32_t EmcSwizzleRank1Byte0; + uint32_t EmcSwizzleRank1Byte1; + uint32_t EmcSwizzleRank1Byte2; + uint32_t EmcSwizzleRank1Byte3; + uint32_t EmcTxdsrvttgen; + uint32_t EmcDataBrlshft0; + uint32_t EmcDataBrlshft1; + uint32_t EmcDqsBrlshft0; + uint32_t EmcDqsBrlshft1; + uint32_t EmcCmdBrlshft0; + uint32_t EmcCmdBrlshft1; + uint32_t EmcCmdBrlshft2; + uint32_t EmcCmdBrlshft3; + uint32_t EmcQuseBrlshft0; + uint32_t EmcQuseBrlshft1; + uint32_t EmcQuseBrlshft2; + uint32_t EmcQuseBrlshft3; + uint32_t EmcPmacroDllCfg0; + uint32_t EmcPmacroDllCfg1; + uint32_t EmcPmcScratch1; + uint32_t EmcPmcScratch2; + uint32_t EmcPmcScratch3; + uint32_t EmcPmacroPadCfgCtrl; + uint32_t EmcPmacroVttgenCtrl0; + uint32_t EmcPmacroVttgenCtrl1; + uint32_t EmcPmacroVttgenCtrl2; + uint32_t EmcPmacroDsrVttgenCtrl0; + uint32_t EmcPmacroBrickCtrlRfu1; + uint32_t EmcPmacroCmdBrickCtrlFdpd; + uint32_t EmcPmacroBrickCtrlRfu2; + uint32_t EmcPmacroDataBrickCtrlFdpd; + uint32_t EmcPmacroBgBiasCtrl0; + uint32_t EmcPmacroDataPadRxCtrl; + uint32_t EmcPmacroCmdPadRxCtrl; + uint32_t EmcPmacroDataRxTermMode; + uint32_t EmcPmacroCmdRxTermMode; + uint32_t EmcPmacroDataPadTxCtrl; + uint32_t EmcPmacroCmdPadTxCtrl; + uint32_t EmcCfg3; + uint32_t EmcPmacroTxPwrd0; + uint32_t EmcPmacroTxPwrd1; + uint32_t EmcPmacroTxPwrd2; + uint32_t EmcPmacroTxPwrd3; + uint32_t EmcPmacroTxPwrd4; + uint32_t EmcPmacroTxPwrd5; + uint32_t EmcConfigSampleDelay; + uint32_t EmcPmacroBrickMapping0; + uint32_t EmcPmacroBrickMapping1; + uint32_t EmcPmacroBrickMapping2; + uint32_t EmcPmacroTxSelClkSrc0; + uint32_t EmcPmacroTxSelClkSrc1; + uint32_t EmcPmacroTxSelClkSrc2; + uint32_t EmcPmacroTxSelClkSrc3; + uint32_t EmcPmacroTxSelClkSrc4; + uint32_t EmcPmacroTxSelClkSrc5; + uint32_t EmcPmacroPerbitFgcgCtrl0; + uint32_t EmcPmacroPerbitFgcgCtrl1; + uint32_t EmcPmacroPerbitFgcgCtrl2; + uint32_t EmcPmacroPerbitFgcgCtrl3; + uint32_t EmcPmacroPerbitFgcgCtrl4; + uint32_t EmcPmacroPerbitFgcgCtrl5; + uint32_t EmcPmacroPerbitRfuCtrl0; + uint32_t EmcPmacroPerbitRfuCtrl1; + uint32_t EmcPmacroPerbitRfuCtrl2; + uint32_t EmcPmacroPerbitRfuCtrl3; + uint32_t EmcPmacroPerbitRfuCtrl4; + uint32_t EmcPmacroPerbitRfuCtrl5; + uint32_t EmcPmacroPerbitRfu1Ctrl0; + uint32_t EmcPmacroPerbitRfu1Ctrl1; + uint32_t EmcPmacroPerbitRfu1Ctrl2; + uint32_t EmcPmacroPerbitRfu1Ctrl3; + uint32_t EmcPmacroPerbitRfu1Ctrl4; + uint32_t EmcPmacroPerbitRfu1Ctrl5; + uint32_t EmcPmacroDataPiCtrl; + uint32_t EmcPmacroCmdPiCtrl; + uint32_t EmcPmacroDdllBypass; + uint32_t EmcPmacroDdllPwrd0; + uint32_t EmcPmacroDdllPwrd1; + uint32_t EmcPmacroDdllPwrd2; + uint32_t EmcPmacroCmdCtrl0; + uint32_t EmcPmacroCmdCtrl1; + uint32_t EmcPmacroCmdCtrl2; + uint32_t McEmemAdrCfg; + uint32_t McEmemAdrCfgDev0; + uint32_t McEmemAdrCfgDev1; + uint32_t McEmemAdrCfgChannelMask; + uint32_t McEmemAdrCfgBankMask0; + uint32_t McEmemAdrCfgBankMask1; + uint32_t McEmemAdrCfgBankMask2; + uint32_t McEmemCfg; + uint32_t McEmemArbCfg; + uint32_t McEmemArbOutstandingReq; + uint32_t McEmemArbRefpbHpCtrl; + uint32_t McEmemArbRefpbBankCtrl; + uint32_t McEmemArbTimingRcd; + uint32_t McEmemArbTimingRp; + uint32_t McEmemArbTimingRc; + uint32_t McEmemArbTimingRas; + uint32_t McEmemArbTimingFaw; + uint32_t McEmemArbTimingRrd; + uint32_t McEmemArbTimingRap2Pre; + uint32_t McEmemArbTimingWap2Pre; + uint32_t McEmemArbTimingR2R; + uint32_t McEmemArbTimingW2W; + uint32_t McEmemArbTimingR2W; + uint32_t McEmemArbTimingW2R; + uint32_t McEmemArbTimingRFCPB; + uint32_t McEmemArbDaTurns; + uint32_t McEmemArbDaCovers; + uint32_t McEmemArbMisc0; + uint32_t McEmemArbMisc1; + uint32_t McEmemArbMisc2; + uint32_t McEmemArbRing1Throttle; + uint32_t McEmemArbOverride; + uint32_t McEmemArbOverride1; + uint32_t McEmemArbRsv; + uint32_t McDaCfg0; + uint32_t McEmemArbTimingCcdmw; + uint32_t McClkenOverride; + uint32_t McStatControl; + uint32_t McVideoProtectBom; + uint32_t McVideoProtectBomAdrHi; + uint32_t McVideoProtectSizeMb; + uint32_t McVideoProtectVprOverride; + uint32_t McVideoProtectVprOverride1; + uint32_t McVideoProtectGpuOverride0; + uint32_t McVideoProtectGpuOverride1; + uint32_t McSecCarveoutBom; + uint32_t McSecCarveoutAdrHi; + uint32_t McSecCarveoutSizeMb; + uint32_t McVideoProtectWriteAccess; + uint32_t McSecCarveoutProtectWriteAccess; + uint32_t McGeneralizedCarveout1Bom; + uint32_t McGeneralizedCarveout1BomHi; + uint32_t McGeneralizedCarveout1Size128kb; + uint32_t McGeneralizedCarveout1Access0; + uint32_t McGeneralizedCarveout1Access1; + uint32_t McGeneralizedCarveout1Access2; + uint32_t McGeneralizedCarveout1Access3; + uint32_t McGeneralizedCarveout1Access4; + uint32_t McGeneralizedCarveout1ForceInternalAccess0; + uint32_t McGeneralizedCarveout1ForceInternalAccess1; + uint32_t McGeneralizedCarveout1ForceInternalAccess2; + uint32_t McGeneralizedCarveout1ForceInternalAccess3; + uint32_t McGeneralizedCarveout1ForceInternalAccess4; + uint32_t McGeneralizedCarveout1Cfg0; + uint32_t McGeneralizedCarveout2Bom; + uint32_t McGeneralizedCarveout2BomHi; + uint32_t McGeneralizedCarveout2Size128kb; + uint32_t McGeneralizedCarveout2Access0; + uint32_t McGeneralizedCarveout2Access1; + uint32_t McGeneralizedCarveout2Access2; + uint32_t McGeneralizedCarveout2Access3; + uint32_t McGeneralizedCarveout2Access4; + uint32_t McGeneralizedCarveout2ForceInternalAccess0; + uint32_t McGeneralizedCarveout2ForceInternalAccess1; + uint32_t McGeneralizedCarveout2ForceInternalAccess2; + uint32_t McGeneralizedCarveout2ForceInternalAccess3; + uint32_t McGeneralizedCarveout2ForceInternalAccess4; + uint32_t McGeneralizedCarveout2Cfg0; + uint32_t McGeneralizedCarveout3Bom; + uint32_t McGeneralizedCarveout3BomHi; + uint32_t McGeneralizedCarveout3Size128kb; + uint32_t McGeneralizedCarveout3Access0; + uint32_t McGeneralizedCarveout3Access1; + uint32_t McGeneralizedCarveout3Access2; + uint32_t McGeneralizedCarveout3Access3; + uint32_t McGeneralizedCarveout3Access4; + uint32_t McGeneralizedCarveout3ForceInternalAccess0; + uint32_t McGeneralizedCarveout3ForceInternalAccess1; + uint32_t McGeneralizedCarveout3ForceInternalAccess2; + uint32_t McGeneralizedCarveout3ForceInternalAccess3; + uint32_t McGeneralizedCarveout3ForceInternalAccess4; + uint32_t McGeneralizedCarveout3Cfg0; + uint32_t McGeneralizedCarveout4Bom; + uint32_t McGeneralizedCarveout4BomHi; + uint32_t McGeneralizedCarveout4Size128kb; + uint32_t McGeneralizedCarveout4Access0; + uint32_t McGeneralizedCarveout4Access1; + uint32_t McGeneralizedCarveout4Access2; + uint32_t McGeneralizedCarveout4Access3; + uint32_t McGeneralizedCarveout4Access4; + uint32_t McGeneralizedCarveout4ForceInternalAccess0; + uint32_t McGeneralizedCarveout4ForceInternalAccess1; + uint32_t McGeneralizedCarveout4ForceInternalAccess2; + uint32_t McGeneralizedCarveout4ForceInternalAccess3; + uint32_t McGeneralizedCarveout4ForceInternalAccess4; + uint32_t McGeneralizedCarveout4Cfg0; + uint32_t McGeneralizedCarveout5Bom; + uint32_t McGeneralizedCarveout5BomHi; + uint32_t McGeneralizedCarveout5Size128kb; + uint32_t McGeneralizedCarveout5Access0; + uint32_t McGeneralizedCarveout5Access1; + uint32_t McGeneralizedCarveout5Access2; + uint32_t McGeneralizedCarveout5Access3; + uint32_t McGeneralizedCarveout5Access4; + uint32_t McGeneralizedCarveout5ForceInternalAccess0; + uint32_t McGeneralizedCarveout5ForceInternalAccess1; + uint32_t McGeneralizedCarveout5ForceInternalAccess2; + uint32_t McGeneralizedCarveout5ForceInternalAccess3; + uint32_t McGeneralizedCarveout5ForceInternalAccess4; + uint32_t McGeneralizedCarveout5Cfg0; + uint32_t EmcCaTrainingEnable; + uint32_t SwizzleRankByteEncode; + uint32_t BootRomPatchControl; + uint32_t BootRomPatchData; + uint32_t McMtsCarveoutBom; + uint32_t McMtsCarveoutAdrHi; + uint32_t McMtsCarveoutSizeMb; + uint32_t McMtsCarveoutRegCtrl; + uint32_t McUntranslatedRegionCheck; + uint32_t BCT_NA; +} sdram_params_mariko_t; + +#endif diff --git a/fusee/fusee-secondary/src/emc.h b/fusee/fusee-secondary/src/emc.h index 17161b407..274d8213f 100644 --- a/fusee/fusee-secondary/src/emc.h +++ b/fusee/fusee-secondary/src/emc.h @@ -1086,4 +1086,44 @@ #define EMC_PMC_SCRATCH2 0x444 #define EMC_PMC_SCRATCH3 0x448 +#define EMC_PMACRO_PERBIT_FGCG_CTRL_0 0xd40 +#define EMC_PMACRO_PERBIT_FGCG_CTRL_1 0xd44 +#define EMC_PMACRO_PERBIT_FGCG_CTRL_2 0xd48 +#define EMC_PMACRO_PERBIT_FGCG_CTRL_3 0xd4c +#define EMC_PMACRO_PERBIT_FGCG_CTRL_4 0xd50 +#define EMC_PMACRO_PERBIT_FGCG_CTRL_5 0xd54 +#define EMC_PMACRO_PERBIT_RFU_CTRL_0 0xd60 +#define EMC_PMACRO_PERBIT_RFU_CTRL_1 0xd64 +#define EMC_PMACRO_PERBIT_RFU_CTRL_2 0xd68 +#define EMC_PMACRO_PERBIT_RFU_CTRL_3 0xd6c +#define EMC_PMACRO_PERBIT_RFU_CTRL_4 0xd70 +#define EMC_PMACRO_PERBIT_RFU_CTRL_5 0xd74 +#define EMC_PMACRO_PERBIT_RFU1_CTRL_0 0xd80 +#define EMC_PMACRO_PERBIT_RFU1_CTRL_1 0xd84 +#define EMC_PMACRO_PERBIT_RFU1_CTRL_2 0xd88 +#define EMC_PMACRO_PERBIT_RFU1_CTRL_3 0xd8c +#define EMC_PMACRO_PERBIT_RFU1_CTRL_4 0xd90 +#define EMC_PMACRO_PERBIT_RFU1_CTRL_5 0xd94 + +#define EMC_PMACRO_PMU_OUT_EOFF1_0 0xda0 +#define EMC_PMACRO_PMU_OUT_EOFF1_1 0xda4 +#define EMC_PMACRO_PMU_OUT_EOFF1_2 0xda8 +#define EMC_PMACRO_PMU_OUT_EOFF1_3 0xdac +#define EMC_PMACRO_PMU_OUT_EOFF1_4 0xdb0 +#define EMC_PMACRO_PMU_OUT_EOFF1_5 0xdb4 + +#define EMC_PMACRO_COMP_PMU_OUT 0xdc0 +#define EMC_PMACRO_DATA_PI_CTRL 0x110 +#define EMC_PMACRO_CMD_PI_CTRL 0x114 + +#define EMC_AUTO_CAL_CONFIG9 0x42c + +#define EMC_TRTM 0xbc +#define EMC_TWTM 0xf8 +#define EMC_TRATM 0xfc +#define EMC_TWATM 0x108 +#define EMC_TR2REF 0x10c + +#define EMC_PMACRO_DSR_VTTGEN_CTRL_0 0xc6c + #endif diff --git a/fusee/fusee-secondary/src/fuse.c b/fusee/fusee-secondary/src/fuse.c index e53cda3b3..14f12e69b 100644 --- a/fusee/fusee-secondary/src/fuse.c +++ b/fusee/fusee-secondary/src/fuse.c @@ -187,7 +187,7 @@ uint32_t fuse_get_reserved_odm(uint32_t index) { /* Get the DramId. */ uint32_t fuse_get_dram_id(void) { - return ((fuse_get_reserved_odm(4) >> 3) & 0x7); + return ((fuse_get_reserved_odm(4) >> 3) & 0x1F); } /* Derive the DeviceId. */ diff --git a/fusee/fusee-secondary/src/mc.h b/fusee/fusee-secondary/src/mc.h index 63a263a59..c414f907a 100644 --- a/fusee/fusee-secondary/src/mc.h +++ b/fusee/fusee-secondary/src/mc.h @@ -497,6 +497,7 @@ #define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08 #define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0 #define MC_DA_CONFIG0 0x9dc +#define MC_UNTRANSLATED_REGION_CHECK 0x948 /* Memory Controller clients */ #define CLIENT_ACCESS_NUM_CLIENTS 32 diff --git a/sept/sept-primary/src/fuse.c b/sept/sept-primary/src/fuse.c index 1787bffb4..cf6966e5d 100644 --- a/sept/sept-primary/src/fuse.c +++ b/sept/sept-primary/src/fuse.c @@ -187,7 +187,7 @@ uint32_t fuse_get_reserved_odm(uint32_t index) { /* Get the DramId. */ uint32_t fuse_get_dram_id(void) { - return ((fuse_get_reserved_odm(4) >> 3) & 0x7); + return ((fuse_get_reserved_odm(4) >> 3) & 0x1F); } /* Derive the DeviceId. */ diff --git a/sept/sept-primary/src/mc.h b/sept/sept-primary/src/mc.h index 9129388d8..fad84a8c9 100644 --- a/sept/sept-primary/src/mc.h +++ b/sept/sept-primary/src/mc.h @@ -497,6 +497,7 @@ #define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08 #define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0 #define MC_DA_CONFIG0 0x9dc +#define MC_UNTRANSLATED_REGION_CHECK 0x948 /* Memory Controller clients */ #define CLIENT_ACCESS_NUM_CLIENTS 32 diff --git a/sept/sept-secondary/src/emc.h b/sept/sept-secondary/src/emc.h index c694f9c87..274d8213f 100644 --- a/sept/sept-secondary/src/emc.h +++ b/sept/sept-secondary/src/emc.h @@ -1,1089 +1,1129 @@ -/* - * arch/arm/mach-tegra/tegra21_emc.h - * - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - */ - -#ifndef FUSEE_EMC_H_ -#define FUSEE_EMC_H_ - -#define EMC_BASE 0x7001B000 -#define EMC0_BASE 0x7001E000 -#define EMC1_BASE 0x7001F000 -#define MAKE_EMC_REG(n) MAKE_REG32(EMC_BASE + n) -#define MAKE_EMC0_REG(n) MAKE_REG32(EMC0_BASE + n) -#define MAKE_EMC1_REG(n) MAKE_REG32(EMC1_BASE + n) - -#define EMC_INTSTATUS 0x0 -#define EMC_INTSTATUS_MRR_DIVLD (0x1 << 5) -#define EMC_INTSTATUS_CLKCHANGE_COMPLETE (0x1 << 4) - -#define EMC_INTMASK 0x4 -#define EMC_DBG 0x8 -#define EMC_DBG_WRITE_MUX_ACTIVE (1 << 1) -#define EMC_DBG_CFG_SWAP_SHIFT 26 -#define EMC_DBG_CFG_SWAP_MASK \ - (0x3 << EMC_DBG_CFG_SWAP_SHIFT) -#define EMC_DBG_WRITE_ACTIVE_ONLY (1 << 30) - -#define EMC_CONFIG_SAMPLE_DELAY 0x5f0 -#define EMC_CFG_UPDATE 0x5f4 -#define EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT 9 -#define EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_MASK \ - (0x3 << EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT) -#define EMC_CFG 0xc -#define EMC_CFG_DRAM_CLKSTOP_PD (1 << 31) -#define EMC_CFG_DRAM_CLKSTOP_SR (1 << 30) -#define EMC_CFG_DRAM_ACPD (1 << 29) -#define EMC_CFG_DYN_SELF_REF (1 << 28) -#define EMC_CFG_REQACT_ASYNC (1 << 26) -#define EMC_CFG_AUTO_PRE_WR (1 << 25) -#define EMC_CFG_AUTO_PRE_RD (1 << 24) -#define EMC_CFG_MAM_PRE_WR (1 << 23) -#define EMC_CFG_MAN_PRE_RD (1 << 22) -#define EMC_CFG_PERIODIC_QRST (1 << 21) -#define EMC_CFG_PERIODIC_QRST_SHIFT (21) -#define EMC_CFG_EN_DYNAMIC_PUTERM (1 << 20) -#define EMC_CFG_DLY_WR_DQ_HALF_CLOCK (1 << 19) -#define EMC_CFG_DSR_VTTGEN_DRV_EN (1 << 18) -#define EMC_CFG_EMC2MC_CLK_RATIO (3 << 16) -#define EMC_CFG_WAIT_FOR_ISP2B_READY_B4_CC (1 << 9) -#define EMC_CFG_WAIT_FOR_VI2_READY_B4_CC (1 << 8) -#define EMC_CFG_WAIT_FOR_ISP2_READY_B4_CC (1 << 7) -#define EMC_CFG_INVERT_DQM (1 << 6) -#define EMC_CFG_WAIT_FOR_DISPLAYB_READY_B4_CC (1 << 5) -#define EMC_CFG_WAIT_FOR_DISPLAY_READY_B4_CC (1 << 4) -#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2 (1 << 3) -#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1 (1 << 2) -#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE (1 << 1) - -#define EMC_ADR_CFG 0x10 -#define EMC_REFCTRL 0x20 -#define EMC_REFCTRL_DEV_SEL_SHIFT 0 -#define EMC_REFCTRL_DEV_SEL_MASK \ - (0x3 << EMC_REFCTRL_DEV_SEL_SHIFT) -#define EMC_REFCTRL_ENABLE (0x1 << 31) -#define EMC_REFCTRL_ENABLE_ALL(num) \ - (((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) \ - | EMC_REFCTRL_ENABLE) -#define EMC_REFCTRL_DISABLE_ALL(num) \ - ((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) - -#define EMC_PIN 0x24 -#define EMC_PIN_PIN_CKE_PER_DEV (1 << 2) -#define EMC_PIN_PIN_CKEB (1 << 1) -#define EMC_PIN_PIN_CKE (1 << 0) - -#define EMC_CLK_FORCE_CC_TRIGGER (1 << 27) - -#define EMC_TIMING_CONTROL 0x28 -#define EMC_RC 0x2c -#define EMC_RFC 0x30 -#define EMC_RFCPB 0x590 -#define EMC_RAS 0x34 -#define EMC_RP 0x38 -#define EMC_R2W 0x3c -#define EMC_W2R 0x40 -#define EMC_R2P 0x44 -#define EMC_W2P 0x48 -#define EMC_CCDMW 0x5c0 -#define EMC_RD_RCD 0x4c -#define EMC_WR_RCD 0x50 -#define EMC_RRD 0x54 -#define EMC_REXT 0x58 -#define EMC_WDV 0x5c -#define EMC_QUSE 0x60 -#define EMC_QRST 0x64 -#define EMC_ISSUE_QRST 0x428 -#define EMC_QSAFE 0x68 -#define EMC_RDV 0x6c -#define EMC_REFRESH 0x70 -#define EMC_BURST_REFRESH_NUM 0x74 -#define EMC_PDEX2WR 0x78 -#define EMC_PDEX2RD 0x7c -#define EMC_PDEX2CKE 0x118 -#define EMC_PCHG2PDEN 0x80 -#define EMC_ACT2PDEN 0x84 -#define EMC_AR2PDEN 0x88 -#define EMC_RW2PDEN 0x8c -#define EMC_CKE2PDEN 0x11c -#define EMC_TXSR 0x90 -#define EMC_TCKE 0x94 -#define EMC_TFAW 0x98 -#define EMC_TRPAB 0x9c -#define EMC_TCLKSTABLE 0xa0 -#define EMC_TCLKSTOP 0xa4 -#define EMC_TREFBW 0xa8 -#define EMC_TPPD 0xac -#define EMC_PDEX2MRR 0xb4 -#define EMC_ODT_WRITE 0xb0 -#define EMC_WEXT 0xb8 -#define EMC_RFC_SLR 0xc0 -#define EMC_MRS_WAIT_CNT2 0xc4 -#define EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_SHIFT 16 -#define EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_MASK \ - (0x7ff << EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_SHIFT) -#define EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_SHIFT 0 -#define EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_MASK \ - (0x3ff << EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_SHIFT) - -#define EMC_MRS_WAIT_CNT 0xc8 -#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0 -#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \ - (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT) -#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16 -#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \ - (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) - -#define EMC_MRS 0xcc -#define EMC_MODE_SET_DLL_RESET (1 << 8) -#define EMC_MRS_USE_MRS_LONG_CNT (1 << 26) - -#define EMC_EMRS 0xd0 -#define EMC_EMRS_USE_EMRS_LONG_CNT (1 << 26) - -#define EMC_REF 0xd4 -#define EMC_REF_FORCE_CMD 1 - -#define EMC_PRE 0xd8 -#define EMC_NOP 0xdc -#define EMC_SELF_REF 0xe0 -#define EMC_SELF_REF_CMD_ENABLED (1 << 0) -#define EMC_SELF_REF_ACTIVE_SELF_REF (1 << 8) -#define EMC_SELF_REF_DEV_SEL_SHIFT 30 -#define EMC_SELF_REF_DEV_SEL_MASK \ - (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT) - -#define EMC_DPD 0xe4 -#define EMC_MRW 0xe8 -#define EMC_MRW_MRW_OP_SHIFT 0 -#define EMC_MRW_MRW_OP_MASK \ - (0xff << EMC_MRW_MRW_OP_SHIFT) -#define EMC_MRW_MRW_MA_SHIFT 16 -#define EMC_MRW_MRW_MA_MASK \ - (0xff << EMC_MRW_MRW_MA_SHIFT) -#define EMC_MRW_USE_MRW_LONG_CNT 26 -#define EMC_MRW_USE_MRW_EXT_CNT 27 -#define EMC_MRW_MRW_DEV_SELECTN_SHIFT 30 -#define EMC_MRW_MRW_DEV_SELECTN_MASK \ - (0x3 << EMC_MRW_MRW_DEV_SELECTN_SHIFT) - -#define EMC_MRR 0xec -#define EMC_MRR_DEV_SEL_SHIFT 30 -#define EMC_MRR_DEV_SEL_MASK \ - (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT) -#define EMC_MRR_MA_SHIFT 16 -#define EMC_MRR_MA_MASK \ - (0xff << EMC_MRR_MA_SHIFT) -#define EMC_MRR_DATA_SHIFT 0 -#define EMC_MRR_DATA_MASK \ - (0xffff << EMC_MRR_DATA_SHIFT) -#define LPDDR2_MR4_TEMP_SHIFT 0 -#define LPDDR2_MR4_TEMP_MASK \ - (0x7 << LPDDR2_MR4_TEMP_SHIFT) - -#define EMC_CMDQ 0xf0 -#define EMC_MC2EMCQ 0xf4 -#define EMC_FBIO_SPARE 0x100 -#define EMC_FBIO_CFG5 0x104 -#define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0 -#define EMC_FBIO_CFG5_DRAM_TYPE_MASK \ - (0x3 << EMC_FBIO_CFG5_DRAM_TYPE_SHIFT) -#define EMC_FBIO_CFG5_CMD_TX_DIS (1 << 8) -#define EMC_FBIO_CFG5_CMD_BUS_RETURN_TO_ZERO (1 << 27) - -#define EMC_CFG5_QUSE_MODE_SHIFT 13 -#define EMC_CFG5_QUSE_MODE_MASK \ - (0x7 << EMC_CFG5_QUSE_MODE_SHIFT) - -#define EMC_CFG_RSV 0x120 -#define EMC_ACPD_CONTROL 0x124 -#define EMC_MPC 0x128 -#define EMC_EMRS2 0x12c -#define EMC_EMRS2_USE_EMRS2_LONG_CNT (1 << 26) - -#define EMC_EMRS3 0x130 -#define EMC_MRW2 0x134 -#define EMC_MRW3 0x138 -#define EMC_MRW4 0x13c -#define EMC_MRW5 0x4a0 -#define EMC_MRW6 0x4a4 -#define EMC_MRW7 0x4a8 -#define EMC_MRW8 0x4ac -#define EMC_MRW9 0x4b0 -#define EMC_MRW10 0x4b4 -#define EMC_MRW11 0x4b8 -#define EMC_MRW12 0x4bc -#define EMC_MRW13 0x4c0 -#define EMC_MRW14 0x4c4 -#define EMC_MRW15 0x4d0 -#define EMC_CFG_SYNC 0x4d4 -#define EMC_CLKEN_OVERRIDE 0x140 -#define EMC_R2R 0x144 -#define EMC_W2W 0x148 -#define EMC_EINPUT 0x14c -#define EMC_EINPUT_DURATION 0x150 -#define EMC_PUTERM_EXTRA 0x154 -#define EMC_TCKESR 0x158 -#define EMC_TPD 0x15c -#define EMC_STAT_CONTROL 0x160 -#define EMC_STAT_STATUS 0x164 -#define EMC_STAT_DRAM_CLOCK_LIMIT_LO 0x19c -#define EMC_STAT_DRAM_CLOCK_LIMIT_HI 0x1a0 -#define EMC_STAT_DRAM_CLOCKS_LO 0x1a4 -#define EMC_STAT_DRAM_CLOCKS_HI 0x1a8 -#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO 0x1ac -#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI 0x1b0 -#define EMC_STAT_DRAM_DEV0_READ_CNT_LO 0x1b4 -#define EMC_STAT_DRAM_DEV0_READ_CNT_HI 0x1b8 -#define EMC_STAT_DRAM_DEV0_READ8_CNT_LO 0x1bc -#define EMC_STAT_DRAM_DEV0_READ8_CNT_HI 0x1c0 -#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO 0x1c4 -#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI 0x1c8 -#define EMC_STAT_DRAM_DEV0_WRITE8_CNT_LO 0x1cc -#define EMC_STAT_DRAM_DEV0_WRITE8_CNT_HI 0x1d0 -#define EMC_STAT_DRAM_DEV0_REF_CNT_LO 0x1d4 -#define EMC_STAT_DRAM_DEV0_REF_CNT_HI 0x1d8 -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x1dc -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x1e0 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x1e4 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x1e8 -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x1ec -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x1f0 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x1f4 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x1f8 -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x1fc -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x200 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x204 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x208 -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x20c -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x210 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x214 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x218 -#define EMC_STAT_DRAM_DEV0_SR_CKE_EQ0_CLKS_LO 0x21c -#define EMC_STAT_DRAM_DEV0_SR_CKE_EQ0_CLKS_HI 0x220 -#define EMC_STAT_DRAM_DEV0_DSR 0x224 -#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO 0x228 -#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI 0x22c -#define EMC_STAT_DRAM_DEV1_READ_CNT_LO 0x230 -#define EMC_STAT_DRAM_DEV1_READ_CNT_HI 0x234 -#define EMC_STAT_DRAM_DEV1_READ8_CNT_LO 0x238 -#define EMC_STAT_DRAM_DEV1_READ8_CNT_HI 0x23c -#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO 0x240 -#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI 0x244 -#define EMC_STAT_DRAM_DEV1_WRITE8_CNT_LO 0x248 -#define EMC_STAT_DRAM_DEV1_WRITE8_CNT_HI 0x24c -#define EMC_STAT_DRAM_DEV1_REF_CNT_LO 0x250 -#define EMC_STAT_DRAM_DEV1_REF_CNT_HI 0x254 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x258 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x25c -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x260 -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x264 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x268 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x26c -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x270 -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x274 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x278 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x27c -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x280 -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x284 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x288 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x28c -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x290 -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x294 -#define EMC_STAT_DRAM_DEV1_SR_CKE_EQ0_CLKS_LO 0x298 -#define EMC_STAT_DRAM_DEV1_SR_CKE_EQ0_CLKS_HI 0x29c -#define EMC_STAT_DRAM_DEV1_DSR 0x2a0 -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0xc8c -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0xc90 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0xc94 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0xc98 -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0xc9c -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0xca0 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0xca4 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0xca8 -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0xcac -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0xcb0 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0xcb4 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0xcb8 -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0xcbc -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0xcc0 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0xcc4 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0xcc8 -#define EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_LO 0xccc -#define EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_HI 0xcd0 -#define EMC_STAT_DRAM_IO_DSR 0xcd4 -#define EMC_AUTO_CAL_CONFIG 0x2a4 -#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_COMPUTE_START (1 << 0) -#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_MEASURE_STALL (1 << 9) -#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_UPDATE_STALL (1 << 10) -#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE (1 << 29) -#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START (1 << 31) - -#define EMC_AUTO_CAL_CONFIG2 0x458 -#define EMC_AUTO_CAL_CONFIG3 0x45c -#define EMC_AUTO_CAL_CONFIG4 0x5b0 -#define EMC_AUTO_CAL_CONFIG5 0x5b4 -#define EMC_AUTO_CAL_CONFIG6 0x5cc -#define EMC_AUTO_CAL_CONFIG7 0x574 -#define EMC_AUTO_CAL_CONFIG8 0x2dc -#define EMC_AUTO_CAL_VREF_SEL_0 0x2f8 -#define EMC_AUTO_CAL_VREF_SEL_1 0x300 -#define EMC_AUTO_CAL_INTERVAL 0x2a8 -#define EMC_AUTO_CAL_STATUS 0x2ac -#define EMC_AUTO_CAL_STATUS2 0x3d4 -#define EMC_AUTO_CAL_CHANNEL 0x464 -#define EMC_PMACRO_RX_TERM 0xc48 -#define EMC_PMACRO_DQ_TX_DRV 0xc70 -#define EMC_PMACRO_CA_TX_DRV 0xc74 -#define EMC_PMACRO_CMD_TX_DRV 0xc4c -#define EMC_PMACRO_AUTOCAL_CFG_0 0x700 -#define EMC_PMACRO_AUTOCAL_CFG_1 0x704 -#define EMC_PMACRO_AUTOCAL_CFG_2 0x708 -#define EMC_PMACRO_AUTOCAL_CFG_COMMON 0xc78 -#define EMC_PMACRO_AUTOCAL_CFG_COMMON_E_CAL_BYPASS_DVFS (1 << 16) - -#define EMC_PMACRO_ZCTRL 0xc44 -#define EMC_XM2COMPPADCTRL 0x30c -#define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE (1 << 10) - -#define EMC_XM2COMPPADCTRL2 0x578 -#define EMC_XM2COMPPADCTRL3 0x2f4 -#define EMC_COMP_PAD_SW_CTRL 0x57c -#define EMC_REQ_CTRL 0x2b0 -#define EMC_EMC_STATUS 0x2b4 -#define EMC_EMC_STATUS_MRR_DIVLD (1 << 20) -#define EMC_EMC_STATUS_TIMING_UPDATE_STALLED (1 << 23) -#define EMC_EMC_STATUS_DRAM_IN_POWERDOWN_SHIFT 4 -#define EMC_EMC_STATUS_DRAM_IN_POWERDOWN_MASK \ - (0x3 << EMC_EMC_STATUS_DRAM_IN_POWERDOWN_SHIFT) -#define EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_SHIFT 8 -#define EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_MASK \ - (0x3 << EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_SHIFT) - -#define EMC_CFG_2 0x2b8 -#define EMC_CFG_DIG_DLL 0x2bc -#define EMC_CFG_DIG_DLL_CFG_DLL_EN (1 << 0) -#define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_UNTIL_LOCK (1 << 1) -#define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_TRAFFIC (1 << 3) -#define EMC_CFG_DIG_DLL_CFG_DLL_STALL_RW_UNTIL_LOCK (1 << 4) -#define EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT 6 -#define EMC_CFG_DIG_DLL_CFG_DLL_MODE_MASK \ - (0x3 << EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT) -#define EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT 8 -#define EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_MASK \ - (0x7 << EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT) - -#define EMC_CFG_DIG_DLL_PERIOD 0x2c0 -#define EMC_DIG_DLL_STATUS 0x2c4 -#define EMC_DIG_DLL_STATUS_DLL_LOCK (1 << 15) -#define EMC_DIG_DLL_STATUS_DLL_PRIV_UPDATED (1 << 17) -#define EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT 0 -#define EMC_DIG_DLL_STATUS_DLL_OUT_MASK \ - (0x7ff << EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT) - -#define EMC_CFG_DIG_DLL_1 0x2c8 -#define EMC_RDV_MASK 0x2cc -#define EMC_WDV_MASK 0x2d0 -#define EMC_RDV_EARLY_MASK 0x2d4 -#define EMC_RDV_EARLY 0x2d8 -#define EMC_WDV_CHK 0x4e0 -#define EMC_ZCAL_INTERVAL 0x2e0 -#define EMC_ZCAL_WAIT_CNT 0x2e4 -#define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_MASK 0x7ff -#define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_SHIFT 0 - -#define EMC_ZCAL_MRW_CMD 0x2e8 -#define EMC_ZQ_CAL 0x2ec -#define EMC_ZQ_CAL_DEV_SEL_SHIFT 30 -#define EMC_ZQ_CAL_DEV_SEL_MASK \ - (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT) -#define EMC_ZQ_CAL_LONG (1 << 4) -#define EMC_ZQ_CAL_ZQ_LATCH_CMD (1 << 1) -#define EMC_ZQ_CAL_ZQ_CAL_CMD (1 << 0) -#define EMC_ZQ_CAL_LONG_CMD_DEV0 \ - (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) -#define EMC_ZQ_CAL_LONG_CMD_DEV1 \ - (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) - -#define EMC_SCRATCH0 0x324 -#define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE 0x3c8 -#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc -#define EMC_UNSTALL_RW_AFTER_CLKCHANGE 0x3d0 -#define EMC_FDPD_CTRL_CMD_NO_RAMP 0x4d8 -#define EMC_FDPD_CTRL_CMD_NO_RAMP_CMD_DPD_NO_RAMP_ENABLE (1 << 0) - -#define EMC_SEL_DPD_CTRL 0x3d8 -#define EMC_SEL_DPD_CTRL_DATA_SEL_DPD_EN (1 << 8) -#define EMC_SEL_DPD_CTRL_ODT_SEL_DPD_EN (1 << 5) -#define EMC_SEL_DPD_CTRL_RESET_SEL_DPD_EN (1 << 4) -#define EMC_SEL_DPD_CTRL_CA_SEL_DPD_EN (1 << 3) -#define EMC_SEL_DPD_CTRL_CLK_SEL_DPD_EN (1 << 2) -#define EMC_SEL_DPD_CTRL_DDR3_MASK \ - ((0xf << 2) | (0x1 << 8)) -#define EMC_SEL_DPD_CTRL_MAS \ - ((0x3 << 2) | (0x1 << 5) | (0x1 << 8)) - -#define EMC_FDPD_CTRL_DQ 0x310 -#define EMC_FDPD_CTRL_CMD 0x314 -#define EMC_PRE_REFRESH_REQ_CNT 0x3dc -#define EMC_REFCTRL2 0x580 -#define EMC_FBIO_CFG7 0x584 -#define EMC_FBIO_CFG7_CH0_ENABLE (1 << 1) -#define EMC_FBIO_CFG7_CH1_ENABLE (1 << 2) - -#define EMC_DATA_BRLSHFT_0 0x588 -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT 21 -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT 18 -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT 15 -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT 12 -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT 9 -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT 6 -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT 3 -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT 0 -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT) - -#define EMC_DATA_BRLSHFT_1 0x58c -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT 21 -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT 18 -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT 15 -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT 12 -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT 9 -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT 6 -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT 3 -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT 0 -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT) - -#define EMC_DQS_BRLSHFT_0 0x594 -#define EMC_DQS_BRLSHFT_1 0x598 -#define EMC_CMD_BRLSHFT_0 0x59c -#define EMC_CMD_BRLSHFT_1 0x5a0 -#define EMC_CMD_BRLSHFT_2 0x5a4 -#define EMC_CMD_BRLSHFT_3 0x5a8 -#define EMC_QUSE_BRLSHFT_0 0x5ac -#define EMC_QUSE_BRLSHFT_1 0x5b8 -#define EMC_QUSE_BRLSHFT_2 0x5bc -#define EMC_QUSE_BRLSHFT_3 0x5c4 -#define EMC_FBIO_CFG8 0x5c8 -#define EMC_CMD_MAPPING_CMD0_0 0x380 -#define EMC_CMD_MAPPING_CMD0_1 0x384 -#define EMC_CMD_MAPPING_CMD0_2 0x388 -#define EMC_CMD_MAPPING_CMD1_0 0x38c -#define EMC_CMD_MAPPING_CMD1_1 0x390 -#define EMC_CMD_MAPPING_CMD1_2 0x394 -#define EMC_CMD_MAPPING_CMD2_0 0x398 -#define EMC_CMD_MAPPING_CMD2_1 0x39c -#define EMC_CMD_MAPPING_CMD2_2 0x3a0 -#define EMC_CMD_MAPPING_CMD3_0 0x3a4 -#define EMC_CMD_MAPPING_CMD3_1 0x3a8 -#define EMC_CMD_MAPPING_CMD3_2 0x3ac -#define EMC_CMD_MAPPING_BYTE 0x3b0 -#define EMC_DYN_SELF_REF_CONTROL 0x3e0 -#define EMC_TXSRDLL 0x3e4 -#define EMC_CCFIFO_ADDR 0x3e8 -#define EMC_CCFIFO_DATA 0x3ec -#define EMC_CCFIFO_STATUS 0x3f0 -#define EMC_SWIZZLE_RANK0_BYTE0 0x404 -#define EMC_SWIZZLE_RANK0_BYTE1 0x408 -#define EMC_SWIZZLE_RANK0_BYTE2 0x40c -#define EMC_SWIZZLE_RANK0_BYTE3 0x410 -#define EMC_SWIZZLE_RANK1_BYTE0 0x418 -#define EMC_SWIZZLE_RANK1_BYTE1 0x41c -#define EMC_SWIZZLE_RANK1_BYTE2 0x420 -#define EMC_SWIZZLE_RANK1_BYTE3 0x424 -#define EMC_TR_TIMING_0 0x3b4 -#define EMC_TR_CTRL_0 0x3b8 -#define EMC_TR_CTRL_1 0x3bc -#define EMC_TR_DVFS 0x460 -#define EMC_TR_DVFS_TRAINING_DVFS (1 << 0) - -#define EMC_SWITCH_BACK_CTRL 0x3c0 -#define EMC_TR_RDV 0x3c4 -#define EMC_TR_QPOP 0x3f4 -#define EMC_TR_RDV_MASK 0x3f8 -#define EMC_TR_QSAFE 0x3fc -#define EMC_TR_QRST 0x400 -#define EMC_IBDLY 0x468 -#define EMC_OBDLY 0x46c -#define EMC_TXDSRVTTGEN 0x480 -#define EMC_WE_DURATION 0x48c -#define EMC_WS_DURATION 0x490 -#define EMC_WEV 0x494 -#define EMC_WSV 0x498 -#define EMC_CFG_3 0x49c -#define EMC_CFG_PIPE_2 0x554 -#define EMC_CFG_PIPE_CLK 0x558 -#define EMC_CFG_PIPE_CLK_CLK_ALWAYS_ON (1 << 0) - -#define EMC_CFG_PIPE_1 0x55c -#define EMC_CFG_PIPE 0x560 -#define EMC_QPOP 0x564 -#define EMC_QUSE_WIDTH 0x568 -#define EMC_PUTERM_WIDTH 0x56c -#define EMC_PROTOBIST_CONFIG_ADR_1 0x5d0 -#define EMC_PROTOBIST_CONFIG_ADR_2 0x5d4 -#define EMC_PROTOBIST_MISC 0x5d8 -#define EMC_PROTOBIST_WDATA_LOWER 0x5dc -#define EMC_PROTOBIST_WDATA_UPPER 0x5e0 -#define EMC_PROTOBIST_RDATA 0x5ec -#define EMC_DLL_CFG_0 0x5e4 -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_IGNORE_START (1 << 29) -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_DUAL_PASS_LOCK (1 << 28) -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_STEP_SIZE_SHIFT 24 -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_STEP_SIZE_MASK \ - (0xf << EMC_DLL_CFG_0_DDLLCAL_CTRL_STEP_SIZE_SHIFT) -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_END_COUNT_SHIFT 20 -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_END_COUNT_MASK \ - (0xf << EMC_DLL_CFG_0_DDLLCAL_CTRL_END_COUNT_SHIFT) -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_FILTER_BITS_SHIFT 16 -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_FILTER_BITS_MASK \ - (0xf << EMC_DLL_CFG_0_DDLLCAL_CTRL_FILTER_BITS_SHIFT) -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_COUNT_SHIFT 12 -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_COUNT_MASK \ - (0xf << EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_COUNT_SHIFT) -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_DELAY_SHIFT 4 -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_DELAY_MASK \ - (0xff << EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_DELAY_SHIFT) -#define EMC_DLL_CFG_0_DDLLCAL_UPDATE_CNT_LIMIT_SHIFT 0 -#define EMC_DLL_CFG_0_DDLLCAL_UPDATE_CNT_LIMIT_MASK \ - (0xf << EMC_DLL_CFG_0_DDLLCAL_UPDATE_CNT_LIMIT_SHIFT) - -#define EMC_DLL_CFG_1 0x5e8 -#define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT 10 -#define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_MASK \ - (0x7ff << EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT) - -#define EMC_TRAINING_CMD 0xe00 -#define EMC_TRAINING_CMD_PRIME (1 << 0) -#define EMC_TRAINING_CMD_CA (1 << 1) -#define EMC_TRAINING_CMD_RD (1 << 2) -#define EMC_TRAINING_CMD_WR (1 << 3) -#define EMC_TRAINING_CMD_QUSE (1 << 4) -#define EMC_TRAINING_CMD_CA_VREF (1 << 5) -#define EMC_TRAINING_CMD_RD_VREF (1 << 6) -#define EMC_TRAINING_CMD_WR_VREF (1 << 7) -#define EMC_TRAINING_CMD_QUSE_VREF (1 << 8) -#define EMC_TRAINING_CMD_GO (1 << 31) - -#define EMC_TRAINING_CTRL 0xe04 -#define EMC_TRAINING_CTRL_SWAP_RANK (1 << 14) - -#define EMC_TRAINING_STATUS 0xe08 -#define EMC_TRAINING_QUSE_CORS_CTRL 0xe0c -#define EMC_TRAINING_QUSE_FINE_CTRL 0xe10 -#define EMC_TRAINING_QUSE_CTRL_MISC 0xe14 -#define EMC_TRAINING_WRITE_FINE_CTRL 0xe18 -#define EMC_TRAINING_WRITE_CTRL_MISC 0xe1c -#define EMC_TRAINING_WRITE_VREF_CTRL 0xe20 -#define EMC_TRAINING_READ_FINE_CTRL 0xe24 -#define EMC_TRAINING_READ_CTRL_MISC 0xe28 -#define EMC_TRAINING_READ_VREF_CTRL 0xe2c -#define EMC_TRAINING_CA_FINE_CTRL 0xe30 -#define EMC_TRAINING_CA_CTRL_MISC 0xe34 -#define EMC_TRAINING_CA_CTRL_MISC1 0xe38 -#define EMC_TRAINING_CA_VREF_CTRL 0xe3c -#define EMC_TRAINING_CA_TADR_CTRL 0xe40 -#define EMC_TRAINING_SETTLE 0xe44 -#define EMC_TRAINING_DEBUG_CTRL 0xe48 -#define EMC_TRAINING_DEBUG_DQ0 0xe4c -#define EMC_TRAINING_DEBUG_DQ1 0xe50 -#define EMC_TRAINING_DEBUG_DQ2 0xe54 -#define EMC_TRAINING_DEBUG_DQ3 0xe58 -#define EMC_TRAINING_MPC 0xe5c -#define EMC_TRAINING_PATRAM_CTRL 0xe60 -#define EMC_TRAINING_PATRAM_DQ 0xe64 -#define EMC_TRAINING_PATRAM_DMI 0xe68 -#define EMC_TRAINING_VREF_SETTLE 0xe6c -#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE0 0xe70 -#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE1 0xe74 -#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE2 0xe78 -#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE3 0xe7c -#define EMC_TRAINING_RW_EYE_CENTER_IB_MISC 0xe80 -#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE0 0xe84 -#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE1 0xe88 -#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE2 0xe8c -#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE3 0xe90 -#define EMC_TRAINING_RW_EYE_CENTER_OB_MISC 0xe94 -#define EMC_TRAINING_RW_OFFSET_IB_BYTE0 0xe98 -#define EMC_TRAINING_RW_OFFSET_IB_BYTE1 0xe9c -#define EMC_TRAINING_RW_OFFSET_IB_BYTE2 0xea0 -#define EMC_TRAINING_RW_OFFSET_IB_BYTE3 0xea4 -#define EMC_TRAINING_RW_OFFSET_IB_MISC 0xea8 -#define EMC_TRAINING_RW_OFFSET_OB_BYTE0 0xeac -#define EMC_TRAINING_RW_OFFSET_OB_BYTE1 0xeb0 -#define EMC_TRAINING_RW_OFFSET_OB_BYTE2 0xeb4 -#define EMC_TRAINING_RW_OFFSET_OB_BYTE3 0xeb8 -#define EMC_TRAINING_RW_OFFSET_OB_MISC 0xebc -#define EMC_TRAINING_OPT_CA_VREF 0xec0 -#define EMC_TRAINING_OPT_DQ_OB_VREF 0xec4 -#define EMC_TRAINING_OPT_DQ_IB_VREF_RANK0 0xec8 -#define EMC_TRAINING_OPT_DQ_IB_VREF_RANK1 0xecc -#define EMC_TRAINING_QUSE_VREF_CTRL 0xed0 -#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 0xed4 -#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 0xed8 -#define EMC_TRAINING_DRAMC_TIMING 0xedc -#define EMC_PMACRO_QUSE_DDLL_RANK0_0 0x600 -#define EMC_PMACRO_QUSE_DDLL_RANK0_1 0x604 -#define EMC_PMACRO_QUSE_DDLL_RANK0_2 0x608 -#define EMC_PMACRO_QUSE_DDLL_RANK0_3 0x60c -#define EMC_PMACRO_QUSE_DDLL_RANK0_4 0x610 -#define EMC_PMACRO_QUSE_DDLL_RANK0_5 0x614 -#define EMC_PMACRO_QUSE_DDLL_RANK1_0 0x620 -#define EMC_PMACRO_QUSE_DDLL_RANK1_1 0x624 -#define EMC_PMACRO_QUSE_DDLL_RANK1_2 0x628 -#define EMC_PMACRO_QUSE_DDLL_RANK1_3 0x62c -#define EMC_PMACRO_QUSE_DDLL_RANK1_4 0x630 -#define EMC_PMACRO_QUSE_DDLL_RANK1_5 0x634 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 0x640 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_SHIFT \ - 16 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_SHIFT -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_SHIFT \ - 0 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_SHIFT - -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 0x644 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_SHIFT \ - 16 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_SHIFT -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_SHIFT \ - 0 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_SHIFT - -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 0x648 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_SHIFT \ - 16 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_SHIFT -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_SHIFT \ - 0 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_SHIFT - -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 0x64c -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_SHIFT \ - 16 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_SHIFT -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_SHIFT \ - 0 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_SHIFT - -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 0x650 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 0x654 - -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 0x660 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_SHIFT \ - 16 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_SHIFT -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_SHIFT \ - 0 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_SHIFT - -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 0x664 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_SHIFT \ - 16 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_SHIFT -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_SHIFT \ - 0 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_SHIFT - -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 0x668 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_SHIFT \ - 16 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_SHIFT -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_SHIFT \ - 0 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_SHIFT - -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 0x66c -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_SHIFT \ - 16 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_SHIFT -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_SHIFT \ - 0 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_SHIFT - -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4 0x670 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5 0x674 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0 0x680 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1 0x684 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2 0x688 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3 0x68c -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4 0x690 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5 0x694 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0 0x6a0 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1 0x6a4 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2 0x6a8 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3 0x6ac -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4 0x6b0 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5 0x6b4 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0 0x6c0 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1 0x6c4 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2 0x6c8 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3 0x6cc -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4 0x6d0 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5 0x6d4 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0 0x6e0 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1 0x6e4 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2 0x6e8 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3 0x6ec -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4 0x6f0 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5 0x6f4 -#define EMC_PMACRO_TX_PWRD_0 0x720 -#define EMC_PMACRO_TX_PWRD_1 0x724 -#define EMC_PMACRO_TX_PWRD_2 0x728 -#define EMC_PMACRO_TX_PWRD_3 0x72c -#define EMC_PMACRO_TX_PWRD_4 0x730 -#define EMC_PMACRO_TX_PWRD_5 0x734 -#define EMC_PMACRO_TX_SEL_CLK_SRC_0 0x740 -#define EMC_PMACRO_TX_SEL_CLK_SRC_1 0x744 -#define EMC_PMACRO_TX_SEL_CLK_SRC_3 0x74c -#define EMC_PMACRO_TX_SEL_CLK_SRC_2 0x748 -#define EMC_PMACRO_TX_SEL_CLK_SRC_4 0x750 -#define EMC_PMACRO_TX_SEL_CLK_SRC_5 0x754 -#define EMC_PMACRO_DDLL_BYPASS 0x760 -#define EMC_PMACRO_DDLL_PWRD_0 0x770 -#define EMC_PMACRO_DDLL_PWRD_1 0x774 -#define EMC_PMACRO_DDLL_PWRD_2 0x778 -#define EMC_PMACRO_CMD_CTRL_0 0x780 -#define EMC_PMACRO_CMD_CTRL_1 0x784 -#define EMC_PMACRO_CMD_CTRL_2 0x788 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0x800 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0x804 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0x808 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 0x80c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0x810 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0x814 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0x818 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 0x81c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0x820 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0x824 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0x828 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 0x82c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0x830 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0x834 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0x838 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 0x83c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0x840 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0x844 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0x848 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 0x84c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0x850 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0x854 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0x858 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 0x85c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0x860 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0x864 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0x868 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 0x86c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0x870 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0x874 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0x878 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 0x87c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 0x880 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 0x884 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 0x888 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3 0x88c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 0x890 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 0x894 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 0x898 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3 0x89c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 0x8a0 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 0x8a4 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 0x8a8 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3 0x8ac -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 0x8b0 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 0x8b4 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 0x8b8 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3 0x8bc -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0x900 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0x904 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0x908 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 0x90c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0x910 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0x914 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0x918 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 0x91c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0x920 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0x924 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0x928 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 0x92c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0x930 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0x934 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0x938 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 0x93c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0x940 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0x944 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0x948 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 0x94c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0x950 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0x954 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0x958 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 0x95c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0x960 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0x964 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0x968 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 0x96c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0x970 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0x974 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0x978 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 0x97c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0 0x980 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1 0x984 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2 0x988 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3 0x98c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0 0x990 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1 0x994 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2 0x998 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3 0x99c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0 0x9a0 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1 0x9a4 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2 0x9a8 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3 0x9ac -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0 0x9b0 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1 0x9b4 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2 0x9b8 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3 0x9bc -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0xa00 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0xa04 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0xa08 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0xa10 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0xa14 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0xa18 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0xa20 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0xa24 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0xa28 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0xa30 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0xa34 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0xa38 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0xa40 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0xa44 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0xa48 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0xa50 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0xa54 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0xa58 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0xa60 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0xa64 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0xa68 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0xa70 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0xa74 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0xa78 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0 0xa80 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1 0xa84 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2 0xa88 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0 0xa90 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1 0xa94 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2 0xa98 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0 0xaa0 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1 0xaa4 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2 0xaa8 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0 0xab0 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1 0xab4 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2 0xab8 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0xb00 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0xb04 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0xb08 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0xb10 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0xb14 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0xb18 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0xb20 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0xb24 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0xb28 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0xb30 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0xb34 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0xb38 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0xb40 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0xb44 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0xb48 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0xb50 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0xb54 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0xb58 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0xb60 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0xb64 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0xb68 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0xb70 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0xb74 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0xb78 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0 0xb80 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1 0xb84 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2 0xb88 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0 0xb90 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1 0xb94 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2 0xb98 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0 0xba0 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1 0xba4 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2 0xba8 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0 0xbb0 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1 0xbb4 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2 0xbb8 -#define EMC_PMACRO_IB_VREF_DQ_0 0xbe0 -#define EMC_PMACRO_IB_VREF_DQ_1 0xbe4 -#define EMC_PMACRO_IB_VREF_DQ_2 0xbe8 -#define EMC_PMACRO_IB_VREF_DQS_0 0xbf0 -#define EMC_PMACRO_IB_VREF_DQS_1 0xbf4 -#define EMC_PMACRO_IB_VREF_DQS_2 0xbf8 -#define EMC_PMACRO_IB_RXRT 0xcf4 -#define EMC_PMACRO_DDLL_LONG_CMD_0 0xc00 -#define EMC_PMACRO_DDLL_LONG_CMD_1 0xc04 -#define EMC_PMACRO_DDLL_LONG_CMD_2 0xc08 -#define EMC_PMACRO_DDLL_LONG_CMD_3 0xc0c -#define EMC_PMACRO_DDLL_LONG_CMD_4 0xc10 -#define EMC_PMACRO_DDLL_LONG_CMD_5 0xc14 -#define EMC_PMACRO_DDLL_SHORT_CMD_0 0xc20 -#define EMC_PMACRO_DDLL_SHORT_CMD_1 0xc24 -#define EMC_PMACRO_DDLL_SHORT_CMD_2 0xc28 -#define EMC_PMACRO_CFG_PM_GLOBAL_0 0xc30 -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE0 (1 << 16) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE1 (1 << 17) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE2 (1 << 18) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE3 (1 << 19) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE4 (1 << 20) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE5 (1 << 21) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE6 (1 << 22) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE7 (1 << 23) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD0 (1 << 24) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD1 (1 << 25) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD2 (1 << 26) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD3 (1 << 27) - -#define EMC_PMACRO_VTTGEN_CTRL_0 0xc34 -#define EMC_PMACRO_VTTGEN_CTRL_1 0xc38 -#define EMC_PMACRO_VTTGEN_CTRL_2 0xcf0 -#define EMC_PMACRO_BG_BIAS_CTRL_0 0xc3c -#define EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD (1 << 0) -#define EMC_PMACRO_BG_BIAS_CTRL_0_BG_MODE (1 << 1) -#define EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD (1 << 2) - -#define EMC_PMACRO_PAD_CFG_CTRL 0xc40 -#define EMC_PMACRO_CMD_PAD_RX_CTRL 0xc50 -#define EMC_PMACRO_DATA_PAD_RX_CTRL 0xc54 -#define EMC_PMACRO_CMD_RX_TERM_MODE 0xc58 -#define EMC_PMACRO_DATA_RX_TERM_MODE 0xc5c -#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSN_RX_TERM_MODE_SHIFT 8 -#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSN_RX_TERM_MODE_MASK (0x3 << \ - EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSN_RX_TERM_MODE_SHIFT) -#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSP_RX_TERM_MODE_SHIFT 4 -#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSP_RX_TERM_MODE_MASK (0x3 << \ - EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSP_RX_TERM_MODE_SHIFT) -#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQ_RX_TERM_MODE_SHIFT 0 -#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQ_RX_TERM_MODE_MASK (0x3 << \ - EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQ_RX_TERM_MODE_SHIFT) - -#define RX_TERM_MODE \ - ~(EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSN_RX_TERM_MODE_MASK | \ - EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSP_RX_TERM_MODE_MASK | \ - EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQ_RX_TERM_MODE_MASK) - -#define EMC_PMACRO_CMD_PAD_TX_CTRL 0xc60 -#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_E_DCC (1 << 1) -#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSP_TX_E_DCC (1 << 9) -#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSN_TX_E_DCC (1 << 16) -#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_CMD_TX_E_DCC (1 << 24) -#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_DRVFORCEON (1 << 26) - -#define EMC_PMACRO_DATA_PAD_TX_CTRL 0xc64 -#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_E_IVREF (1 << 0) -#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_TX_E_DCC (1 << 1) -#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF (1 << 8) -#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSP_TX_E_DCC (1 << 9) -#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC (1 << 16) -#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC (1 << 24) - -#define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xc68 -#define EMC_PMACRO_BRICK_MAPPING_0 0xc80 -#define EMC_PMACRO_BRICK_MAPPING_1 0xc84 -#define EMC_PMACRO_BRICK_MAPPING_2 0xc88 -#define EMC_PMACRO_DDLLCAL_CAL 0xce0 -#define EMC_PMACRO_DDLL_OFFSET 0xce4 -#define EMC_PMACRO_DDLL_PERIODIC_OFFSET 0xce8 -#define EMC_PMACRO_BRICK_CTRL_RFU1 0x330 -#define EMC_PMACRO_BRICK_CTRL_RFU2 0x334 -#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD 0x318 -#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD 0x31c -#define EMC_PMACRO_TRAINING_CTRL_0 0xcf8 -#define EMC_PMACRO_TRAINING_CTRL_0_CH0_TRAINING_E_WRPTR (1 << 3) - -#define EMC_PMACRO_TRAINING_CTRL_1 0xcfc -#define EMC_PMACRO_TRAINING_CTRL_1_CH1_TRAINING_E_WRPTR (1 << 3) - -#define EMC_PMC_SCRATCH1 0x440 -#define EMC_PMC_SCRATCH2 0x444 -#define EMC_PMC_SCRATCH3 0x448 - -#endif +/* + * arch/arm/mach-tegra/tegra21_emc.h + * + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2020 Atmosphère-NX + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ + +#ifndef FUSEE_EMC_H_ +#define FUSEE_EMC_H_ + +#define EMC_BASE 0x7001B000 +#define EMC0_BASE 0x7001E000 +#define EMC1_BASE 0x7001F000 +#define MAKE_EMC_REG(n) MAKE_REG32(EMC_BASE + n) +#define MAKE_EMC0_REG(n) MAKE_REG32(EMC0_BASE + n) +#define MAKE_EMC1_REG(n) MAKE_REG32(EMC1_BASE + n) + +#define EMC_INTSTATUS 0x0 +#define EMC_INTSTATUS_MRR_DIVLD (0x1 << 5) +#define EMC_INTSTATUS_CLKCHANGE_COMPLETE (0x1 << 4) + +#define EMC_INTMASK 0x4 +#define EMC_DBG 0x8 +#define EMC_DBG_WRITE_MUX_ACTIVE (1 << 1) +#define EMC_DBG_CFG_SWAP_SHIFT 26 +#define EMC_DBG_CFG_SWAP_MASK \ + (0x3 << EMC_DBG_CFG_SWAP_SHIFT) +#define EMC_DBG_WRITE_ACTIVE_ONLY (1 << 30) + +#define EMC_CONFIG_SAMPLE_DELAY 0x5f0 +#define EMC_CFG_UPDATE 0x5f4 +#define EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT 9 +#define EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_MASK \ + (0x3 << EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT) +#define EMC_CFG 0xc +#define EMC_CFG_DRAM_CLKSTOP_PD (1 << 31) +#define EMC_CFG_DRAM_CLKSTOP_SR (1 << 30) +#define EMC_CFG_DRAM_ACPD (1 << 29) +#define EMC_CFG_DYN_SELF_REF (1 << 28) +#define EMC_CFG_REQACT_ASYNC (1 << 26) +#define EMC_CFG_AUTO_PRE_WR (1 << 25) +#define EMC_CFG_AUTO_PRE_RD (1 << 24) +#define EMC_CFG_MAM_PRE_WR (1 << 23) +#define EMC_CFG_MAN_PRE_RD (1 << 22) +#define EMC_CFG_PERIODIC_QRST (1 << 21) +#define EMC_CFG_PERIODIC_QRST_SHIFT (21) +#define EMC_CFG_EN_DYNAMIC_PUTERM (1 << 20) +#define EMC_CFG_DLY_WR_DQ_HALF_CLOCK (1 << 19) +#define EMC_CFG_DSR_VTTGEN_DRV_EN (1 << 18) +#define EMC_CFG_EMC2MC_CLK_RATIO (3 << 16) +#define EMC_CFG_WAIT_FOR_ISP2B_READY_B4_CC (1 << 9) +#define EMC_CFG_WAIT_FOR_VI2_READY_B4_CC (1 << 8) +#define EMC_CFG_WAIT_FOR_ISP2_READY_B4_CC (1 << 7) +#define EMC_CFG_INVERT_DQM (1 << 6) +#define EMC_CFG_WAIT_FOR_DISPLAYB_READY_B4_CC (1 << 5) +#define EMC_CFG_WAIT_FOR_DISPLAY_READY_B4_CC (1 << 4) +#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2 (1 << 3) +#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1 (1 << 2) +#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE (1 << 1) + +#define EMC_ADR_CFG 0x10 +#define EMC_REFCTRL 0x20 +#define EMC_REFCTRL_DEV_SEL_SHIFT 0 +#define EMC_REFCTRL_DEV_SEL_MASK \ + (0x3 << EMC_REFCTRL_DEV_SEL_SHIFT) +#define EMC_REFCTRL_ENABLE (0x1 << 31) +#define EMC_REFCTRL_ENABLE_ALL(num) \ + (((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) \ + | EMC_REFCTRL_ENABLE) +#define EMC_REFCTRL_DISABLE_ALL(num) \ + ((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) + +#define EMC_PIN 0x24 +#define EMC_PIN_PIN_CKE_PER_DEV (1 << 2) +#define EMC_PIN_PIN_CKEB (1 << 1) +#define EMC_PIN_PIN_CKE (1 << 0) + +#define EMC_CLK_FORCE_CC_TRIGGER (1 << 27) + +#define EMC_TIMING_CONTROL 0x28 +#define EMC_RC 0x2c +#define EMC_RFC 0x30 +#define EMC_RFCPB 0x590 +#define EMC_RAS 0x34 +#define EMC_RP 0x38 +#define EMC_R2W 0x3c +#define EMC_W2R 0x40 +#define EMC_R2P 0x44 +#define EMC_W2P 0x48 +#define EMC_CCDMW 0x5c0 +#define EMC_RD_RCD 0x4c +#define EMC_WR_RCD 0x50 +#define EMC_RRD 0x54 +#define EMC_REXT 0x58 +#define EMC_WDV 0x5c +#define EMC_QUSE 0x60 +#define EMC_QRST 0x64 +#define EMC_ISSUE_QRST 0x428 +#define EMC_QSAFE 0x68 +#define EMC_RDV 0x6c +#define EMC_REFRESH 0x70 +#define EMC_BURST_REFRESH_NUM 0x74 +#define EMC_PDEX2WR 0x78 +#define EMC_PDEX2RD 0x7c +#define EMC_PDEX2CKE 0x118 +#define EMC_PCHG2PDEN 0x80 +#define EMC_ACT2PDEN 0x84 +#define EMC_AR2PDEN 0x88 +#define EMC_RW2PDEN 0x8c +#define EMC_CKE2PDEN 0x11c +#define EMC_TXSR 0x90 +#define EMC_TCKE 0x94 +#define EMC_TFAW 0x98 +#define EMC_TRPAB 0x9c +#define EMC_TCLKSTABLE 0xa0 +#define EMC_TCLKSTOP 0xa4 +#define EMC_TREFBW 0xa8 +#define EMC_TPPD 0xac +#define EMC_PDEX2MRR 0xb4 +#define EMC_ODT_WRITE 0xb0 +#define EMC_WEXT 0xb8 +#define EMC_RFC_SLR 0xc0 +#define EMC_MRS_WAIT_CNT2 0xc4 +#define EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_SHIFT 16 +#define EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_MASK \ + (0x7ff << EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_SHIFT) +#define EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_SHIFT 0 +#define EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_MASK \ + (0x3ff << EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_SHIFT) + +#define EMC_MRS_WAIT_CNT 0xc8 +#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0 +#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \ + (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT) +#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16 +#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \ + (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) + +#define EMC_MRS 0xcc +#define EMC_MODE_SET_DLL_RESET (1 << 8) +#define EMC_MRS_USE_MRS_LONG_CNT (1 << 26) + +#define EMC_EMRS 0xd0 +#define EMC_EMRS_USE_EMRS_LONG_CNT (1 << 26) + +#define EMC_REF 0xd4 +#define EMC_REF_FORCE_CMD 1 + +#define EMC_PRE 0xd8 +#define EMC_NOP 0xdc +#define EMC_SELF_REF 0xe0 +#define EMC_SELF_REF_CMD_ENABLED (1 << 0) +#define EMC_SELF_REF_ACTIVE_SELF_REF (1 << 8) +#define EMC_SELF_REF_DEV_SEL_SHIFT 30 +#define EMC_SELF_REF_DEV_SEL_MASK \ + (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT) + +#define EMC_DPD 0xe4 +#define EMC_MRW 0xe8 +#define EMC_MRW_MRW_OP_SHIFT 0 +#define EMC_MRW_MRW_OP_MASK \ + (0xff << EMC_MRW_MRW_OP_SHIFT) +#define EMC_MRW_MRW_MA_SHIFT 16 +#define EMC_MRW_MRW_MA_MASK \ + (0xff << EMC_MRW_MRW_MA_SHIFT) +#define EMC_MRW_USE_MRW_LONG_CNT 26 +#define EMC_MRW_USE_MRW_EXT_CNT 27 +#define EMC_MRW_MRW_DEV_SELECTN_SHIFT 30 +#define EMC_MRW_MRW_DEV_SELECTN_MASK \ + (0x3 << EMC_MRW_MRW_DEV_SELECTN_SHIFT) + +#define EMC_MRR 0xec +#define EMC_MRR_DEV_SEL_SHIFT 30 +#define EMC_MRR_DEV_SEL_MASK \ + (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT) +#define EMC_MRR_MA_SHIFT 16 +#define EMC_MRR_MA_MASK \ + (0xff << EMC_MRR_MA_SHIFT) +#define EMC_MRR_DATA_SHIFT 0 +#define EMC_MRR_DATA_MASK \ + (0xffff << EMC_MRR_DATA_SHIFT) +#define LPDDR2_MR4_TEMP_SHIFT 0 +#define LPDDR2_MR4_TEMP_MASK \ + (0x7 << LPDDR2_MR4_TEMP_SHIFT) + +#define EMC_CMDQ 0xf0 +#define EMC_MC2EMCQ 0xf4 +#define EMC_FBIO_SPARE 0x100 +#define EMC_FBIO_CFG5 0x104 +#define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0 +#define EMC_FBIO_CFG5_DRAM_TYPE_MASK \ + (0x3 << EMC_FBIO_CFG5_DRAM_TYPE_SHIFT) +#define EMC_FBIO_CFG5_CMD_TX_DIS (1 << 8) +#define EMC_FBIO_CFG5_CMD_BUS_RETURN_TO_ZERO (1 << 27) + +#define EMC_CFG5_QUSE_MODE_SHIFT 13 +#define EMC_CFG5_QUSE_MODE_MASK \ + (0x7 << EMC_CFG5_QUSE_MODE_SHIFT) + +#define EMC_CFG_RSV 0x120 +#define EMC_ACPD_CONTROL 0x124 +#define EMC_MPC 0x128 +#define EMC_EMRS2 0x12c +#define EMC_EMRS2_USE_EMRS2_LONG_CNT (1 << 26) + +#define EMC_EMRS3 0x130 +#define EMC_MRW2 0x134 +#define EMC_MRW3 0x138 +#define EMC_MRW4 0x13c +#define EMC_MRW5 0x4a0 +#define EMC_MRW6 0x4a4 +#define EMC_MRW7 0x4a8 +#define EMC_MRW8 0x4ac +#define EMC_MRW9 0x4b0 +#define EMC_MRW10 0x4b4 +#define EMC_MRW11 0x4b8 +#define EMC_MRW12 0x4bc +#define EMC_MRW13 0x4c0 +#define EMC_MRW14 0x4c4 +#define EMC_MRW15 0x4d0 +#define EMC_CFG_SYNC 0x4d4 +#define EMC_CLKEN_OVERRIDE 0x140 +#define EMC_R2R 0x144 +#define EMC_W2W 0x148 +#define EMC_EINPUT 0x14c +#define EMC_EINPUT_DURATION 0x150 +#define EMC_PUTERM_EXTRA 0x154 +#define EMC_TCKESR 0x158 +#define EMC_TPD 0x15c +#define EMC_STAT_CONTROL 0x160 +#define EMC_STAT_STATUS 0x164 +#define EMC_STAT_DRAM_CLOCK_LIMIT_LO 0x19c +#define EMC_STAT_DRAM_CLOCK_LIMIT_HI 0x1a0 +#define EMC_STAT_DRAM_CLOCKS_LO 0x1a4 +#define EMC_STAT_DRAM_CLOCKS_HI 0x1a8 +#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO 0x1ac +#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI 0x1b0 +#define EMC_STAT_DRAM_DEV0_READ_CNT_LO 0x1b4 +#define EMC_STAT_DRAM_DEV0_READ_CNT_HI 0x1b8 +#define EMC_STAT_DRAM_DEV0_READ8_CNT_LO 0x1bc +#define EMC_STAT_DRAM_DEV0_READ8_CNT_HI 0x1c0 +#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO 0x1c4 +#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI 0x1c8 +#define EMC_STAT_DRAM_DEV0_WRITE8_CNT_LO 0x1cc +#define EMC_STAT_DRAM_DEV0_WRITE8_CNT_HI 0x1d0 +#define EMC_STAT_DRAM_DEV0_REF_CNT_LO 0x1d4 +#define EMC_STAT_DRAM_DEV0_REF_CNT_HI 0x1d8 +#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x1dc +#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x1e0 +#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x1e4 +#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x1e8 +#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x1ec +#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x1f0 +#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x1f4 +#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x1f8 +#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x1fc +#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x200 +#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x204 +#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x208 +#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x20c +#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x210 +#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x214 +#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x218 +#define EMC_STAT_DRAM_DEV0_SR_CKE_EQ0_CLKS_LO 0x21c +#define EMC_STAT_DRAM_DEV0_SR_CKE_EQ0_CLKS_HI 0x220 +#define EMC_STAT_DRAM_DEV0_DSR 0x224 +#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO 0x228 +#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI 0x22c +#define EMC_STAT_DRAM_DEV1_READ_CNT_LO 0x230 +#define EMC_STAT_DRAM_DEV1_READ_CNT_HI 0x234 +#define EMC_STAT_DRAM_DEV1_READ8_CNT_LO 0x238 +#define EMC_STAT_DRAM_DEV1_READ8_CNT_HI 0x23c +#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO 0x240 +#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI 0x244 +#define EMC_STAT_DRAM_DEV1_WRITE8_CNT_LO 0x248 +#define EMC_STAT_DRAM_DEV1_WRITE8_CNT_HI 0x24c +#define EMC_STAT_DRAM_DEV1_REF_CNT_LO 0x250 +#define EMC_STAT_DRAM_DEV1_REF_CNT_HI 0x254 +#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x258 +#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x25c +#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x260 +#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x264 +#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x268 +#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x26c +#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x270 +#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x274 +#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x278 +#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x27c +#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x280 +#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x284 +#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x288 +#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x28c +#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x290 +#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x294 +#define EMC_STAT_DRAM_DEV1_SR_CKE_EQ0_CLKS_LO 0x298 +#define EMC_STAT_DRAM_DEV1_SR_CKE_EQ0_CLKS_HI 0x29c +#define EMC_STAT_DRAM_DEV1_DSR 0x2a0 +#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0xc8c +#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0xc90 +#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0xc94 +#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0xc98 +#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0xc9c +#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0xca0 +#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0xca4 +#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0xca8 +#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0xcac +#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0xcb0 +#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0xcb4 +#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0xcb8 +#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0xcbc +#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0xcc0 +#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0xcc4 +#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0xcc8 +#define EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_LO 0xccc +#define EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_HI 0xcd0 +#define EMC_STAT_DRAM_IO_DSR 0xcd4 +#define EMC_AUTO_CAL_CONFIG 0x2a4 +#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_COMPUTE_START (1 << 0) +#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_MEASURE_STALL (1 << 9) +#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_UPDATE_STALL (1 << 10) +#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE (1 << 29) +#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START (1 << 31) + +#define EMC_AUTO_CAL_CONFIG2 0x458 +#define EMC_AUTO_CAL_CONFIG3 0x45c +#define EMC_AUTO_CAL_CONFIG4 0x5b0 +#define EMC_AUTO_CAL_CONFIG5 0x5b4 +#define EMC_AUTO_CAL_CONFIG6 0x5cc +#define EMC_AUTO_CAL_CONFIG7 0x574 +#define EMC_AUTO_CAL_CONFIG8 0x2dc +#define EMC_AUTO_CAL_VREF_SEL_0 0x2f8 +#define EMC_AUTO_CAL_VREF_SEL_1 0x300 +#define EMC_AUTO_CAL_INTERVAL 0x2a8 +#define EMC_AUTO_CAL_STATUS 0x2ac +#define EMC_AUTO_CAL_STATUS2 0x3d4 +#define EMC_AUTO_CAL_CHANNEL 0x464 +#define EMC_PMACRO_RX_TERM 0xc48 +#define EMC_PMACRO_DQ_TX_DRV 0xc70 +#define EMC_PMACRO_CA_TX_DRV 0xc74 +#define EMC_PMACRO_CMD_TX_DRV 0xc4c +#define EMC_PMACRO_AUTOCAL_CFG_0 0x700 +#define EMC_PMACRO_AUTOCAL_CFG_1 0x704 +#define EMC_PMACRO_AUTOCAL_CFG_2 0x708 +#define EMC_PMACRO_AUTOCAL_CFG_COMMON 0xc78 +#define EMC_PMACRO_AUTOCAL_CFG_COMMON_E_CAL_BYPASS_DVFS (1 << 16) + +#define EMC_PMACRO_ZCTRL 0xc44 +#define EMC_XM2COMPPADCTRL 0x30c +#define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE (1 << 10) + +#define EMC_XM2COMPPADCTRL2 0x578 +#define EMC_XM2COMPPADCTRL3 0x2f4 +#define EMC_COMP_PAD_SW_CTRL 0x57c +#define EMC_REQ_CTRL 0x2b0 +#define EMC_EMC_STATUS 0x2b4 +#define EMC_EMC_STATUS_MRR_DIVLD (1 << 20) +#define EMC_EMC_STATUS_TIMING_UPDATE_STALLED (1 << 23) +#define EMC_EMC_STATUS_DRAM_IN_POWERDOWN_SHIFT 4 +#define EMC_EMC_STATUS_DRAM_IN_POWERDOWN_MASK \ + (0x3 << EMC_EMC_STATUS_DRAM_IN_POWERDOWN_SHIFT) +#define EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_SHIFT 8 +#define EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_MASK \ + (0x3 << EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_SHIFT) + +#define EMC_CFG_2 0x2b8 +#define EMC_CFG_DIG_DLL 0x2bc +#define EMC_CFG_DIG_DLL_CFG_DLL_EN (1 << 0) +#define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_UNTIL_LOCK (1 << 1) +#define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_TRAFFIC (1 << 3) +#define EMC_CFG_DIG_DLL_CFG_DLL_STALL_RW_UNTIL_LOCK (1 << 4) +#define EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT 6 +#define EMC_CFG_DIG_DLL_CFG_DLL_MODE_MASK \ + (0x3 << EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT) +#define EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT 8 +#define EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_MASK \ + (0x7 << EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT) + +#define EMC_CFG_DIG_DLL_PERIOD 0x2c0 +#define EMC_DIG_DLL_STATUS 0x2c4 +#define EMC_DIG_DLL_STATUS_DLL_LOCK (1 << 15) +#define EMC_DIG_DLL_STATUS_DLL_PRIV_UPDATED (1 << 17) +#define EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT 0 +#define EMC_DIG_DLL_STATUS_DLL_OUT_MASK \ + (0x7ff << EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT) + +#define EMC_CFG_DIG_DLL_1 0x2c8 +#define EMC_RDV_MASK 0x2cc +#define EMC_WDV_MASK 0x2d0 +#define EMC_RDV_EARLY_MASK 0x2d4 +#define EMC_RDV_EARLY 0x2d8 +#define EMC_WDV_CHK 0x4e0 +#define EMC_ZCAL_INTERVAL 0x2e0 +#define EMC_ZCAL_WAIT_CNT 0x2e4 +#define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_MASK 0x7ff +#define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_SHIFT 0 + +#define EMC_ZCAL_MRW_CMD 0x2e8 +#define EMC_ZQ_CAL 0x2ec +#define EMC_ZQ_CAL_DEV_SEL_SHIFT 30 +#define EMC_ZQ_CAL_DEV_SEL_MASK \ + (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT) +#define EMC_ZQ_CAL_LONG (1 << 4) +#define EMC_ZQ_CAL_ZQ_LATCH_CMD (1 << 1) +#define EMC_ZQ_CAL_ZQ_CAL_CMD (1 << 0) +#define EMC_ZQ_CAL_LONG_CMD_DEV0 \ + (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) +#define EMC_ZQ_CAL_LONG_CMD_DEV1 \ + (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) + +#define EMC_SCRATCH0 0x324 +#define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE 0x3c8 +#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc +#define EMC_UNSTALL_RW_AFTER_CLKCHANGE 0x3d0 +#define EMC_FDPD_CTRL_CMD_NO_RAMP 0x4d8 +#define EMC_FDPD_CTRL_CMD_NO_RAMP_CMD_DPD_NO_RAMP_ENABLE (1 << 0) + +#define EMC_SEL_DPD_CTRL 0x3d8 +#define EMC_SEL_DPD_CTRL_DATA_SEL_DPD_EN (1 << 8) +#define EMC_SEL_DPD_CTRL_ODT_SEL_DPD_EN (1 << 5) +#define EMC_SEL_DPD_CTRL_RESET_SEL_DPD_EN (1 << 4) +#define EMC_SEL_DPD_CTRL_CA_SEL_DPD_EN (1 << 3) +#define EMC_SEL_DPD_CTRL_CLK_SEL_DPD_EN (1 << 2) +#define EMC_SEL_DPD_CTRL_DDR3_MASK \ + ((0xf << 2) | (0x1 << 8)) +#define EMC_SEL_DPD_CTRL_MAS \ + ((0x3 << 2) | (0x1 << 5) | (0x1 << 8)) + +#define EMC_FDPD_CTRL_DQ 0x310 +#define EMC_FDPD_CTRL_CMD 0x314 +#define EMC_PRE_REFRESH_REQ_CNT 0x3dc +#define EMC_REFCTRL2 0x580 +#define EMC_FBIO_CFG7 0x584 +#define EMC_FBIO_CFG7_CH0_ENABLE (1 << 1) +#define EMC_FBIO_CFG7_CH1_ENABLE (1 << 2) + +#define EMC_DATA_BRLSHFT_0 0x588 +#define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT 21 +#define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_MASK \ + (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT) +#define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT 18 +#define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_MASK \ + (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT) +#define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT 15 +#define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_MASK \ + (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT) +#define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT 12 +#define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_MASK \ + (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT) +#define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT 9 +#define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_MASK \ + (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT) +#define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT 6 +#define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_MASK \ + (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT) +#define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT 3 +#define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_MASK \ + (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT) +#define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT 0 +#define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_MASK \ + (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT) + +#define EMC_DATA_BRLSHFT_1 0x58c +#define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT 21 +#define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_MASK \ + (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT) +#define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT 18 +#define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_MASK \ + (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT) +#define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT 15 +#define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_MASK \ + (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT) +#define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT 12 +#define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_MASK \ + (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT) +#define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT 9 +#define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_MASK \ + (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT) +#define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT 6 +#define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_MASK \ + (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT) +#define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT 3 +#define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_MASK \ + (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT) +#define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT 0 +#define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_MASK \ + (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT) + +#define EMC_DQS_BRLSHFT_0 0x594 +#define EMC_DQS_BRLSHFT_1 0x598 +#define EMC_CMD_BRLSHFT_0 0x59c +#define EMC_CMD_BRLSHFT_1 0x5a0 +#define EMC_CMD_BRLSHFT_2 0x5a4 +#define EMC_CMD_BRLSHFT_3 0x5a8 +#define EMC_QUSE_BRLSHFT_0 0x5ac +#define EMC_QUSE_BRLSHFT_1 0x5b8 +#define EMC_QUSE_BRLSHFT_2 0x5bc +#define EMC_QUSE_BRLSHFT_3 0x5c4 +#define EMC_FBIO_CFG8 0x5c8 +#define EMC_CMD_MAPPING_CMD0_0 0x380 +#define EMC_CMD_MAPPING_CMD0_1 0x384 +#define EMC_CMD_MAPPING_CMD0_2 0x388 +#define EMC_CMD_MAPPING_CMD1_0 0x38c +#define EMC_CMD_MAPPING_CMD1_1 0x390 +#define EMC_CMD_MAPPING_CMD1_2 0x394 +#define EMC_CMD_MAPPING_CMD2_0 0x398 +#define EMC_CMD_MAPPING_CMD2_1 0x39c +#define EMC_CMD_MAPPING_CMD2_2 0x3a0 +#define EMC_CMD_MAPPING_CMD3_0 0x3a4 +#define EMC_CMD_MAPPING_CMD3_1 0x3a8 +#define EMC_CMD_MAPPING_CMD3_2 0x3ac +#define EMC_CMD_MAPPING_BYTE 0x3b0 +#define EMC_DYN_SELF_REF_CONTROL 0x3e0 +#define EMC_TXSRDLL 0x3e4 +#define EMC_CCFIFO_ADDR 0x3e8 +#define EMC_CCFIFO_DATA 0x3ec +#define EMC_CCFIFO_STATUS 0x3f0 +#define EMC_SWIZZLE_RANK0_BYTE0 0x404 +#define EMC_SWIZZLE_RANK0_BYTE1 0x408 +#define EMC_SWIZZLE_RANK0_BYTE2 0x40c +#define EMC_SWIZZLE_RANK0_BYTE3 0x410 +#define EMC_SWIZZLE_RANK1_BYTE0 0x418 +#define EMC_SWIZZLE_RANK1_BYTE1 0x41c +#define EMC_SWIZZLE_RANK1_BYTE2 0x420 +#define EMC_SWIZZLE_RANK1_BYTE3 0x424 +#define EMC_TR_TIMING_0 0x3b4 +#define EMC_TR_CTRL_0 0x3b8 +#define EMC_TR_CTRL_1 0x3bc +#define EMC_TR_DVFS 0x460 +#define EMC_TR_DVFS_TRAINING_DVFS (1 << 0) + +#define EMC_SWITCH_BACK_CTRL 0x3c0 +#define EMC_TR_RDV 0x3c4 +#define EMC_TR_QPOP 0x3f4 +#define EMC_TR_RDV_MASK 0x3f8 +#define EMC_TR_QSAFE 0x3fc +#define EMC_TR_QRST 0x400 +#define EMC_IBDLY 0x468 +#define EMC_OBDLY 0x46c +#define EMC_TXDSRVTTGEN 0x480 +#define EMC_WE_DURATION 0x48c +#define EMC_WS_DURATION 0x490 +#define EMC_WEV 0x494 +#define EMC_WSV 0x498 +#define EMC_CFG_3 0x49c +#define EMC_CFG_PIPE_2 0x554 +#define EMC_CFG_PIPE_CLK 0x558 +#define EMC_CFG_PIPE_CLK_CLK_ALWAYS_ON (1 << 0) + +#define EMC_CFG_PIPE_1 0x55c +#define EMC_CFG_PIPE 0x560 +#define EMC_QPOP 0x564 +#define EMC_QUSE_WIDTH 0x568 +#define EMC_PUTERM_WIDTH 0x56c +#define EMC_PROTOBIST_CONFIG_ADR_1 0x5d0 +#define EMC_PROTOBIST_CONFIG_ADR_2 0x5d4 +#define EMC_PROTOBIST_MISC 0x5d8 +#define EMC_PROTOBIST_WDATA_LOWER 0x5dc +#define EMC_PROTOBIST_WDATA_UPPER 0x5e0 +#define EMC_PROTOBIST_RDATA 0x5ec +#define EMC_DLL_CFG_0 0x5e4 +#define EMC_DLL_CFG_0_DDLLCAL_CTRL_IGNORE_START (1 << 29) +#define EMC_DLL_CFG_0_DDLLCAL_CTRL_DUAL_PASS_LOCK (1 << 28) +#define EMC_DLL_CFG_0_DDLLCAL_CTRL_STEP_SIZE_SHIFT 24 +#define EMC_DLL_CFG_0_DDLLCAL_CTRL_STEP_SIZE_MASK \ + (0xf << EMC_DLL_CFG_0_DDLLCAL_CTRL_STEP_SIZE_SHIFT) +#define EMC_DLL_CFG_0_DDLLCAL_CTRL_END_COUNT_SHIFT 20 +#define EMC_DLL_CFG_0_DDLLCAL_CTRL_END_COUNT_MASK \ + (0xf << EMC_DLL_CFG_0_DDLLCAL_CTRL_END_COUNT_SHIFT) +#define EMC_DLL_CFG_0_DDLLCAL_CTRL_FILTER_BITS_SHIFT 16 +#define EMC_DLL_CFG_0_DDLLCAL_CTRL_FILTER_BITS_MASK \ + (0xf << EMC_DLL_CFG_0_DDLLCAL_CTRL_FILTER_BITS_SHIFT) +#define EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_COUNT_SHIFT 12 +#define EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_COUNT_MASK \ + (0xf << EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_COUNT_SHIFT) +#define EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_DELAY_SHIFT 4 +#define EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_DELAY_MASK \ + (0xff << EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_DELAY_SHIFT) +#define EMC_DLL_CFG_0_DDLLCAL_UPDATE_CNT_LIMIT_SHIFT 0 +#define EMC_DLL_CFG_0_DDLLCAL_UPDATE_CNT_LIMIT_MASK \ + (0xf << EMC_DLL_CFG_0_DDLLCAL_UPDATE_CNT_LIMIT_SHIFT) + +#define EMC_DLL_CFG_1 0x5e8 +#define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT 10 +#define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_MASK \ + (0x7ff << EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT) + +#define EMC_TRAINING_CMD 0xe00 +#define EMC_TRAINING_CMD_PRIME (1 << 0) +#define EMC_TRAINING_CMD_CA (1 << 1) +#define EMC_TRAINING_CMD_RD (1 << 2) +#define EMC_TRAINING_CMD_WR (1 << 3) +#define EMC_TRAINING_CMD_QUSE (1 << 4) +#define EMC_TRAINING_CMD_CA_VREF (1 << 5) +#define EMC_TRAINING_CMD_RD_VREF (1 << 6) +#define EMC_TRAINING_CMD_WR_VREF (1 << 7) +#define EMC_TRAINING_CMD_QUSE_VREF (1 << 8) +#define EMC_TRAINING_CMD_GO (1 << 31) + +#define EMC_TRAINING_CTRL 0xe04 +#define EMC_TRAINING_CTRL_SWAP_RANK (1 << 14) + +#define EMC_TRAINING_STATUS 0xe08 +#define EMC_TRAINING_QUSE_CORS_CTRL 0xe0c +#define EMC_TRAINING_QUSE_FINE_CTRL 0xe10 +#define EMC_TRAINING_QUSE_CTRL_MISC 0xe14 +#define EMC_TRAINING_WRITE_FINE_CTRL 0xe18 +#define EMC_TRAINING_WRITE_CTRL_MISC 0xe1c +#define EMC_TRAINING_WRITE_VREF_CTRL 0xe20 +#define EMC_TRAINING_READ_FINE_CTRL 0xe24 +#define EMC_TRAINING_READ_CTRL_MISC 0xe28 +#define EMC_TRAINING_READ_VREF_CTRL 0xe2c +#define EMC_TRAINING_CA_FINE_CTRL 0xe30 +#define EMC_TRAINING_CA_CTRL_MISC 0xe34 +#define EMC_TRAINING_CA_CTRL_MISC1 0xe38 +#define EMC_TRAINING_CA_VREF_CTRL 0xe3c +#define EMC_TRAINING_CA_TADR_CTRL 0xe40 +#define EMC_TRAINING_SETTLE 0xe44 +#define EMC_TRAINING_DEBUG_CTRL 0xe48 +#define EMC_TRAINING_DEBUG_DQ0 0xe4c +#define EMC_TRAINING_DEBUG_DQ1 0xe50 +#define EMC_TRAINING_DEBUG_DQ2 0xe54 +#define EMC_TRAINING_DEBUG_DQ3 0xe58 +#define EMC_TRAINING_MPC 0xe5c +#define EMC_TRAINING_PATRAM_CTRL 0xe60 +#define EMC_TRAINING_PATRAM_DQ 0xe64 +#define EMC_TRAINING_PATRAM_DMI 0xe68 +#define EMC_TRAINING_VREF_SETTLE 0xe6c +#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE0 0xe70 +#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE1 0xe74 +#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE2 0xe78 +#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE3 0xe7c +#define EMC_TRAINING_RW_EYE_CENTER_IB_MISC 0xe80 +#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE0 0xe84 +#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE1 0xe88 +#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE2 0xe8c +#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE3 0xe90 +#define EMC_TRAINING_RW_EYE_CENTER_OB_MISC 0xe94 +#define EMC_TRAINING_RW_OFFSET_IB_BYTE0 0xe98 +#define EMC_TRAINING_RW_OFFSET_IB_BYTE1 0xe9c +#define EMC_TRAINING_RW_OFFSET_IB_BYTE2 0xea0 +#define EMC_TRAINING_RW_OFFSET_IB_BYTE3 0xea4 +#define EMC_TRAINING_RW_OFFSET_IB_MISC 0xea8 +#define EMC_TRAINING_RW_OFFSET_OB_BYTE0 0xeac +#define EMC_TRAINING_RW_OFFSET_OB_BYTE1 0xeb0 +#define EMC_TRAINING_RW_OFFSET_OB_BYTE2 0xeb4 +#define EMC_TRAINING_RW_OFFSET_OB_BYTE3 0xeb8 +#define EMC_TRAINING_RW_OFFSET_OB_MISC 0xebc +#define EMC_TRAINING_OPT_CA_VREF 0xec0 +#define EMC_TRAINING_OPT_DQ_OB_VREF 0xec4 +#define EMC_TRAINING_OPT_DQ_IB_VREF_RANK0 0xec8 +#define EMC_TRAINING_OPT_DQ_IB_VREF_RANK1 0xecc +#define EMC_TRAINING_QUSE_VREF_CTRL 0xed0 +#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 0xed4 +#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 0xed8 +#define EMC_TRAINING_DRAMC_TIMING 0xedc +#define EMC_PMACRO_QUSE_DDLL_RANK0_0 0x600 +#define EMC_PMACRO_QUSE_DDLL_RANK0_1 0x604 +#define EMC_PMACRO_QUSE_DDLL_RANK0_2 0x608 +#define EMC_PMACRO_QUSE_DDLL_RANK0_3 0x60c +#define EMC_PMACRO_QUSE_DDLL_RANK0_4 0x610 +#define EMC_PMACRO_QUSE_DDLL_RANK0_5 0x614 +#define EMC_PMACRO_QUSE_DDLL_RANK1_0 0x620 +#define EMC_PMACRO_QUSE_DDLL_RANK1_1 0x624 +#define EMC_PMACRO_QUSE_DDLL_RANK1_2 0x628 +#define EMC_PMACRO_QUSE_DDLL_RANK1_3 0x62c +#define EMC_PMACRO_QUSE_DDLL_RANK1_4 0x630 +#define EMC_PMACRO_QUSE_DDLL_RANK1_5 0x634 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 0x640 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_SHIFT \ + 16 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_MASK \ + 0x3ff << \ + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_SHIFT +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_SHIFT \ + 0 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_MASK \ + 0x3ff << \ + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_SHIFT + +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 0x644 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_SHIFT \ + 16 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_MASK \ + 0x3ff << \ + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_SHIFT +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_SHIFT \ + 0 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_MASK \ + 0x3ff << \ + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_SHIFT + +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 0x648 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_SHIFT \ + 16 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_MASK \ + 0x3ff << \ + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_SHIFT +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_SHIFT \ + 0 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_MASK \ + 0x3ff << \ + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_SHIFT + +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 0x64c +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_SHIFT \ + 16 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_MASK \ + 0x3ff << \ + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_SHIFT +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_SHIFT \ + 0 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_MASK \ + 0x3ff << \ + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_SHIFT + +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 0x650 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 0x654 + +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 0x660 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_SHIFT \ + 16 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_MASK \ + 0x3ff << \ + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_SHIFT +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_SHIFT \ + 0 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_MASK \ + 0x3ff << \ + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_SHIFT + +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 0x664 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_SHIFT \ + 16 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_MASK \ + 0x3ff << \ + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_SHIFT +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_SHIFT \ + 0 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_MASK \ + 0x3ff << \ + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_SHIFT + +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 0x668 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_SHIFT \ + 16 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_MASK \ + 0x3ff << \ + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_SHIFT +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_SHIFT \ + 0 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_MASK \ + 0x3ff << \ + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_SHIFT + +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 0x66c +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_SHIFT \ + 16 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_MASK \ + 0x3ff << \ + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_SHIFT +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_SHIFT \ + 0 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_MASK \ + 0x3ff << \ + EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_SHIFT + +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4 0x670 +#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5 0x674 +#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0 0x680 +#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1 0x684 +#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2 0x688 +#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3 0x68c +#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4 0x690 +#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5 0x694 +#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0 0x6a0 +#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1 0x6a4 +#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2 0x6a8 +#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3 0x6ac +#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4 0x6b0 +#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5 0x6b4 +#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0 0x6c0 +#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1 0x6c4 +#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2 0x6c8 +#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3 0x6cc +#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4 0x6d0 +#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5 0x6d4 +#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0 0x6e0 +#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1 0x6e4 +#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2 0x6e8 +#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3 0x6ec +#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4 0x6f0 +#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5 0x6f4 +#define EMC_PMACRO_TX_PWRD_0 0x720 +#define EMC_PMACRO_TX_PWRD_1 0x724 +#define EMC_PMACRO_TX_PWRD_2 0x728 +#define EMC_PMACRO_TX_PWRD_3 0x72c +#define EMC_PMACRO_TX_PWRD_4 0x730 +#define EMC_PMACRO_TX_PWRD_5 0x734 +#define EMC_PMACRO_TX_SEL_CLK_SRC_0 0x740 +#define EMC_PMACRO_TX_SEL_CLK_SRC_1 0x744 +#define EMC_PMACRO_TX_SEL_CLK_SRC_3 0x74c +#define EMC_PMACRO_TX_SEL_CLK_SRC_2 0x748 +#define EMC_PMACRO_TX_SEL_CLK_SRC_4 0x750 +#define EMC_PMACRO_TX_SEL_CLK_SRC_5 0x754 +#define EMC_PMACRO_DDLL_BYPASS 0x760 +#define EMC_PMACRO_DDLL_PWRD_0 0x770 +#define EMC_PMACRO_DDLL_PWRD_1 0x774 +#define EMC_PMACRO_DDLL_PWRD_2 0x778 +#define EMC_PMACRO_CMD_CTRL_0 0x780 +#define EMC_PMACRO_CMD_CTRL_1 0x784 +#define EMC_PMACRO_CMD_CTRL_2 0x788 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0x800 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0x804 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0x808 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 0x80c +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0x810 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0x814 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0x818 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 0x81c +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0x820 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0x824 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0x828 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 0x82c +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0x830 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0x834 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0x838 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 0x83c +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0x840 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0x844 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0x848 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 0x84c +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0x850 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0x854 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0x858 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 0x85c +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0x860 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0x864 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0x868 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 0x86c +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0x870 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0x874 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0x878 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 0x87c +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 0x880 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 0x884 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 0x888 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3 0x88c +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 0x890 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 0x894 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 0x898 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3 0x89c +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 0x8a0 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 0x8a4 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 0x8a8 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3 0x8ac +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 0x8b0 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 0x8b4 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 0x8b8 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3 0x8bc +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0x900 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0x904 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0x908 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 0x90c +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0x910 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0x914 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0x918 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 0x91c +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0x920 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0x924 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0x928 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 0x92c +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0x930 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0x934 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0x938 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 0x93c +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0x940 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0x944 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0x948 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 0x94c +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0x950 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0x954 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0x958 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 0x95c +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0x960 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0x964 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0x968 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 0x96c +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0x970 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0x974 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0x978 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 0x97c +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0 0x980 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1 0x984 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2 0x988 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3 0x98c +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0 0x990 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1 0x994 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2 0x998 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3 0x99c +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0 0x9a0 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1 0x9a4 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2 0x9a8 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3 0x9ac +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0 0x9b0 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1 0x9b4 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2 0x9b8 +#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3 0x9bc +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0xa00 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0xa04 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0xa08 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0xa10 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0xa14 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0xa18 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0xa20 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0xa24 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0xa28 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0xa30 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0xa34 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0xa38 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0xa40 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0xa44 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0xa48 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0xa50 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0xa54 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0xa58 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0xa60 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0xa64 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0xa68 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0xa70 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0xa74 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0xa78 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0 0xa80 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1 0xa84 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2 0xa88 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0 0xa90 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1 0xa94 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2 0xa98 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0 0xaa0 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1 0xaa4 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2 0xaa8 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0 0xab0 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1 0xab4 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2 0xab8 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0xb00 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0xb04 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0xb08 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0xb10 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0xb14 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0xb18 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0xb20 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0xb24 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0xb28 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0xb30 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0xb34 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0xb38 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0xb40 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0xb44 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0xb48 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0xb50 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0xb54 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0xb58 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0xb60 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0xb64 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0xb68 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0xb70 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0xb74 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0xb78 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0 0xb80 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1 0xb84 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2 0xb88 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0 0xb90 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1 0xb94 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2 0xb98 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0 0xba0 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1 0xba4 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2 0xba8 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0 0xbb0 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1 0xbb4 +#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2 0xbb8 +#define EMC_PMACRO_IB_VREF_DQ_0 0xbe0 +#define EMC_PMACRO_IB_VREF_DQ_1 0xbe4 +#define EMC_PMACRO_IB_VREF_DQ_2 0xbe8 +#define EMC_PMACRO_IB_VREF_DQS_0 0xbf0 +#define EMC_PMACRO_IB_VREF_DQS_1 0xbf4 +#define EMC_PMACRO_IB_VREF_DQS_2 0xbf8 +#define EMC_PMACRO_IB_RXRT 0xcf4 +#define EMC_PMACRO_DDLL_LONG_CMD_0 0xc00 +#define EMC_PMACRO_DDLL_LONG_CMD_1 0xc04 +#define EMC_PMACRO_DDLL_LONG_CMD_2 0xc08 +#define EMC_PMACRO_DDLL_LONG_CMD_3 0xc0c +#define EMC_PMACRO_DDLL_LONG_CMD_4 0xc10 +#define EMC_PMACRO_DDLL_LONG_CMD_5 0xc14 +#define EMC_PMACRO_DDLL_SHORT_CMD_0 0xc20 +#define EMC_PMACRO_DDLL_SHORT_CMD_1 0xc24 +#define EMC_PMACRO_DDLL_SHORT_CMD_2 0xc28 +#define EMC_PMACRO_CFG_PM_GLOBAL_0 0xc30 +#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE0 (1 << 16) +#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE1 (1 << 17) +#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE2 (1 << 18) +#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE3 (1 << 19) +#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE4 (1 << 20) +#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE5 (1 << 21) +#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE6 (1 << 22) +#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE7 (1 << 23) +#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD0 (1 << 24) +#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD1 (1 << 25) +#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD2 (1 << 26) +#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD3 (1 << 27) + +#define EMC_PMACRO_VTTGEN_CTRL_0 0xc34 +#define EMC_PMACRO_VTTGEN_CTRL_1 0xc38 +#define EMC_PMACRO_VTTGEN_CTRL_2 0xcf0 +#define EMC_PMACRO_BG_BIAS_CTRL_0 0xc3c +#define EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD (1 << 0) +#define EMC_PMACRO_BG_BIAS_CTRL_0_BG_MODE (1 << 1) +#define EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD (1 << 2) + +#define EMC_PMACRO_PAD_CFG_CTRL 0xc40 +#define EMC_PMACRO_CMD_PAD_RX_CTRL 0xc50 +#define EMC_PMACRO_DATA_PAD_RX_CTRL 0xc54 +#define EMC_PMACRO_CMD_RX_TERM_MODE 0xc58 +#define EMC_PMACRO_DATA_RX_TERM_MODE 0xc5c +#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSN_RX_TERM_MODE_SHIFT 8 +#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSN_RX_TERM_MODE_MASK (0x3 << \ + EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSN_RX_TERM_MODE_SHIFT) +#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSP_RX_TERM_MODE_SHIFT 4 +#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSP_RX_TERM_MODE_MASK (0x3 << \ + EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSP_RX_TERM_MODE_SHIFT) +#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQ_RX_TERM_MODE_SHIFT 0 +#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQ_RX_TERM_MODE_MASK (0x3 << \ + EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQ_RX_TERM_MODE_SHIFT) + +#define RX_TERM_MODE \ + ~(EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSN_RX_TERM_MODE_MASK | \ + EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSP_RX_TERM_MODE_MASK | \ + EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQ_RX_TERM_MODE_MASK) + +#define EMC_PMACRO_CMD_PAD_TX_CTRL 0xc60 +#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_E_DCC (1 << 1) +#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSP_TX_E_DCC (1 << 9) +#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSN_TX_E_DCC (1 << 16) +#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_CMD_TX_E_DCC (1 << 24) +#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_DRVFORCEON (1 << 26) + +#define EMC_PMACRO_DATA_PAD_TX_CTRL 0xc64 +#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_E_IVREF (1 << 0) +#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_TX_E_DCC (1 << 1) +#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF (1 << 8) +#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSP_TX_E_DCC (1 << 9) +#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC (1 << 16) +#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC (1 << 24) + +#define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xc68 +#define EMC_PMACRO_BRICK_MAPPING_0 0xc80 +#define EMC_PMACRO_BRICK_MAPPING_1 0xc84 +#define EMC_PMACRO_BRICK_MAPPING_2 0xc88 +#define EMC_PMACRO_DDLLCAL_CAL 0xce0 +#define EMC_PMACRO_DDLL_OFFSET 0xce4 +#define EMC_PMACRO_DDLL_PERIODIC_OFFSET 0xce8 +#define EMC_PMACRO_BRICK_CTRL_RFU1 0x330 +#define EMC_PMACRO_BRICK_CTRL_RFU2 0x334 +#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD 0x318 +#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD 0x31c +#define EMC_PMACRO_TRAINING_CTRL_0 0xcf8 +#define EMC_PMACRO_TRAINING_CTRL_0_CH0_TRAINING_E_WRPTR (1 << 3) + +#define EMC_PMACRO_TRAINING_CTRL_1 0xcfc +#define EMC_PMACRO_TRAINING_CTRL_1_CH1_TRAINING_E_WRPTR (1 << 3) + +#define EMC_PMC_SCRATCH1 0x440 +#define EMC_PMC_SCRATCH2 0x444 +#define EMC_PMC_SCRATCH3 0x448 + +#define EMC_PMACRO_PERBIT_FGCG_CTRL_0 0xd40 +#define EMC_PMACRO_PERBIT_FGCG_CTRL_1 0xd44 +#define EMC_PMACRO_PERBIT_FGCG_CTRL_2 0xd48 +#define EMC_PMACRO_PERBIT_FGCG_CTRL_3 0xd4c +#define EMC_PMACRO_PERBIT_FGCG_CTRL_4 0xd50 +#define EMC_PMACRO_PERBIT_FGCG_CTRL_5 0xd54 +#define EMC_PMACRO_PERBIT_RFU_CTRL_0 0xd60 +#define EMC_PMACRO_PERBIT_RFU_CTRL_1 0xd64 +#define EMC_PMACRO_PERBIT_RFU_CTRL_2 0xd68 +#define EMC_PMACRO_PERBIT_RFU_CTRL_3 0xd6c +#define EMC_PMACRO_PERBIT_RFU_CTRL_4 0xd70 +#define EMC_PMACRO_PERBIT_RFU_CTRL_5 0xd74 +#define EMC_PMACRO_PERBIT_RFU1_CTRL_0 0xd80 +#define EMC_PMACRO_PERBIT_RFU1_CTRL_1 0xd84 +#define EMC_PMACRO_PERBIT_RFU1_CTRL_2 0xd88 +#define EMC_PMACRO_PERBIT_RFU1_CTRL_3 0xd8c +#define EMC_PMACRO_PERBIT_RFU1_CTRL_4 0xd90 +#define EMC_PMACRO_PERBIT_RFU1_CTRL_5 0xd94 + +#define EMC_PMACRO_PMU_OUT_EOFF1_0 0xda0 +#define EMC_PMACRO_PMU_OUT_EOFF1_1 0xda4 +#define EMC_PMACRO_PMU_OUT_EOFF1_2 0xda8 +#define EMC_PMACRO_PMU_OUT_EOFF1_3 0xdac +#define EMC_PMACRO_PMU_OUT_EOFF1_4 0xdb0 +#define EMC_PMACRO_PMU_OUT_EOFF1_5 0xdb4 + +#define EMC_PMACRO_COMP_PMU_OUT 0xdc0 +#define EMC_PMACRO_DATA_PI_CTRL 0x110 +#define EMC_PMACRO_CMD_PI_CTRL 0x114 + +#define EMC_AUTO_CAL_CONFIG9 0x42c + +#define EMC_TRTM 0xbc +#define EMC_TWTM 0xf8 +#define EMC_TRATM 0xfc +#define EMC_TWATM 0x108 +#define EMC_TR2REF 0x10c + +#define EMC_PMACRO_DSR_VTTGEN_CTRL_0 0xc6c + +#endif diff --git a/sept/sept-secondary/src/fuse.c b/sept/sept-secondary/src/fuse.c index ef42ce431..5acb3aec0 100644 --- a/sept/sept-secondary/src/fuse.c +++ b/sept/sept-secondary/src/fuse.c @@ -187,7 +187,7 @@ uint32_t fuse_get_reserved_odm(uint32_t index) { /* Get the DramId. */ uint32_t fuse_get_dram_id(void) { - return ((fuse_get_reserved_odm(4) >> 3) & 0x7); + return ((fuse_get_reserved_odm(4) >> 3) & 0x1F); } /* Derive the DeviceId. */ diff --git a/sept/sept-secondary/src/hwinit.c b/sept/sept-secondary/src/hwinit.c index adc701ce4..dc343e70e 100644 --- a/sept/sept-secondary/src/hwinit.c +++ b/sept/sept-secondary/src/hwinit.c @@ -34,8 +34,7 @@ #include "timers.h" #include "uart.h" -void config_oscillators() -{ +static void config_oscillators(void) { volatile tegra_car_t *car = car_get_regs(); volatile tegra_pmc_t *pmc = pmc_get_regs(); @@ -57,8 +56,7 @@ void config_oscillators() car->clk_sys_rate = 2; } -void config_gpios() -{ +static void config_gpios_erista(void) { volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); pinmux->uart2_tx = 0; @@ -79,15 +77,50 @@ void config_gpios() i2c_config(I2C_5); uart_config(UART_A); - /* Configure volume up/down as inputs. */ + /* Configure volume up/down buttons as inputs. */ gpio_configure_mode(GPIO_BUTTON_VOL_UP, GPIO_MODE_GPIO); gpio_configure_mode(GPIO_BUTTON_VOL_DOWN, GPIO_MODE_GPIO); gpio_configure_direction(GPIO_BUTTON_VOL_UP, GPIO_DIRECTION_INPUT); gpio_configure_direction(GPIO_BUTTON_VOL_DOWN, GPIO_DIRECTION_INPUT); } -void config_pmc_scratch() -{ +static void config_gpios_mariko(void) { + volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); + uint32_t hardware_type = fuse_get_hardware_type(); + + /* Only for HardwareType_Iowa and HardwareType_Five. */ + if ((hardware_type == 3) || (hardware_type == 5)) { + pinmux->uart2_tx = 0; + pinmux->uart3_tx = 0; + gpio_configure_mode(TEGRA_GPIO(G, 0), GPIO_MODE_GPIO); + gpio_configure_mode(TEGRA_GPIO(D, 1), GPIO_MODE_GPIO); + gpio_configure_direction(TEGRA_GPIO(G, 0), GPIO_DIRECTION_INPUT); + gpio_configure_direction(TEGRA_GPIO(D, 1), GPIO_DIRECTION_INPUT); + } + + pinmux->pe6 = PINMUX_INPUT; + pinmux->ph6 = PINMUX_INPUT; + gpio_configure_mode(TEGRA_GPIO(E, 6), GPIO_MODE_GPIO); + gpio_configure_mode(TEGRA_GPIO(H, 6), GPIO_MODE_GPIO); + gpio_configure_direction(TEGRA_GPIO(E, 6), GPIO_DIRECTION_INPUT); + gpio_configure_direction(TEGRA_GPIO(H, 6), GPIO_DIRECTION_INPUT); + + i2c_config(I2C_1); + i2c_config(I2C_5); + uart_config(UART_A); + + /* Configure volume up/down buttons as inputs. */ + gpio_configure_mode(GPIO_BUTTON_VOL_UP, GPIO_MODE_GPIO); + gpio_configure_mode(GPIO_BUTTON_VOL_DOWN, GPIO_MODE_GPIO); + gpio_configure_direction(GPIO_BUTTON_VOL_UP, GPIO_DIRECTION_INPUT); + gpio_configure_direction(GPIO_BUTTON_VOL_DOWN, GPIO_DIRECTION_INPUT); + + /* Configure home button as input. */ + gpio_configure_mode(TEGRA_GPIO(Y, 1), GPIO_MODE_GPIO); + gpio_configure_direction(TEGRA_GPIO(Y, 1), GPIO_DIRECTION_INPUT); +} + +static void config_pmc_scratch(void) { volatile tegra_pmc_t *pmc = pmc_get_regs(); pmc->scratch20 &= 0xFFF3FFFF; @@ -95,8 +128,7 @@ void config_pmc_scratch() pmc->secure_scratch21 |= 0x10; } -void mbist_workaround() -{ +static void mbist_workaround(void) { volatile tegra_car_t *car = car_get_regs(); car->clk_source_sor1 = ((car->clk_source_sor1 | 0x8000) & 0xFFFFBFFF); @@ -151,8 +183,7 @@ void mbist_workaround() car->clk_source_nvenc = ((car->clk_source_nvenc & 0x1FFFFFFF) | 0x80000000); } -void config_se_brom() -{ +static void config_se_brom(void) { volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); volatile tegra_se_t *se = se_get_regs(); volatile tegra_pmc_t *pmc = pmc_get_regs(); @@ -178,8 +209,7 @@ void config_se_brom() pmc->reset_status = 0; } -void nx_hwinit() -{ +void nx_hwinit_erista(bool enable_log) { volatile tegra_pmc_t *pmc = pmc_get_regs(); volatile tegra_car_t *car = car_get_regs(); @@ -210,13 +240,13 @@ void nx_hwinit() /* Configure GPIOs. */ /* NOTE: [3.0.0+] Part of the GPIO configuration is skipped if the unit is SDEV. */ /* NOTE: [6.0.0+] The GPIO configuration's order was changed a bit. */ - config_gpios(); + config_gpios_erista(); - /* Uncomment for UART debugging. */ - /* - clkrst_reboot(CARDEVICE_UARTC); - uart_init(UART_C, 115200); - */ + /* UART debugging. */ + if (enable_log) { + clkrst_reboot(CARDEVICE_UARTA); + uart_init(UART_A, 115200); + } /* Reboot CL-DVFS. */ clkrst_reboot(CARDEVICE_CL_DVFS); @@ -290,8 +320,84 @@ void nx_hwinit() /* mc_config_carveout(); */ /* Initialize SDRAM. */ - sdram_init(); + sdram_init_erista(); - /* Save SDRAM LP0 parameters. */ - sdram_lp0_save_params(sdram_get_params()); + /* Save SDRAM parameters to scratch. */ + sdram_save_params_erista(sdram_get_params_erista(fuse_get_dram_id())); +} + +void nx_hwinit_mariko(bool enable_log) { + volatile tegra_car_t *car = car_get_regs(); + + /* Enable SE clock. */ + clkrst_reboot(CARDEVICE_SE); + + /* Initialize the fuse driver. */ + fuse_init(); + + /* Initialize the memory controller. */ + mc_enable(); + + /* Configure oscillators. */ + config_oscillators(); + + /* Disable pinmux tristate input clamping. */ + APB_MISC_PP_PINMUX_GLOBAL_0 = 0; + + /* Configure GPIOs. */ + config_gpios_mariko(); + + /* UART debugging. */ + if (enable_log) { + clkrst_reboot(CARDEVICE_UARTA); + uart_init(UART_A, 115200); + } + + /* Enable CL-DVFS clock. */ + clkrst_reboot(CARDEVICE_CL_DVFS); + + /* Enable I2C1 clock. */ + clkrst_reboot(CARDEVICE_I2C1); + + /* Enable I2C5 clock. */ + clkrst_reboot(CARDEVICE_I2C5); + + /* Enable TZRAM clock. */ + clkrst_reboot(CARDEVICE_TZRAM); + + /* Initialize I2C5. */ + i2c_init(I2C_5); + + /* Configure the PMIC. */ + uint8_t val = 0x40; + i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGBBC, &val, 1); + val = 0x78; + i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &val, 1); + + /* Configure SD0 voltage. */ + val = 0x24; + i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD0, &val, 1); + + /* Enable LDO8 in HardwareType_Hoag only. */ + if (fuse_get_hardware_type() == 2) { + val = 0xE8; + i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO8_CFG, &val, 1); + } + + /* Initialize I2C1. */ + i2c_init(I2C_1); + + /* Set super clock burst policy. */ + car->sclk_brst_pol = ((car->sclk_brst_pol & 0xFFFF8888) | 0x3333); + + /* Mariko only PMC configuration. */ + MAKE_PMC_REG(0xBE8) &= 0xFFFFFFFE; + MAKE_PMC_REG(0xBF0) = 0x3; + MAKE_PMC_REG(0xBEC) = 0x3; + + /* Initialize SDRAM. */ + sdram_init_mariko(); + + /* Save SDRAM parameters to scratch. */ + sdram_save_params_mariko(sdram_get_params_mariko(fuse_get_dram_id())); } \ No newline at end of file diff --git a/sept/sept-secondary/src/hwinit.h b/sept/sept-secondary/src/hwinit.h index a165346e8..7388813cd 100644 --- a/sept/sept-secondary/src/hwinit.h +++ b/sept/sept-secondary/src/hwinit.h @@ -19,9 +19,12 @@ #ifndef FUSEE_HWINIT_H_ #define FUSEE_HWINIT_H_ +#include + #define I2S_BASE 0x702D1000 #define MAKE_I2S_REG(n) MAKE_REG32(I2S_BASE + n) -void nx_hwinit(); +void nx_hwinit_erista(bool enable_log); +void nx_hwinit_mariko(bool enable_log); #endif diff --git a/sept/sept-secondary/src/main.c b/sept/sept-secondary/src/main.c index 83cf6ddf7..80390d560 100644 --- a/sept/sept-secondary/src/main.c +++ b/sept/sept-secondary/src/main.c @@ -108,7 +108,7 @@ static void setup_env(void) { g_framebuffer = (void *)0xC0000000; /* Initialize hardware. */ - nx_hwinit(); + nx_hwinit_erista(false); /* Zero-fill the framebuffer and register it as printk provider. */ video_init(g_framebuffer); diff --git a/sept/sept-secondary/src/mc.h b/sept/sept-secondary/src/mc.h index 63a263a59..c414f907a 100644 --- a/sept/sept-secondary/src/mc.h +++ b/sept/sept-secondary/src/mc.h @@ -497,6 +497,7 @@ #define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08 #define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0 #define MC_DA_CONFIG0 0x9dc +#define MC_UNTRANSLATED_REGION_CHECK 0x948 /* Memory Controller clients */ #define CLIENT_ACCESS_NUM_CLIENTS 32 diff --git a/sept/sept-secondary/src/sdram.c b/sept/sept-secondary/src/sdram.c index 55a2f6af8..6198c2ceb 100644 --- a/sept/sept-secondary/src/sdram.c +++ b/sept/sept-secondary/src/sdram.c @@ -23,50 +23,40 @@ #include "sysreg.h" #include "fuse.h" #include "max77620.h" -#include "sdram_param_t210.h" +#include "sdram_params.h" #include "car.h" -#define CONFIG_SDRAM_COMPRESS_CFG +#define CONFIG_SDRAM_COMPRESS -#ifdef CONFIG_SDRAM_COMPRESS_CFG +#ifdef CONFIG_SDRAM_COMPRESS #include "../../../fusee/common/lz.h" #include "sdram_lz.inl" #else #include "sdram.inl" #endif -static uint32_t _get_sdram_id() -{ - return ((fuse_get_reserved_odm(4) & 0x38) >> 3); -} - -static void _sdram_config(const sdram_params_t *params) -{ +static void sdram_config_erista(const sdram_params_erista_t *params) { volatile tegra_car_t *car = car_get_regs(); volatile tegra_pmc_t *pmc = pmc_get_regs(); - pmc->io_dpd3_req = (((4 * params->emc_pmc_scratch1 >> 2) + 0x80000000) ^ 0xFFFF) & 0xC000FFFF; - udelay(params->pmc_io_dpd3_req_wait); - - uint32_t req = (4 * params->emc_pmc_scratch2 >> 2) + 0x80000000; + pmc->io_dpd3_req = (((4 * params->EmcPmcScratch1 >> 2) + 0x80000000) ^ 0xFFFF) & 0xC000FFFF; + udelay(params->PmcIoDpd3ReqWait); + uint32_t req = (4 * params->EmcPmcScratch2 >> 2) + 0x80000000; pmc->io_dpd4_req = (req >> 16 << 16) ^ 0x3FFF0000; - - udelay(params->pmc_io_dpd4_req_wait); + udelay(params->PmcIoDpd4ReqWait); pmc->io_dpd4_req = (req ^ 0xFFFF) & 0xC000FFFF; - udelay(params->pmc_io_dpd4_req_wait); - + udelay(params->PmcIoDpd4ReqWait); pmc->weak_bias = 0; udelay(1); - car->pllm_misc1 = params->pllm_setup_control; + car->pllm_misc1 = params->PllMSetupControl; car->pllm_misc2 = 0; - car->pllm_base = ((params->pllm_feedback_divider << 8) | params->pllm_input_divider | 0x40000000 | ((params->pllm_post_divider & 0xFFFF) << 20)); + car->pllm_base = ((params->PllMFeedbackDivider << 8) | params->PllMInputDivider | 0x40000000 | ((params->PllMPostDivider & 0xFFFF) << 20)); bool timeout = false; uint32_t wait_end = get_time_us() + 300; - while (!(car->pllm_base & 0x8000000) && !timeout) - { + while (!(car->pllm_base & 0x8000000) && !timeout) { if (get_time_us() >= wait_end) timeout = true; } @@ -75,504 +65,2159 @@ static void _sdram_config(const sdram_params_t *params) udelay(10); } - car->clk_source_emc = (((params->mc_emem_arb_misc0 >> 11) & 0x10000) | (params->emc_clock_source & 0xFFFEFFFF)); + car->clk_source_emc = (((params->McEmemArbMisc0 >> 11) & 0x10000) | (params->EmcClockSource & 0xFFFEFFFF)); - if (params->emc_clock_source_dll) - car->clk_source_emc_dll = params->emc_clock_source_dll; - - if (params->clear_clock2_mc1) + if (params->EmcClockSourceDll) { + car->clk_source_emc_dll = params->EmcClockSourceDll; + } + if (params->ClearClk2Mc1) { car->clk_enb_w_clr = 0x40000000; + } car->clk_enb_h_set = 0x2000001; car->clk_enb_x_set = 0x4000; car->rst_dev_h_clr = 0x2000001; - MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_0) = params->emc_pmacro_vttgen_ctrl0; - MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_1) = params->emc_pmacro_vttgen_ctrl1; - MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_2) = params->emc_pmacro_vttgen_ctrl2; + MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_0) = params->EmcPmacroVttgenCtrl0; + MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_1) = params->EmcPmacroVttgenCtrl1; + MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_2) = params->EmcPmacroVttgenCtrl2; MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; udelay(1); - MAKE_EMC_REG(EMC_DBG) = (params->emc_dbg_write_mux << 1) | params->emc_dbg; + MAKE_EMC_REG(EMC_DBG) = (params->EmcDbgWriteMux << 1) | params->EmcDbg; - if (params->emc_bct_spare2) - *(volatile uint32_t *)params->emc_bct_spare2 = params->emc_bct_spare3; + if (params->EmcBctSpare2) { + *(volatile uint32_t *)params->EmcBctSpare2 = params->EmcBctSpare3; + } - MAKE_EMC_REG(EMC_FBIO_CFG7) = params->emc_fbio_cfg7; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_0) = params->emc_cmd_mapping_cmd0_0; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_1) = params->emc_cmd_mapping_cmd0_1; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_2) = params->emc_cmd_mapping_cmd0_2; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_0) = params->emc_cmd_mapping_cmd1_0; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_1) = params->emc_cmd_mapping_cmd1_1; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_2) = params->emc_cmd_mapping_cmd1_2; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_0) = params->emc_cmd_mapping_cmd2_0; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_1) = params->emc_cmd_mapping_cmd2_1; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_2) = params->emc_cmd_mapping_cmd2_2; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_0) = params->emc_cmd_mapping_cmd3_0; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_1) = params->emc_cmd_mapping_cmd3_1; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_2) = params->emc_cmd_mapping_cmd3_2; - MAKE_EMC_REG(EMC_CMD_MAPPING_BYTE) = params->emc_cmd_mapping_byte; - MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_0) = params->emc_pmacro_brick_mapping0; - MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_1) = params->emc_pmacro_brick_mapping1; - MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_2) = params->emc_pmacro_brick_mapping2; - MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = ((params->emc_pmacro_brick_ctrl_rfu1 & 0x1120112) | 0x1EED1EED); - MAKE_EMC_REG(EMC_CONFIG_SAMPLE_DELAY) = params->emc_config_sample_delay; - MAKE_EMC_REG(EMC_FBIO_CFG8) = params->emc_fbio_cfg8; - MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE0) = params->emc_swizzle_rank0_byte0; - MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE1) = params->emc_swizzle_rank0_byte1; - MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE2) = params->emc_swizzle_rank0_byte2; - MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE3) = params->emc_swizzle_rank0_byte3; - MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE0) = params->emc_swizzle_rank1_byte0; - MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE1) = params->emc_swizzle_rank1_byte1; - MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE2) = params->emc_swizzle_rank1_byte2; - MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE3) = params->emc_swizzle_rank1_byte3; + MAKE_EMC_REG(EMC_FBIO_CFG7) = params->EmcFbioCfg7; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_0) = params->EmcCmdMappingCmd0_0; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_1) = params->EmcCmdMappingCmd0_1; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_2) = params->EmcCmdMappingCmd0_2; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_0) = params->EmcCmdMappingCmd1_0; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_1) = params->EmcCmdMappingCmd1_1; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_2) = params->EmcCmdMappingCmd1_2; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_0) = params->EmcCmdMappingCmd2_0; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_1) = params->EmcCmdMappingCmd2_1; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_2) = params->EmcCmdMappingCmd2_2; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_0) = params->EmcCmdMappingCmd3_0; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_1) = params->EmcCmdMappingCmd3_1; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_2) = params->EmcCmdMappingCmd3_2; + MAKE_EMC_REG(EMC_CMD_MAPPING_BYTE) = params->EmcCmdMappingByte; + MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_0) = params->EmcPmacroBrickMapping0; + MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_1) = params->EmcPmacroBrickMapping1; + MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_2) = params->EmcPmacroBrickMapping2; + MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = ((params->EmcPmacroBrickCtrlRfu1 & 0x1120112) | 0x1EED1EED); + MAKE_EMC_REG(EMC_CONFIG_SAMPLE_DELAY) = params->EmcConfigSampleDelay; + MAKE_EMC_REG(EMC_FBIO_CFG8) = params->EmcFbioCfg8; + MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE0) = params->EmcSwizzleRank0Byte0; + MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE1) = params->EmcSwizzleRank0Byte1; + MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE2) = params->EmcSwizzleRank0Byte2; + MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE3) = params->EmcSwizzleRank0Byte3; + MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE0) = params->EmcSwizzleRank1Byte0; + MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE1) = params->EmcSwizzleRank1Byte1; + MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE2) = params->EmcSwizzleRank1Byte2; + MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE3) = params->EmcSwizzleRank1Byte3; - if (params->emc_bct_spare6) - *(volatile uint32_t *)params->emc_bct_spare6 = params->emc_bct_spare7; + if (params->EmcBctSpare6) { + *(volatile uint32_t *)params->EmcBctSpare6 = params->EmcBctSpare7; + } - MAKE_EMC_REG(EMC_XM2COMPPADCTRL) = params->emc_xm2_comp_pad_ctrl; - MAKE_EMC_REG(EMC_XM2COMPPADCTRL2) = params->emc_xm2_comp_pad_ctrl2; - MAKE_EMC_REG(EMC_XM2COMPPADCTRL3) = params->emc_xm2_comp_pad_ctrl3; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG2) = params->emc_auto_cal_config2; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG3) = params->emc_auto_cal_config3; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG4) = params->emc_auto_cal_config4; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG5) = params->emc_auto_cal_config5; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG6) = params->emc_auto_cal_config6; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG7) = params->emc_auto_cal_config7; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG8) = params->emc_auto_cal_config8; - MAKE_EMC_REG(EMC_PMACRO_RX_TERM) = params->emc_pmacro_rx_term; - MAKE_EMC_REG(EMC_PMACRO_DQ_TX_DRV) = params->emc_pmacro_dq_tx_drive; - MAKE_EMC_REG(EMC_PMACRO_CA_TX_DRV) = params->emc_pmacro_ca_tx_drive; - MAKE_EMC_REG(EMC_PMACRO_CMD_TX_DRV) = params->emc_pmacro_cmd_tx_drive; - MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_COMMON) = params->emc_pmacro_auto_cal_common; - MAKE_EMC_REG(EMC_AUTO_CAL_CHANNEL) = params->emc_auto_cal_channel; - MAKE_EMC_REG(EMC_PMACRO_ZCTRL) = params->emc_pmacro_zcrtl; - MAKE_EMC_REG(EMC_DLL_CFG_0) = params->emc_dll_cfg0; - MAKE_EMC_REG(EMC_DLL_CFG_1) = params->emc_dll_cfg1; - MAKE_EMC_REG(EMC_CFG_DIG_DLL_1) = params->emc_cfg_dig_dll_1; - MAKE_EMC_REG(EMC_DATA_BRLSHFT_0) = params->emc_data_brlshft0; - MAKE_EMC_REG(EMC_DATA_BRLSHFT_1) = params->emc_data_brlshft1; - MAKE_EMC_REG(EMC_DQS_BRLSHFT_0) = params->emc_dqs_brlshft0; - MAKE_EMC_REG(EMC_DQS_BRLSHFT_1) = params->emc_dqs_brlshft1; - MAKE_EMC_REG(EMC_CMD_BRLSHFT_0) = params->emc_cmd_brlshft0; - MAKE_EMC_REG(EMC_CMD_BRLSHFT_1) = params->emc_cmd_brlshft1; - MAKE_EMC_REG(EMC_CMD_BRLSHFT_2) = params->emc_cmd_brlshft2; - MAKE_EMC_REG(EMC_CMD_BRLSHFT_3) = params->emc_cmd_brlshft3; - MAKE_EMC_REG(EMC_QUSE_BRLSHFT_0) = params->emc_quse_brlshft0; - MAKE_EMC_REG(EMC_QUSE_BRLSHFT_1) = params->emc_quse_brlshft1; - MAKE_EMC_REG(EMC_QUSE_BRLSHFT_2) = params->emc_quse_brlshft2; - MAKE_EMC_REG(EMC_QUSE_BRLSHFT_3) = params->emc_quse_brlshft3; - MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = ((params->emc_pmacro_brick_ctrl_rfu1 & 0x1BF01BF) | 0x1E401E40); - MAKE_EMC_REG(EMC_PMACRO_PAD_CFG_CTRL) = params->emc_pmacro_pad_cfg_ctrl; - MAKE_EMC_REG(EMC_PMACRO_CMD_BRICK_CTRL_FDPD) = params->emc_pmacro_cmd_brick_ctrl_fdpd; - MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU2) = (params->emc_pmacro_brick_ctrl_rfu2 & 0xFF7FFF7F); - MAKE_EMC_REG(EMC_PMACRO_DATA_BRICK_CTRL_FDPD) = params->emc_pmacro_data_brick_ctrl_fdpd; - MAKE_EMC_REG(EMC_PMACRO_BG_BIAS_CTRL_0) = params->emc_pmacro_bg_bias_ctrl0; - MAKE_EMC_REG(EMC_PMACRO_DATA_PAD_RX_CTRL) = params->emc_pmacro_data_pad_rx_ctrl; - MAKE_EMC_REG(EMC_PMACRO_CMD_PAD_RX_CTRL) = params->emc_pmacro_cmd_pad_rx_ctrl; - MAKE_EMC_REG(EMC_PMACRO_DATA_PAD_TX_CTRL) = params->emc_pmacro_data_pad_tx_ctrl; - MAKE_EMC_REG(EMC_PMACRO_DATA_RX_TERM_MODE) = params->emc_pmacro_data_rx_term_mode; - MAKE_EMC_REG(EMC_PMACRO_CMD_RX_TERM_MODE) = params->emc_pmacro_cmd_rx_term_mode; - MAKE_EMC_REG(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->emc_pmacro_cmd_pad_tx_ctrl; - MAKE_EMC_REG(EMC_CFG_3) = params->emc_cfg3; - MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_0) = params->emc_pmacro_tx_pwrd0; - MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_1) = params->emc_pmacro_tx_pwrd1; - MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_2) = params->emc_pmacro_tx_pwrd2; - MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_3) = params->emc_pmacro_tx_pwrd3; - MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_4) = params->emc_pmacro_tx_pwrd4; - MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_5) = params->emc_pmacro_tx_pwrd5; - MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_0) = params->emc_pmacro_tx_sel_clk_src0; - MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_1) = params->emc_pmacro_tx_sel_clk_src1; - MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_2) = params->emc_pmacro_tx_sel_clk_src2; - MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_3) = params->emc_pmacro_tx_sel_clk_src3; - MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_4) = params->emc_pmacro_tx_sel_clk_src4; - MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_5) = params->emc_pmacro_tx_sel_clk_src5; - MAKE_EMC_REG(EMC_PMACRO_DDLL_BYPASS) = params->emc_pmacro_ddll_bypass; - MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_0) = params->emc_pmacro_ddll_pwrd0; - MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_1) = params->emc_pmacro_ddll_pwrd1; - MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_2) = params->emc_pmacro_ddll_pwrd2; - MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_0) = params->emc_pmacro_cmd_ctrl0; - MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_1) = params->emc_pmacro_cmd_ctrl1; - MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_2) = params->emc_pmacro_cmd_ctrl2; - MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQ_0) = params->emc_pmacro_ib_vref_dq_0; - MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQ_1) = params->emc_pmacro_ib_vref_dq_1; - MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQS_0) = params->emc_pmacro_ib_vref_dqs_0; - MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQS_1) = params->emc_pmacro_ib_vref_dqs_1; - MAKE_EMC_REG(EMC_PMACRO_IB_RXRT) = params->emc_pmacro_ib_rxrt; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_0) = params->emc_pmacro_quse_ddll_rank0_0; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_1) = params->emc_pmacro_quse_ddll_rank0_1; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_2) = params->emc_pmacro_quse_ddll_rank0_2; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_3) = params->emc_pmacro_quse_ddll_rank0_3; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_4) = params->emc_pmacro_quse_ddll_rank0_4; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_5) = params->emc_pmacro_quse_ddll_rank0_5; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_0) = params->emc_pmacro_quse_ddll_rank1_0; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_1) = params->emc_pmacro_quse_ddll_rank1_1; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_2) = params->emc_pmacro_quse_ddll_rank1_2; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_3) = params->emc_pmacro_quse_ddll_rank1_3; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_4) = params->emc_pmacro_quse_ddll_rank1_4; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_5) = params->emc_pmacro_quse_ddll_rank1_5; - MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = params->emc_pmacro_brick_ctrl_rfu1; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0) = params->emc_pmacro_ob_ddll_long_dq_rank0_0; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1) = params->emc_pmacro_ob_ddll_long_dq_rank0_1; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2) = params->emc_pmacro_ob_ddll_long_dq_rank0_2; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3) = params->emc_pmacro_ob_ddll_long_dq_rank0_3; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4) = params->emc_pmacro_ob_ddll_long_dq_rank0_4; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5) = params->emc_pmacro_ob_ddll_long_dq_rank0_5; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0) = params->emc_pmacro_ob_ddll_long_dq_rank1_0; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1) = params->emc_pmacro_ob_ddll_long_dq_rank1_1; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2) = params->emc_pmacro_ob_ddll_long_dq_rank1_2; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3) = params->emc_pmacro_ob_ddll_long_dq_rank1_3; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4) = params->emc_pmacro_ob_ddll_long_dq_rank1_4; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5) = params->emc_pmacro_ob_ddll_long_dq_rank1_5; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0) = params->emc_pmacro_ob_ddll_long_dqs_rank0_0; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1) = params->emc_pmacro_ob_ddll_long_dqs_rank0_1; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2) = params->emc_pmacro_ob_ddll_long_dqs_rank0_2; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3) = params->emc_pmacro_ob_ddll_long_dqs_rank0_3; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4) = params->emc_pmacro_ob_ddll_long_dqs_rank0_4; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5) = params->emc_pmacro_ob_ddll_long_dqs_rank0_5; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0) = params->emc_pmacro_ob_ddll_long_dqs_rank1_0; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1) = params->emc_pmacro_ob_ddll_long_dqs_rank1_1; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2) = params->emc_pmacro_ob_ddll_long_dqs_rank1_2; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3) = params->emc_pmacro_ob_ddll_long_dqs_rank1_3; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4) = params->emc_pmacro_ob_ddll_long_dqs_rank1_4; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5) = params->emc_pmacro_ob_ddll_long_dqs_rank1_5; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0) = params->emc_pmacro_ib_ddll_long_dqs_rank0_0; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1) = params->emc_pmacro_ib_ddll_long_dqs_rank0_1; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2) = params->emc_pmacro_ib_ddll_long_dqs_rank0_2; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3) = params->emc_pmacro_ib_ddll_long_dqs_rank0_3; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0) = params->emc_pmacro_ib_ddll_long_dqs_rank1_0; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1) = params->emc_pmacro_ib_ddll_long_dqs_rank1_1; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2) = params->emc_pmacro_ib_ddll_long_dqs_rank1_2; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3) = params->emc_pmacro_ib_ddll_long_dqs_rank1_3; - MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_0) = params->emc_pmacro_ddll_long_cmd_0; - MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_1) = params->emc_pmacro_ddll_long_cmd_1; - MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_2) = params->emc_pmacro_ddll_long_cmd_2; - MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_3) = params->emc_pmacro_ddll_long_cmd_3; - MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_4) = params->emc_pmacro_ddll_long_cmd_4; - MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_0) = params->emc_pmacro_ddll_short_cmd_0; - MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_1) = params->emc_pmacro_ddll_short_cmd_1; - MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_2) = params->emc_pmacro_ddll_short_cmd_2; - MAKE_EMC_REG(EMC_PMACRO_COMMON_PAD_TX_CTRL) = ((params->emc_pmacro_common_pad_tx_ctrl & 1) | 0xE); + MAKE_EMC_REG(EMC_XM2COMPPADCTRL) = params->EmcXm2CompPadCtrl; + MAKE_EMC_REG(EMC_XM2COMPPADCTRL2) = params->EmcXm2CompPadCtrl2; + MAKE_EMC_REG(EMC_XM2COMPPADCTRL3) = params->EmcXm2CompPadCtrl3; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG2) = params->EmcAutoCalConfig2; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG3) = params->EmcAutoCalConfig3; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG4) = params->EmcAutoCalConfig4; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG5) = params->EmcAutoCalConfig5; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG6) = params->EmcAutoCalConfig6; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG7) = params->EmcAutoCalConfig7; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG8) = params->EmcAutoCalConfig8; + MAKE_EMC_REG(EMC_PMACRO_RX_TERM) = params->EmcPmacroRxTerm; + MAKE_EMC_REG(EMC_PMACRO_DQ_TX_DRV) = params->EmcPmacroDqTxDrv; + MAKE_EMC_REG(EMC_PMACRO_CA_TX_DRV) = params->EmcPmacroCaTxDrv; + MAKE_EMC_REG(EMC_PMACRO_CMD_TX_DRV) = params->EmcPmacroCmdTxDrv; + MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_COMMON) = params->EmcPmacroAutocalCfgCommon; + MAKE_EMC_REG(EMC_AUTO_CAL_CHANNEL) = params->EmcAutoCalChannel; + MAKE_EMC_REG(EMC_PMACRO_ZCTRL) = params->EmcPmacroZctrl; + MAKE_EMC_REG(EMC_DLL_CFG_0) = params->EmcDllCfg0; + MAKE_EMC_REG(EMC_DLL_CFG_1) = params->EmcDllCfg1; + MAKE_EMC_REG(EMC_CFG_DIG_DLL_1) = params->EmcCfgDigDll_1; + MAKE_EMC_REG(EMC_DATA_BRLSHFT_0) = params->EmcDataBrlshft0; + MAKE_EMC_REG(EMC_DATA_BRLSHFT_1) = params->EmcDataBrlshft1; + MAKE_EMC_REG(EMC_DQS_BRLSHFT_0) = params->EmcDqsBrlshft0; + MAKE_EMC_REG(EMC_DQS_BRLSHFT_1) = params->EmcDqsBrlshft1; + MAKE_EMC_REG(EMC_CMD_BRLSHFT_0) = params->EmcCmdBrlshft0; + MAKE_EMC_REG(EMC_CMD_BRLSHFT_1) = params->EmcCmdBrlshft1; + MAKE_EMC_REG(EMC_CMD_BRLSHFT_2) = params->EmcCmdBrlshft2; + MAKE_EMC_REG(EMC_CMD_BRLSHFT_3) = params->EmcCmdBrlshft3; + MAKE_EMC_REG(EMC_QUSE_BRLSHFT_0) = params->EmcQuseBrlshft0; + MAKE_EMC_REG(EMC_QUSE_BRLSHFT_1) = params->EmcQuseBrlshft1; + MAKE_EMC_REG(EMC_QUSE_BRLSHFT_2) = params->EmcQuseBrlshft2; + MAKE_EMC_REG(EMC_QUSE_BRLSHFT_3) = params->EmcQuseBrlshft3; + MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = ((params->EmcPmacroBrickCtrlRfu1 & 0x1BF01BF) | 0x1E401E40); + MAKE_EMC_REG(EMC_PMACRO_PAD_CFG_CTRL) = params->EmcPmacroPadCfgCtrl; + MAKE_EMC_REG(EMC_PMACRO_CMD_BRICK_CTRL_FDPD) = params->EmcPmacroCmdBrickCtrlFdpd; + MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU2) = (params->EmcPmacroBrickCtrlRfu2 & 0xFF7FFF7F); + MAKE_EMC_REG(EMC_PMACRO_DATA_BRICK_CTRL_FDPD) = params->EmcPmacroDataBrickCtrlFdpd; + MAKE_EMC_REG(EMC_PMACRO_BG_BIAS_CTRL_0) = params->EmcPmacroBgBiasCtrl0; + MAKE_EMC_REG(EMC_PMACRO_DATA_PAD_RX_CTRL) = params->EmcPmacroDataPadRxCtrl; + MAKE_EMC_REG(EMC_PMACRO_CMD_PAD_RX_CTRL) = params->EmcPmacroCmdPadRxCtrl; + MAKE_EMC_REG(EMC_PMACRO_DATA_PAD_TX_CTRL) = params->EmcPmacroDataPadTxCtrl; + MAKE_EMC_REG(EMC_PMACRO_DATA_RX_TERM_MODE) = params->EmcPmacroDataRxTermMode; + MAKE_EMC_REG(EMC_PMACRO_CMD_RX_TERM_MODE) = params->EmcPmacroCmdRxTermMode; + MAKE_EMC_REG(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->EmcPmacroCmdPadTxCtrl; + MAKE_EMC_REG(EMC_CFG_3) = params->EmcCfg3; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_0) = params->EmcPmacroTxPwrd0; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_1) = params->EmcPmacroTxPwrd1; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_2) = params->EmcPmacroTxPwrd2; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_3) = params->EmcPmacroTxPwrd3; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_4) = params->EmcPmacroTxPwrd4; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_5) = params->EmcPmacroTxPwrd5; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_0) = params->EmcPmacroTxSelClkSrc0; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_1) = params->EmcPmacroTxSelClkSrc1; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_2) = params->EmcPmacroTxSelClkSrc2; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_3) = params->EmcPmacroTxSelClkSrc3; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_4) = params->EmcPmacroTxSelClkSrc4; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_5) = params->EmcPmacroTxSelClkSrc5; + MAKE_EMC_REG(EMC_PMACRO_DDLL_BYPASS) = params->EmcPmacroDdllBypass; + MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_0) = params->EmcPmacroDdllPwrd0; + MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_1) = params->EmcPmacroDdllPwrd1; + MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_2) = params->EmcPmacroDdllPwrd2; + MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_0) = params->EmcPmacroCmdCtrl0; + MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_1) = params->EmcPmacroCmdCtrl1; + MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_2) = params->EmcPmacroCmdCtrl2; + MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQ_0) = params->EmcPmacroIbVrefDq_0; + MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQ_1) = params->EmcPmacroIbVrefDq_1; + MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQS_0) = params->EmcPmacroIbVrefDqs_0; + MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQS_1) = params->EmcPmacroIbVrefDqs_1; + MAKE_EMC_REG(EMC_PMACRO_IB_RXRT) = params->EmcPmacroIbRxrt; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_0) = params->EmcPmacroQuseDdllRank0_0; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_1) = params->EmcPmacroQuseDdllRank0_1; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_2) = params->EmcPmacroQuseDdllRank0_2; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_3) = params->EmcPmacroQuseDdllRank0_3; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_4) = params->EmcPmacroQuseDdllRank0_4; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_5) = params->EmcPmacroQuseDdllRank0_5; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_0) = params->EmcPmacroQuseDdllRank1_0; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_1) = params->EmcPmacroQuseDdllRank1_1; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_2) = params->EmcPmacroQuseDdllRank1_2; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_3) = params->EmcPmacroQuseDdllRank1_3; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_4) = params->EmcPmacroQuseDdllRank1_4; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_5) = params->EmcPmacroQuseDdllRank1_5; + MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = params->EmcPmacroBrickCtrlRfu1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0) = params->EmcPmacroObDdllLongDqRank0_0; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1) = params->EmcPmacroObDdllLongDqRank0_1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2) = params->EmcPmacroObDdllLongDqRank0_2; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3) = params->EmcPmacroObDdllLongDqRank0_3; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4) = params->EmcPmacroObDdllLongDqRank0_4; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5) = params->EmcPmacroObDdllLongDqRank0_5; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0) = params->EmcPmacroObDdllLongDqRank1_0; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1) = params->EmcPmacroObDdllLongDqRank1_1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2) = params->EmcPmacroObDdllLongDqRank1_2; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3) = params->EmcPmacroObDdllLongDqRank1_3; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4) = params->EmcPmacroObDdllLongDqRank1_4; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5) = params->EmcPmacroObDdllLongDqRank1_5; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0) = params->EmcPmacroObDdllLongDqsRank0_0; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1) = params->EmcPmacroObDdllLongDqsRank0_1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2) = params->EmcPmacroObDdllLongDqsRank0_2; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3) = params->EmcPmacroObDdllLongDqsRank0_3; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4) = params->EmcPmacroObDdllLongDqsRank0_4; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5) = params->EmcPmacroObDdllLongDqsRank0_5; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0) = params->EmcPmacroObDdllLongDqsRank1_0; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1) = params->EmcPmacroObDdllLongDqsRank1_1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2) = params->EmcPmacroObDdllLongDqsRank1_2; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3) = params->EmcPmacroObDdllLongDqsRank1_3; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4) = params->EmcPmacroObDdllLongDqsRank1_4; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5) = params->EmcPmacroObDdllLongDqsRank1_5; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0) = params->EmcPmacroIbDdllLongDqsRank0_0; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1) = params->EmcPmacroIbDdllLongDqsRank0_1; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2) = params->EmcPmacroIbDdllLongDqsRank0_2; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3) = params->EmcPmacroIbDdllLongDqsRank0_3; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0) = params->EmcPmacroIbDdllLongDqsRank1_0; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1) = params->EmcPmacroIbDdllLongDqsRank1_1; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2) = params->EmcPmacroIbDdllLongDqsRank1_2; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3) = params->EmcPmacroIbDdllLongDqsRank1_3; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_0) = params->EmcPmacroDdllLongCmd_0; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_1) = params->EmcPmacroDdllLongCmd_1; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_2) = params->EmcPmacroDdllLongCmd_2; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_3) = params->EmcPmacroDdllLongCmd_3; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_4) = params->EmcPmacroDdllLongCmd_4; + MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_0) = params->EmcPmacroDdllShortCmd_0; + MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_1) = params->EmcPmacroDdllShortCmd_1; + MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_2) = params->EmcPmacroDdllShortCmd_2; + MAKE_EMC_REG(EMC_PMACRO_COMMON_PAD_TX_CTRL) = ((params->EmcPmacroCommonPadTxCtrl & 1) | 0xE); - if (params->emc_bct_spare4) - *(volatile uint32_t *)params->emc_bct_spare4 = params->emc_bct_spare5; + if (params->EmcBctSpare4) { + *(volatile uint32_t *)params->EmcBctSpare4 = params->EmcBctSpare5; + } MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; - MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = params->mc_video_protect_bom; - MAKE_MC_REG(MC_VIDEO_PROTECT_BOM_ADR_HI) = params->mc_video_protect_bom_adr_hi; - MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = params->mc_video_protect_size_mb; - MAKE_MC_REG(MC_VIDEO_PROTECT_VPR_OVERRIDE) = params->mc_video_protect_vpr_override; - MAKE_MC_REG(MC_VIDEO_PROTECT_VPR_OVERRIDE1) = params->mc_video_protect_vpr_override1; - MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = params->mc_video_protect_gpu_override0; - MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = params->mc_video_protect_gpu_override1; - MAKE_MC_REG(MC_EMEM_ADR_CFG) = params->mc_emem_adr_cfg; - MAKE_MC_REG(MC_EMEM_ADR_CFG_DEV0) = params->mc_emem_adr_cfg_dev0; - MAKE_MC_REG(MC_EMEM_ADR_CFG_DEV1) = params->mc_emem_adr_cfg_dev1; - MAKE_MC_REG(MC_EMEM_ADR_CFG_CHANNEL_MASK) = params->mc_emem_adr_cfg_channel_mask; - MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_0) = params->mc_emem_adr_cfg_bank_mask0; - MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_1) = params->mc_emem_adr_cfg_bank_mask1; - MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_2) = params->mc_emem_adr_cfg_bank_mask2; - MAKE_MC_REG(MC_EMEM_CFG) = params->mc_emem_cfg; - MAKE_MC_REG(MC_SEC_CARVEOUT_BOM) = params->mc_sec_carveout_bom; - MAKE_MC_REG(MC_SEC_CARVEOUT_ADR_HI) = params->mc_sec_carveout_adr_hi; - MAKE_MC_REG(MC_SEC_CARVEOUT_SIZE_MB) = params->mc_sec_carveout_size_mb; - MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = params->mc_mts_carveout_bom; - MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = params->mc_mts_carveout_adr_hi; - MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = params->mc_mts_carveout_size_mb; - MAKE_MC_REG(MC_EMEM_ARB_CFG) = params->mc_emem_arb_cfg; - MAKE_MC_REG(MC_EMEM_ARB_OUTSTANDING_REQ) = params->mc_emem_arb_outstanding_req; - MAKE_MC_REG(MC_EMEM_ARB_REFPB_HP_CTRL) = params->emc_emem_arb_refpb_hp_ctrl; - MAKE_MC_REG(MC_EMEM_ARB_REFPB_BANK_CTRL) = params->emc_emem_arb_refpb_bank_ctrl; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RCD) = params->mc_emem_arb_timing_rcd; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RP) = params->mc_emem_arb_timing_rp; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RC) = params->mc_emem_arb_timing_rc; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RAS) = params->mc_emem_arb_timing_ras; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_FAW) = params->mc_emem_arb_timing_faw; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RRD) = params->mc_emem_arb_timing_rrd; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RAP2PRE) = params->mc_emem_arb_timing_rap2pre; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_WAP2PRE) = params->mc_emem_arb_timing_wap2pre; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_R2R) = params->mc_emem_arb_timing_r2r; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_W2W) = params->mc_emem_arb_timing_w2w; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_CCDMW) = params->mc_emem_arb_timing_ccdmw; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_R2W) = params->mc_emem_arb_timing_r2w; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_W2R) = params->mc_emem_arb_timing_w2r; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RFCPB) = params->mc_emem_arb_timing_rfcpb; - MAKE_MC_REG(MC_EMEM_ARB_DA_TURNS) = params->mc_emem_arb_da_turns; - MAKE_MC_REG(MC_EMEM_ARB_DA_COVERS) = params->mc_emem_arb_da_covers; - MAKE_MC_REG(MC_EMEM_ARB_MISC0) = params->mc_emem_arb_misc0; - MAKE_MC_REG(MC_EMEM_ARB_MISC1) = params->mc_emem_arb_misc1; - MAKE_MC_REG(MC_EMEM_ARB_MISC2) = params->mc_emem_arb_misc2; - MAKE_MC_REG(MC_EMEM_ARB_RING1_THROTTLE) = params->mc_emem_arb_ring1_throttle; - MAKE_MC_REG(MC_EMEM_ARB_OVERRIDE) = params->mc_emem_arb_override; - MAKE_MC_REG(MC_EMEM_ARB_OVERRIDE_1) = params->mc_emem_arb_override1; - MAKE_MC_REG(MC_EMEM_ARB_RSV) = params->mc_emem_arb_rsv; - MAKE_MC_REG(MC_DA_CONFIG0) = params->mc_da_cfg0; + MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = params->McVideoProtectBom; + MAKE_MC_REG(MC_VIDEO_PROTECT_BOM_ADR_HI) = params->McVideoProtectBomAdrHi; + MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = params->McVideoProtectSizeMb; + MAKE_MC_REG(MC_VIDEO_PROTECT_VPR_OVERRIDE) = params->McVideoProtectVprOverride; + MAKE_MC_REG(MC_VIDEO_PROTECT_VPR_OVERRIDE1) = params->McVideoProtectVprOverride1; + MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = params->McVideoProtectGpuOverride0; + MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = params->McVideoProtectGpuOverride1; + MAKE_MC_REG(MC_EMEM_ADR_CFG) = params->McEmemAdrCfg; + MAKE_MC_REG(MC_EMEM_ADR_CFG_DEV0) = params->McEmemAdrCfgDev0; + MAKE_MC_REG(MC_EMEM_ADR_CFG_DEV1) = params->McEmemAdrCfgDev1; + MAKE_MC_REG(MC_EMEM_ADR_CFG_CHANNEL_MASK) = params->McEmemAdrCfgChannelMask; + MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_0) = params->McEmemAdrCfgBankMask0; + MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_1) = params->McEmemAdrCfgBankMask1; + MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_2) = params->McEmemAdrCfgBankMask2; + MAKE_MC_REG(MC_EMEM_CFG) = params->McEmemCfg; + MAKE_MC_REG(MC_SEC_CARVEOUT_BOM) = params->McSecCarveoutBom; + MAKE_MC_REG(MC_SEC_CARVEOUT_ADR_HI) = params->McSecCarveoutAdrHi; + MAKE_MC_REG(MC_SEC_CARVEOUT_SIZE_MB) = params->McSecCarveoutSizeMb; + MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = params->McMtsCarveoutBom; + MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = params->McMtsCarveoutAdrHi; + MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = params->McMtsCarveoutSizeMb; + MAKE_MC_REG(MC_EMEM_ARB_CFG) = params->McEmemArbCfg; + MAKE_MC_REG(MC_EMEM_ARB_OUTSTANDING_REQ) = params->McEmemArbOutstandingReq; + MAKE_MC_REG(MC_EMEM_ARB_REFPB_HP_CTRL) = params->McEmemArbRefpbHpCtrl; + MAKE_MC_REG(MC_EMEM_ARB_REFPB_BANK_CTRL) = params->McEmemArbRefpbBankCtrl; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RCD) = params->McEmemArbTimingRcd; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RP) = params->McEmemArbTimingRp; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RC) = params->McEmemArbTimingRc; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RAS) = params->McEmemArbTimingRas; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_FAW) = params->McEmemArbTimingFaw; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RRD) = params->McEmemArbTimingRrd; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RAP2PRE) = params->McEmemArbTimingRap2Pre; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_WAP2PRE) = params->McEmemArbTimingWap2Pre; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_R2R) = params->McEmemArbTimingR2R; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_W2W) = params->McEmemArbTimingW2W; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_CCDMW) = params->McEmemArbTimingCcdmw; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_R2W) = params->McEmemArbTimingR2W; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_W2R) = params->McEmemArbTimingW2R; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RFCPB) = params->McEmemArbTimingRFCPB; + MAKE_MC_REG(MC_EMEM_ARB_DA_TURNS) = params->McEmemArbDaTurns; + MAKE_MC_REG(MC_EMEM_ARB_DA_COVERS) = params->McEmemArbDaCovers; + MAKE_MC_REG(MC_EMEM_ARB_MISC0) = params->McEmemArbMisc0; + MAKE_MC_REG(MC_EMEM_ARB_MISC1) = params->McEmemArbMisc1; + MAKE_MC_REG(MC_EMEM_ARB_MISC2) = params->McEmemArbMisc2; + MAKE_MC_REG(MC_EMEM_ARB_RING1_THROTTLE) = params->McEmemArbRing1Throttle; + MAKE_MC_REG(MC_EMEM_ARB_OVERRIDE) = params->McEmemArbOverride; + MAKE_MC_REG(MC_EMEM_ARB_OVERRIDE_1) = params->McEmemArbOverride1; + MAKE_MC_REG(MC_EMEM_ARB_RSV) = params->McEmemArbRsv; + MAKE_MC_REG(MC_DA_CONFIG0) = params->McDaCfg0; MAKE_MC_REG(MC_TIMING_CONTROL) = 1; - MAKE_MC_REG(MC_CLKEN_OVERRIDE) = params->mc_clken_override; - MAKE_MC_REG(MC_STAT_CONTROL) = params->mc_stat_control; + MAKE_MC_REG(MC_CLKEN_OVERRIDE) = params->McClkenOverride; + MAKE_MC_REG(MC_STAT_CONTROL) = params->McStatControl; - MAKE_EMC_REG(EMC_ADR_CFG) = params->emc_adr_cfg; - MAKE_EMC_REG(EMC_CLKEN_OVERRIDE) = params->emc_clken_override; - MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_0) = params->emc_pmacro_auto_cal_cfg0; - MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_1) = params->emc_pmacro_auto_cal_cfg1; - MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_2) = params->emc_pmacro_auto_cal_cfg2; - MAKE_EMC_REG(EMC_AUTO_CAL_VREF_SEL_0) = params->emc_auto_cal_vref_sel0; - MAKE_EMC_REG(EMC_AUTO_CAL_VREF_SEL_1) = params->emc_auto_cal_vref_sel1; - MAKE_EMC_REG(EMC_AUTO_CAL_INTERVAL) = params->emc_auto_cal_interval; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config; - udelay(params->emc_auto_cal_wait); + MAKE_EMC_REG(EMC_ADR_CFG) = params->EmcAdrCfg; + MAKE_EMC_REG(EMC_CLKEN_OVERRIDE) = params->EmcClkenOverride; + MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_0) = params->EmcPmacroAutocalCfg0; + MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_1) = params->EmcPmacroAutocalCfg1; + MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_2) = params->EmcPmacroAutocalCfg2; + MAKE_EMC_REG(EMC_AUTO_CAL_VREF_SEL_0) = params->EmcAutoCalVrefSel0; + MAKE_EMC_REG(EMC_AUTO_CAL_VREF_SEL_1) = params->EmcAutoCalVrefSel1; + MAKE_EMC_REG(EMC_AUTO_CAL_INTERVAL) = params->EmcAutoCalInterval; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG) = params->EmcAutoCalConfig; + udelay(params->EmcAutoCalWait); - if (params->emc_bct_spare8) - *(volatile uint32_t *)params->emc_bct_spare8 = params->emc_bct_spare9; + if (params->EmcBctSpare8) { + *(volatile uint32_t *)params->EmcBctSpare8 = params->EmcBctSpare9; + } - MAKE_EMC_REG(EMC_CFG_2) = params->emc_cfg2; - MAKE_EMC_REG(EMC_CFG_PIPE) = params->emc_cfg_pipe; - MAKE_EMC_REG(EMC_CFG_PIPE_1) = params->emc_cfg_pipe1; - MAKE_EMC_REG(EMC_CFG_PIPE_2) = params->emc_cfg_pipe2; - MAKE_EMC_REG(EMC_CMDQ) = params->emc_cmd_q; - MAKE_EMC_REG(EMC_MC2EMCQ) = params->emc_mc2emc_q; - MAKE_EMC_REG(EMC_MRS_WAIT_CNT) = params->emc_mrs_wait_cnt; - MAKE_EMC_REG(EMC_MRS_WAIT_CNT2) = params->emc_mrs_wait_cnt2; - MAKE_EMC_REG(EMC_FBIO_CFG5) = params->emc_fbio_cfg5; - MAKE_EMC_REG(EMC_RC) = params->emc_rc; - MAKE_EMC_REG(EMC_RFC) = params->emc_rfc; - MAKE_EMC_REG(EMC_RFCPB) = params->emc_rfc_pb; - MAKE_EMC_REG(EMC_REFCTRL2) = params->emc_ref_ctrl2; - MAKE_EMC_REG(EMC_RFC_SLR) = params->emc_rfc_slr; - MAKE_EMC_REG(EMC_RAS) = params->emc_ras; - MAKE_EMC_REG(EMC_RP) = params->emc_rp; - MAKE_EMC_REG(EMC_TPPD) = params->emc_tppd; - MAKE_EMC_REG(EMC_R2R) = params->emc_r2r; - MAKE_EMC_REG(EMC_W2W) = params->emc_w2w; - MAKE_EMC_REG(EMC_R2W) = params->emc_r2w; - MAKE_EMC_REG(EMC_W2R) = params->emc_w2r; - MAKE_EMC_REG(EMC_R2P) = params->emc_r2p; - MAKE_EMC_REG(EMC_W2P) = params->emc_w2p; - MAKE_EMC_REG(EMC_CCDMW) = params->emc_ccdmw; - MAKE_EMC_REG(EMC_RD_RCD) = params->emc_rd_rcd; - MAKE_EMC_REG(EMC_WR_RCD) = params->emc_wr_rcd; - MAKE_EMC_REG(EMC_RRD) = params->emc_rrd; - MAKE_EMC_REG(EMC_REXT) = params->emc_rext; - MAKE_EMC_REG(EMC_WEXT) = params->emc_wext; - MAKE_EMC_REG(EMC_WDV) = params->emc_wdv; - MAKE_EMC_REG(EMC_WDV_CHK) = params->emc_wdv_chk; - MAKE_EMC_REG(EMC_WSV) = params->emc_wsv; - MAKE_EMC_REG(EMC_WEV) = params->emc_wev; - MAKE_EMC_REG(EMC_WDV_MASK) = params->emc_wdv_mask; - MAKE_EMC_REG(EMC_WS_DURATION) = params->emc_ws_duration; - MAKE_EMC_REG(EMC_WE_DURATION) = params->emc_we_duration; - MAKE_EMC_REG(EMC_QUSE) = params->emc_quse; - MAKE_EMC_REG(EMC_QUSE_WIDTH) = params->emc_quse_width; - MAKE_EMC_REG(EMC_IBDLY) = params->emc_ibdly; - MAKE_EMC_REG(EMC_OBDLY) = params->emc_obdly; - MAKE_EMC_REG(EMC_EINPUT) = params->emc_einput; - MAKE_EMC_REG(EMC_EINPUT_DURATION) = params->emc_einput_duration; - MAKE_EMC_REG(EMC_PUTERM_EXTRA) = params->emc_puterm_extra; - MAKE_EMC_REG(EMC_PUTERM_WIDTH) = params->emc_puterm_width; - MAKE_EMC_REG(EMC_PMACRO_COMMON_PAD_TX_CTRL) = params->emc_pmacro_common_pad_tx_ctrl; - MAKE_EMC_REG(EMC_DBG) = params->emc_dbg; - MAKE_EMC_REG(EMC_QRST) = params->emc_qrst; + MAKE_EMC_REG(EMC_CFG_2) = params->EmcCfg2; + MAKE_EMC_REG(EMC_CFG_PIPE) = params->EmcCfgPipe; + MAKE_EMC_REG(EMC_CFG_PIPE_1) = params->EmcCfgPipe1; + MAKE_EMC_REG(EMC_CFG_PIPE_2) = params->EmcCfgPipe2; + MAKE_EMC_REG(EMC_CMDQ) = params->EmcCmdQ; + MAKE_EMC_REG(EMC_MC2EMCQ) = params->EmcMc2EmcQ; + MAKE_EMC_REG(EMC_MRS_WAIT_CNT) = params->EmcMrsWaitCnt; + MAKE_EMC_REG(EMC_MRS_WAIT_CNT2) = params->EmcMrsWaitCnt2; + MAKE_EMC_REG(EMC_FBIO_CFG5) = params->EmcFbioCfg5; + MAKE_EMC_REG(EMC_RC) = params->EmcRc; + MAKE_EMC_REG(EMC_RFC) = params->EmcRfc; + MAKE_EMC_REG(EMC_RFCPB) = params->EmcRfcPb; + MAKE_EMC_REG(EMC_REFCTRL2) = params->EmcRefctrl2; + MAKE_EMC_REG(EMC_RFC_SLR) = params->EmcRfcSlr; + MAKE_EMC_REG(EMC_RAS) = params->EmcRas; + MAKE_EMC_REG(EMC_RP) = params->EmcRp; + MAKE_EMC_REG(EMC_TPPD) = params->EmcTppd; + MAKE_EMC_REG(EMC_R2R) = params->EmcR2r; + MAKE_EMC_REG(EMC_W2W) = params->EmcW2w; + MAKE_EMC_REG(EMC_R2W) = params->EmcR2w; + MAKE_EMC_REG(EMC_W2R) = params->EmcW2r; + MAKE_EMC_REG(EMC_R2P) = params->EmcR2p; + MAKE_EMC_REG(EMC_W2P) = params->EmcW2p; + MAKE_EMC_REG(EMC_CCDMW) = params->EmcCcdmw; + MAKE_EMC_REG(EMC_RD_RCD) = params->EmcRdRcd; + MAKE_EMC_REG(EMC_WR_RCD) = params->EmcWrRcd; + MAKE_EMC_REG(EMC_RRD) = params->EmcRrd; + MAKE_EMC_REG(EMC_REXT) = params->EmcRext; + MAKE_EMC_REG(EMC_WEXT) = params->EmcWext; + MAKE_EMC_REG(EMC_WDV) = params->EmcWdv; + MAKE_EMC_REG(EMC_WDV_CHK) = params->EmcWdvChk; + MAKE_EMC_REG(EMC_WSV) = params->EmcWsv; + MAKE_EMC_REG(EMC_WEV) = params->EmcWev; + MAKE_EMC_REG(EMC_WDV_MASK) = params->EmcWdvMask; + MAKE_EMC_REG(EMC_WS_DURATION) = params->EmcWsDuration; + MAKE_EMC_REG(EMC_WE_DURATION) = params->EmcWeDuration; + MAKE_EMC_REG(EMC_QUSE) = params->EmcQUse; + MAKE_EMC_REG(EMC_QUSE_WIDTH) = params->EmcQuseWidth; + MAKE_EMC_REG(EMC_IBDLY) = params->EmcIbdly; + MAKE_EMC_REG(EMC_OBDLY) = params->EmcObdly; + MAKE_EMC_REG(EMC_EINPUT) = params->EmcEInput; + MAKE_EMC_REG(EMC_EINPUT_DURATION) = params->EmcEInputDuration; + MAKE_EMC_REG(EMC_PUTERM_EXTRA) = params->EmcPutermExtra; + MAKE_EMC_REG(EMC_PUTERM_WIDTH) = params->EmcPutermWidth; + MAKE_EMC_REG(EMC_PMACRO_COMMON_PAD_TX_CTRL) = params->EmcPmacroCommonPadTxCtrl; + MAKE_EMC_REG(EMC_DBG) = params->EmcDbg; + MAKE_EMC_REG(EMC_QRST) = params->EmcQRst; MAKE_EMC_REG(EMC_ISSUE_QRST) = 0; - MAKE_EMC_REG(EMC_QSAFE) = params->emc_qsafe; - MAKE_EMC_REG(EMC_RDV) = params->emc_rdv; - MAKE_EMC_REG(EMC_RDV_MASK) = params->emc_rdv_mask; - MAKE_EMC_REG(EMC_RDV_EARLY) = params->emc_rdv_early; - MAKE_EMC_REG(EMC_RDV_EARLY_MASK) = params->emc_rdv_early_mask; - MAKE_EMC_REG(EMC_QPOP) = params->emc_qpop; - MAKE_EMC_REG(EMC_REFRESH) = params->emc_refresh; - MAKE_EMC_REG(EMC_BURST_REFRESH_NUM) = params->emc_burst_refresh_num; - MAKE_EMC_REG(EMC_PRE_REFRESH_REQ_CNT) = params->emc_prerefresh_req_cnt; - MAKE_EMC_REG(EMC_PDEX2WR) = params->emc_pdex2wr; - MAKE_EMC_REG(EMC_PDEX2RD) = params->emc_pdex2rd; - MAKE_EMC_REG(EMC_PCHG2PDEN) = params->emc_pchg2pden; - MAKE_EMC_REG(EMC_ACT2PDEN) = params->emc_act2pden; - MAKE_EMC_REG(EMC_AR2PDEN) = params->emc_ar2pden; - MAKE_EMC_REG(EMC_RW2PDEN) = params->emc_rw2pden; - MAKE_EMC_REG(EMC_CKE2PDEN) = params->emc_cke2pden; - MAKE_EMC_REG(EMC_PDEX2CKE) = params->emc_pdex2che; - MAKE_EMC_REG(EMC_PDEX2MRR) = params->emc_pdex2mrr; - MAKE_EMC_REG(EMC_TXSR) = params->emc_txsr; - MAKE_EMC_REG(EMC_TXSRDLL) = params->emc_txsr_dll; - MAKE_EMC_REG(EMC_TCKE) = params->emc_tcke; - MAKE_EMC_REG(EMC_TCKESR) = params->emc_tckesr; - MAKE_EMC_REG(EMC_TPD) = params->emc_tpd; - MAKE_EMC_REG(EMC_TFAW) = params->emc_tfaw; - MAKE_EMC_REG(EMC_TRPAB) = params->emc_trpab; - MAKE_EMC_REG(EMC_TCLKSTABLE) = params->emc_tclkstable; - MAKE_EMC_REG(EMC_TCLKSTOP) = params->emc_tclkstop; - MAKE_EMC_REG(EMC_TREFBW) = params->emc_trefbw; - MAKE_EMC_REG(EMC_ODT_WRITE) = params->emc_odt_write; - MAKE_EMC_REG(EMC_CFG_DIG_DLL) = params->emc_cfg_dig_dll; - MAKE_EMC_REG(EMC_CFG_DIG_DLL_PERIOD) = params->emc_cfg_dig_dll_period; - MAKE_EMC_REG(EMC_FBIO_SPARE) = params->emc_fbio_spare & 0xFFFFFFFD; - MAKE_EMC_REG(EMC_CFG_RSV) = params->emc_cfg_rsv; - MAKE_EMC_REG(EMC_PMC_SCRATCH1) = params->emc_pmc_scratch1; - MAKE_EMC_REG(EMC_PMC_SCRATCH2) = params->emc_pmc_scratch2; - MAKE_EMC_REG(EMC_PMC_SCRATCH3) = params->emc_pmc_scratch3; - MAKE_EMC_REG(EMC_ACPD_CONTROL) = params->emc_acpd_control; - MAKE_EMC_REG(EMC_TXDSRVTTGEN) = params->emc_txdsrvttgen; - MAKE_EMC_REG(EMC_CFG) = (params->emc_cfg & 0xE) | 0x3C00000; + MAKE_EMC_REG(EMC_QSAFE) = params->EmcQSafe; + MAKE_EMC_REG(EMC_RDV) = params->EmcRdv; + MAKE_EMC_REG(EMC_RDV_MASK) = params->EmcRdvMask; + MAKE_EMC_REG(EMC_RDV_EARLY) = params->EmcRdvEarly; + MAKE_EMC_REG(EMC_RDV_EARLY_MASK) = params->EmcRdvEarlyMask; + MAKE_EMC_REG(EMC_QPOP) = params->EmcQpop; + MAKE_EMC_REG(EMC_REFRESH) = params->EmcRefresh; + MAKE_EMC_REG(EMC_BURST_REFRESH_NUM) = params->EmcBurstRefreshNum; + MAKE_EMC_REG(EMC_PRE_REFRESH_REQ_CNT) = params->EmcPreRefreshReqCnt; + MAKE_EMC_REG(EMC_PDEX2WR) = params->EmcPdEx2Wr; + MAKE_EMC_REG(EMC_PDEX2RD) = params->EmcPdEx2Rd; + MAKE_EMC_REG(EMC_PCHG2PDEN) = params->EmcPChg2Pden; + MAKE_EMC_REG(EMC_ACT2PDEN) = params->EmcAct2Pden; + MAKE_EMC_REG(EMC_AR2PDEN) = params->EmcAr2Pden; + MAKE_EMC_REG(EMC_RW2PDEN) = params->EmcRw2Pden; + MAKE_EMC_REG(EMC_CKE2PDEN) = params->EmcCke2Pden; + MAKE_EMC_REG(EMC_PDEX2CKE) = params->EmcPdex2Cke; + MAKE_EMC_REG(EMC_PDEX2MRR) = params->EmcPdex2Mrr; + MAKE_EMC_REG(EMC_TXSR) = params->EmcTxsr; + MAKE_EMC_REG(EMC_TXSRDLL) = params->EmcTxsrDll; + MAKE_EMC_REG(EMC_TCKE) = params->EmcTcke; + MAKE_EMC_REG(EMC_TCKESR) = params->EmcTckesr; + MAKE_EMC_REG(EMC_TPD) = params->EmcTpd; + MAKE_EMC_REG(EMC_TFAW) = params->EmcTfaw; + MAKE_EMC_REG(EMC_TRPAB) = params->EmcTrpab; + MAKE_EMC_REG(EMC_TCLKSTABLE) = params->EmcTClkStable; + MAKE_EMC_REG(EMC_TCLKSTOP) = params->EmcTClkStop; + MAKE_EMC_REG(EMC_TREFBW) = params->EmcTRefBw; + MAKE_EMC_REG(EMC_ODT_WRITE) = params->EmcOdtWrite; + MAKE_EMC_REG(EMC_CFG_DIG_DLL) = params->EmcCfgDigDll; + MAKE_EMC_REG(EMC_CFG_DIG_DLL_PERIOD) = params->EmcCfgDigDllPeriod; + MAKE_EMC_REG(EMC_FBIO_SPARE) = params->EmcFbioSpare & 0xFFFFFFFD; + MAKE_EMC_REG(EMC_CFG_RSV) = params->EmcCfgRsv; + MAKE_EMC_REG(EMC_PMC_SCRATCH1) = params->EmcPmcScratch1; + MAKE_EMC_REG(EMC_PMC_SCRATCH2) = params->EmcPmcScratch2; + MAKE_EMC_REG(EMC_PMC_SCRATCH3) = params->EmcPmcScratch3; + MAKE_EMC_REG(EMC_ACPD_CONTROL) = params->EmcAcpdControl; + MAKE_EMC_REG(EMC_TXDSRVTTGEN) = params->EmcTxdsrvttgen; + MAKE_EMC_REG(EMC_CFG) = (params->EmcCfg & 0xE) | 0x3C00000; - if (params->boot_rom_patch_control & 0x80000000) - { - *(volatile uint32_t *)(4 * (params->boot_rom_patch_control + 0x1C000000)) = params->boot_rom_patch_data; + if (params->BootRomPatchControl & 0x80000000) { + *(volatile uint32_t *)(4 * (params->BootRomPatchControl + 0x1C000000)) = params->BootRomPatchData; MAKE_MC_REG(MC_TIMING_CONTROL) = 1; } - pmc->io_dpd3_req = (((4 * params->emc_pmc_scratch1 >> 2) + 0x40000000) & 0xCFFF0000); - udelay(params->pmc_io_dpd3_req_wait); + pmc->io_dpd3_req = (((4 * params->EmcPmcScratch1 >> 2) + 0x40000000) & 0xCFFF0000); + udelay(params->PmcIoDpd3ReqWait); - if (!params->emc_auto_cal_interval) - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG) = (params->emc_auto_cal_config | 0x200); + if (!params->EmcAutoCalInterval) { + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG) = (params->EmcAutoCalConfig | 0x200); + } - MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU2) = params->emc_pmacro_brick_ctrl_rfu2; + MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU2) = params->EmcPmacroBrickCtrlRfu2; - if (params->emc_zcal_warm_cold_boot_enables & 1) - { - if (params->memory_type == 2) - MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = (8 * params->emc_zcal_wait_cnt); - - if (params->memory_type == 3) - { - MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt; - MAKE_EMC_REG(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; + if (params->EmcZcalWarmColdBootEnables & 1) { + if (params->MemoryType == NvBootMemoryType_Ddr3) { + MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = (8 * params->EmcZcalWaitCnt); + } else if (params->MemoryType == NvBootMemoryType_LpDdr4) { + MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = params->EmcZcalWaitCnt; + MAKE_EMC_REG(EMC_ZCAL_MRW_CMD) = params->EmcZcalMrwCmd; } } MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; - udelay(params->emc_timing_control_wait); + udelay(params->EmcTimingControlWait); pmc->ddr_cntrl &= 0xFFF8007F; - udelay(params->pmc_ddr_ctrl_wait); + udelay(params->PmcDdrCntrlWait); - if (params->memory_type == 2) - { - MAKE_EMC_REG(EMC_PIN) = ((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)); - udelay(params->emc_pin_extra_wait + 200); - MAKE_EMC_REG(EMC_PIN) = (((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 256); - udelay(params->emc_pin_extra_wait + 500); + MAKE_EMC_REG(EMC_PIN) = (params->EmcPinGpioEn << 16) | (params->EmcPinGpio << 12); + udelay(params->EmcPinExtraWait + 200); + MAKE_EMC_REG(EMC_PIN) = ((params->EmcPinGpioEn << 16) | (params->EmcPinGpio << 12)) + 256; + + if (params->MemoryType == NvBootMemoryType_Ddr3) { + udelay(params->EmcPinExtraWait + 500); + } else if (params->MemoryType == NvBootMemoryType_LpDdr4) { + udelay(params->EmcPinExtraWait + 2000); } - if (params->memory_type == 3) - { - MAKE_EMC_REG(EMC_PIN) = ((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)); - udelay(params->emc_pin_extra_wait + 200); - MAKE_EMC_REG(EMC_PIN) = (((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 256); - udelay(params->emc_pin_extra_wait + 2000); - } + MAKE_EMC_REG(EMC_PIN) = (((params->EmcPinGpioEn << 16) | (params->EmcPinGpio << 12)) + 0x101); + udelay(params->EmcPinProgramWait); - MAKE_EMC_REG(EMC_PIN) = (((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 0x101); - udelay(params->emc_pin_program_wait); - - if (params->memory_type != 3) - MAKE_EMC_REG(EMC_NOP) = ((params->emc_dev_select << 30) + 1); - - if (params->memory_type == 1) - udelay(params->emc_pin_extra_wait + 200); - - if (params->memory_type == 3) - { - if (params->emc_bct_spare10) - *(volatile uint32_t *)params->emc_bct_spare10 = params->emc_bct_spare11; + if (params->MemoryType != NvBootMemoryType_LpDdr4) { + MAKE_EMC_REG(EMC_NOP) = (params->EmcDevSelect << 30) + 1; + if (params->MemoryType == NvBootMemoryType_LpDdr2) { + udelay(params->EmcPinExtraWait + 200); + } + } else { + if (params->EmcBctSpare10) { + *(volatile uint32_t *)params->EmcBctSpare10 = params->EmcBctSpare11; + } - MAKE_EMC_REG(EMC_MRW2) = params->emc_mrw2; - MAKE_EMC_REG(EMC_MRW) = params->emc_mrw1; - MAKE_EMC_REG(EMC_MRW3) = params->emc_mrw3; - MAKE_EMC_REG(EMC_MRW4) = params->emc_mrw4; - MAKE_EMC_REG(EMC_MRW6) = params->emc_mrw6; - MAKE_EMC_REG(EMC_MRW14) = params->emc_mrw14; - MAKE_EMC_REG(EMC_MRW8) = params->emc_mrw8; - MAKE_EMC_REG(EMC_MRW12) = params->emc_mrw12; - MAKE_EMC_REG(EMC_MRW9) = params->emc_mrw9; - MAKE_EMC_REG(EMC_MRW13) = params->emc_mrw13; + MAKE_EMC_REG(EMC_MRW2) = params->EmcMrw2; + MAKE_EMC_REG(EMC_MRW) = params->EmcMrw1; + MAKE_EMC_REG(EMC_MRW3) = params->EmcMrw3; + MAKE_EMC_REG(EMC_MRW4) = params->EmcMrw4; + MAKE_EMC_REG(EMC_MRW6) = params->EmcMrw6; + MAKE_EMC_REG(EMC_MRW14) = params->EmcMrw14; + MAKE_EMC_REG(EMC_MRW8) = params->EmcMrw8; + MAKE_EMC_REG(EMC_MRW12) = params->EmcMrw12; + MAKE_EMC_REG(EMC_MRW9) = params->EmcMrw9; + MAKE_EMC_REG(EMC_MRW13) = params->EmcMrw13; - if (params->emc_zcal_warm_cold_boot_enables & 1) - { - MAKE_EMC_REG(EMC_ZQ_CAL) = params->emc_zcal_init_dev0; - udelay(params->emc_zcal_init_wait); - MAKE_EMC_REG(EMC_ZQ_CAL) = (params->emc_zcal_init_dev0 ^ 3); + if (params->EmcZcalWarmColdBootEnables & 1) { + MAKE_EMC_REG(EMC_ZQ_CAL) = params->EmcZcalInitDev0; + udelay(params->EmcZcalInitWait); + MAKE_EMC_REG(EMC_ZQ_CAL) = (params->EmcZcalInitDev0 ^ 3); - if (!(params->emc_dev_select & 2)) - { - MAKE_EMC_REG(EMC_ZQ_CAL) = params->emc_zcal_init_dev1; - udelay(params->emc_zcal_init_wait); - MAKE_EMC_REG(EMC_ZQ_CAL) = (params->emc_zcal_init_dev1 ^ 3); + if (!(params->EmcDevSelect & 2)) { + MAKE_EMC_REG(EMC_ZQ_CAL) = params->EmcZcalInitDev1; + udelay(params->EmcZcalInitWait); + MAKE_EMC_REG(EMC_ZQ_CAL) = (params->EmcZcalInitDev1 ^ 3); } } } - pmc->ddr_cfg = params->pmc_ddr_cfg; - if ((params->memory_type - 1) <= 2) - { - MAKE_EMC_REG(EMC_ZCAL_INTERVAL) = params->emc_zcal_interval; - MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt; - MAKE_EMC_REG(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; + pmc->ddr_cfg = params->PmcDdrCfg; + if ((params->MemoryType == NvBootMemoryType_LpDdr2) + || (params->MemoryType == NvBootMemoryType_Ddr3) + || (params->MemoryType == NvBootMemoryType_LpDdr4)) { + MAKE_EMC_REG(EMC_ZCAL_INTERVAL) = params->EmcZcalInterval; + MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = params->EmcZcalWaitCnt; + MAKE_EMC_REG(EMC_ZCAL_MRW_CMD) = params->EmcZcalMrwCmd; } - if (params->emc_bct_spare12) - *(volatile uint32_t *)params->emc_bct_spare12 = params->emc_bct_spare13; + if (params->EmcBctSpare12) { + *(volatile uint32_t *)params->EmcBctSpare12 = params->EmcBctSpare13; + } MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; - if (params->emc_extra_refresh_num) - MAKE_EMC_REG(EMC_REF) = (((1 << params->emc_extra_refresh_num << 8) - 0xFD) | (params->emc_pin_gpio << 30)); + if (params->EmcExtraRefreshNum) { + MAKE_EMC_REG(EMC_REF) = (((1 << params->EmcExtraRefreshNum << 8) - 0xFD) | (params->EmcPinGpio << 30)); + } - MAKE_EMC_REG(EMC_REFCTRL) = (params->emc_dev_select | 0x80000000); - MAKE_EMC_REG(EMC_DYN_SELF_REF_CONTROL) = params->emc_dyn_self_ref_control; - MAKE_EMC_REG(EMC_CFG_UPDATE) = params->emc_cfg_update; - MAKE_EMC_REG(EMC_CFG) = params->emc_cfg; - MAKE_EMC_REG(EMC_FDPD_CTRL_DQ) = params->emc_fdpd_ctrl_dq; - MAKE_EMC_REG(EMC_FDPD_CTRL_CMD) = params->emc_fdpd_ctrl_cmd; - MAKE_EMC_REG(EMC_SEL_DPD_CTRL) = params->emc_sel_dpd_ctrl; - MAKE_EMC_REG(EMC_FBIO_SPARE) = (params->emc_fbio_spare | 2); + MAKE_EMC_REG(EMC_REFCTRL) = (params->EmcDevSelect | 0x80000000); + MAKE_EMC_REG(EMC_DYN_SELF_REF_CONTROL) = params->EmcDynSelfRefControl; + MAKE_EMC_REG(EMC_CFG_UPDATE) = params->EmcCfgUpdate; + MAKE_EMC_REG(EMC_CFG) = params->EmcCfg; + MAKE_EMC_REG(EMC_FDPD_CTRL_DQ) = params->EmcFdpdCtrlDq; + MAKE_EMC_REG(EMC_FDPD_CTRL_CMD) = params->EmcFdpdCtrlCmd; + MAKE_EMC_REG(EMC_SEL_DPD_CTRL) = params->EmcSelDpdCtrl; + MAKE_EMC_REG(EMC_FBIO_SPARE) = (params->EmcFbioSpare | 2); MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; - MAKE_EMC_REG(EMC_CFG_PIPE_CLK) = params->emc_cfg_pipe_clk; - MAKE_EMC_REG(EMC_FDPD_CTRL_CMD_NO_RAMP) = params->emc_fdpd_ctrl_cmd_no_ramp; + MAKE_EMC_REG(EMC_CFG_PIPE_CLK) = params->EmcCfgPipeClk; + MAKE_EMC_REG(EMC_FDPD_CTRL_CMD_NO_RAMP) = params->EmcFdpdCtrlCmdNoRamp; - AHB_ARBITRATION_XBAR_CTRL_0 = ((AHB_ARBITRATION_XBAR_CTRL_0 & 0xFFFEFFFF) | ((params->ahb_arbitration_xbar_ctrl_meminit_done & 0xFFFF) << 16)); + AHB_ARBITRATION_XBAR_CTRL_0 = ((AHB_ARBITRATION_XBAR_CTRL_0 & 0xFFFEFFFF) | ((params->AhbArbitrationXbarCtrlMemInitDone & 0xFFFF) << 16)); - MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = params->mc_video_protect_write_access; - MAKE_MC_REG(MC_SEC_CARVEOUT_REG_CTRL) = params->mc_sec_carveout_protect_write_access; - MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = params->mc_mts_carveout_reg_ctrl; - MAKE_MC_REG(MC_EMEM_CFG_ACCESS_CTRL) = 1; /* Disable write access to a bunch of MC registers. */ + MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = params->McVideoProtectWriteAccess; + MAKE_MC_REG(MC_SEC_CARVEOUT_REG_CTRL) = params->McSecCarveoutProtectWriteAccess; + MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = params->McMtsCarveoutRegCtrl; + MAKE_MC_REG(MC_EMEM_CFG_ACCESS_CTRL) = 1; } -const void *sdram_get_params() -{ - /* TODO: sdram_id should be in [0, 7]. */ +static void sdram_config_mariko(const sdram_params_mariko_t *params) { + volatile tegra_car_t *car = car_get_regs(); + volatile tegra_pmc_t *pmc = pmc_get_regs(); + + if (params->EmcBctSpare0) { + *(volatile uint32_t *)params->EmcBctSpare0 = params->EmcBctSpare1; + } + + if (params->ClkRstControllerPllmMisc2OverrideEnable) { + car->pllm_misc2 = params->ClkRstControllerPllmMisc2Override; + } + + pmc->weak_bias = ((~params->EmcPmcScratch1 & 0x1000) << 19) | ((~params->EmcPmcScratch1 & 0xFFF) << 18) | ((~params->EmcPmcScratch1 & 0x8000) << 15); + pmc->io_dpd3_req = (~params->EmcPmcScratch1 & 0x9FFF) + 0x80000000; + udelay(params->PmcIoDpd3ReqWait); + pmc->io_dpd4_req = (~params->EmcPmcScratch2 & 0x3FFF0000) + 0x80000000; + udelay(params->PmcIoDpd4ReqWait); + pmc->io_dpd4_req = (~params->EmcPmcScratch2 & 0x1FFF) + 0x80000000; + udelay(1); + + MAKE_EMC_REG(EMC_FBIO_CFG7) = params->EmcFbioCfg7; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_0) = params->EmcCmdMappingCmd0_0; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_1) = params->EmcCmdMappingCmd0_1; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_2) = params->EmcCmdMappingCmd0_2; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_0) = params->EmcCmdMappingCmd1_0; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_1) = params->EmcCmdMappingCmd1_1; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_2) = params->EmcCmdMappingCmd1_2; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_0) = params->EmcCmdMappingCmd2_0; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_1) = params->EmcCmdMappingCmd2_1; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_2) = params->EmcCmdMappingCmd2_2; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_0) = params->EmcCmdMappingCmd3_0; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_1) = params->EmcCmdMappingCmd3_1; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_2) = params->EmcCmdMappingCmd3_2; + MAKE_EMC_REG(EMC_CMD_MAPPING_BYTE) = params->EmcCmdMappingByte; + MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_0) = params->EmcPmacroBrickMapping0; + MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_1) = params->EmcPmacroBrickMapping1; + MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_2) = params->EmcPmacroBrickMapping2; + MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_0) = params->EmcPmacroVttgenCtrl0; + MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_1) = params->EmcPmacroVttgenCtrl1; + MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_2) = params->EmcPmacroVttgenCtrl2; + MAKE_EMC_REG(EMC_PMACRO_BG_BIAS_CTRL_0) = params->EmcPmacroBgBiasCtrl0; + + if (params->EmcBctSpareSecure0) { + *(volatile uint32_t *)params->EmcBctSpareSecure0 = params->EmcBctSpareSecure1; + } + if (params->EmcBctSpareSecure2) { + *(volatile uint32_t *)params->EmcBctSpareSecure2 = params->EmcBctSpareSecure3; + } + if (params->EmcBctSpareSecure4) { + *(volatile uint32_t *)params->EmcBctSpareSecure4 = params->EmcBctSpareSecure5; + } + + MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; + udelay(params->PmcVddpSelWait + 2); + car->clk_source_emc = params->EmcClockSource; + car->clk_source_emc_dll = params->EmcClockSourceDll; + MAKE_EMC_REG(EMC_DBG) = params->EmcDbg | 2 * params->EmcDbgWriteMux; + + if (params->EmcBctSpare2) { + *(volatile uint32_t *)params->EmcBctSpare2 = params->EmcBctSpare3; + } + + MAKE_EMC_REG(EMC_CONFIG_SAMPLE_DELAY) = params->EmcConfigSampleDelay; + MAKE_EMC_REG(EMC_FBIO_CFG8) = params->EmcFbioCfg8; + MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE0) = params->EmcSwizzleRank0Byte0; + MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE1) = params->EmcSwizzleRank0Byte1; + MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE2) = params->EmcSwizzleRank0Byte2; + MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE3) = params->EmcSwizzleRank0Byte3; + MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE0) = params->EmcSwizzleRank1Byte0; + MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE1) = params->EmcSwizzleRank1Byte1; + MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE2) = params->EmcSwizzleRank1Byte2; + MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE3) = params->EmcSwizzleRank1Byte3; + + if (params->EmcBctSpare6) { + *(volatile uint32_t *)params->EmcBctSpare6 = params->EmcBctSpare7; + } + + MAKE_EMC_REG(EMC_XM2COMPPADCTRL) = params->EmcXm2CompPadCtrl; + MAKE_EMC_REG(EMC_XM2COMPPADCTRL2) = params->EmcXm2CompPadCtrl2; + MAKE_EMC_REG(EMC_XM2COMPPADCTRL3) = params->EmcXm2CompPadCtrl3; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG2) = params->EmcAutoCalConfig2; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG3) = params->EmcAutoCalConfig3; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG4) = params->EmcAutoCalConfig4; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG5) = params->EmcAutoCalConfig5; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG6) = params->EmcAutoCalConfig6; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG7) = params->EmcAutoCalConfig7; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG8) = params->EmcAutoCalConfig8; + MAKE_EMC_REG(EMC_PMACRO_RX_TERM) = params->EmcPmacroRxTerm; + MAKE_EMC_REG(EMC_PMACRO_DQ_TX_DRV) = params->EmcPmacroDqTxDrv; + MAKE_EMC_REG(EMC_PMACRO_CA_TX_DRV) = params->EmcPmacroCaTxDrv; + MAKE_EMC_REG(EMC_PMACRO_CMD_TX_DRV) = params->EmcPmacroCmdTxDrv; + MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_COMMON) = params->EmcPmacroAutocalCfgCommon; + MAKE_EMC_REG(EMC_AUTO_CAL_CHANNEL) = params->EmcAutoCalChannel; + MAKE_EMC_REG(EMC_PMACRO_ZCTRL) = params->EmcPmacroZctrl; + MAKE_EMC_REG(EMC_DLL_CFG_0) = params->EmcPmacroDllCfg0; + MAKE_EMC_REG(EMC_DLL_CFG_1) = params->EmcPmacroDllCfg1; + MAKE_EMC_REG(EMC_CFG_DIG_DLL_1) = params->EmcCfgDigDll_1; + MAKE_EMC_REG(EMC_DATA_BRLSHFT_0) = params->EmcDataBrlshft0; + MAKE_EMC_REG(EMC_DATA_BRLSHFT_1) = params->EmcDataBrlshft1; + MAKE_EMC_REG(EMC_DQS_BRLSHFT_0) = params->EmcDqsBrlshft0; + MAKE_EMC_REG(EMC_DQS_BRLSHFT_1) = params->EmcDqsBrlshft1; + MAKE_EMC_REG(EMC_CMD_BRLSHFT_0) = params->EmcCmdBrlshft0; + MAKE_EMC_REG(EMC_CMD_BRLSHFT_1) = params->EmcCmdBrlshft1; + MAKE_EMC_REG(EMC_CMD_BRLSHFT_2) = params->EmcCmdBrlshft2; + MAKE_EMC_REG(EMC_CMD_BRLSHFT_3) = params->EmcCmdBrlshft3; + MAKE_EMC_REG(EMC_QUSE_BRLSHFT_0) = params->EmcQuseBrlshft0; + MAKE_EMC_REG(EMC_QUSE_BRLSHFT_1) = params->EmcQuseBrlshft1; + MAKE_EMC_REG(EMC_QUSE_BRLSHFT_2) = params->EmcQuseBrlshft2; + MAKE_EMC_REG(EMC_QUSE_BRLSHFT_3) = params->EmcQuseBrlshft3; + MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = params->EmcPmacroBrickCtrlRfu1; + MAKE_EMC_REG(EMC_PMACRO_PAD_CFG_CTRL) = params->EmcPmacroPadCfgCtrl; + MAKE_EMC_REG(EMC_PMACRO_CMD_BRICK_CTRL_FDPD) = params->EmcPmacroCmdBrickCtrlFdpd; + MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU2) = params->EmcPmacroBrickCtrlRfu2; + MAKE_EMC_REG(EMC_PMACRO_DATA_BRICK_CTRL_FDPD) = params->EmcPmacroDataBrickCtrlFdpd; + MAKE_EMC_REG(EMC_PMACRO_DATA_PAD_RX_CTRL) = params->EmcPmacroDataPadRxCtrl; + MAKE_EMC_REG(EMC_PMACRO_CMD_PAD_RX_CTRL) = params->EmcPmacroCmdPadRxCtrl; + MAKE_EMC_REG(EMC_PMACRO_DATA_PAD_TX_CTRL) = params->EmcPmacroDataPadTxCtrl; + MAKE_EMC_REG(EMC_PMACRO_DATA_RX_TERM_MODE) = params->EmcPmacroDataRxTermMode; + MAKE_EMC_REG(EMC_PMACRO_CMD_RX_TERM_MODE) = params->EmcPmacroCmdRxTermMode; + MAKE_EMC_REG(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->EmcPmacroCmdPadTxCtrl & 0xEFFFFFFF; + MAKE_EMC_REG(EMC_CFG_3) = params->EmcCfg3; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_0) = params->EmcPmacroTxPwrd0; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_1) = params->EmcPmacroTxPwrd1; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_2) = params->EmcPmacroTxPwrd2; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_3) = params->EmcPmacroTxPwrd3; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_4) = params->EmcPmacroTxPwrd4; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_5) = params->EmcPmacroTxPwrd5; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_0) = params->EmcPmacroTxSelClkSrc0; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_1) = params->EmcPmacroTxSelClkSrc1; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_2) = params->EmcPmacroTxSelClkSrc2; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_3) = params->EmcPmacroTxSelClkSrc3; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_4) = params->EmcPmacroTxSelClkSrc4; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_5) = params->EmcPmacroTxSelClkSrc5; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_FGCG_CTRL_0) = params->EmcPmacroPerbitFgcgCtrl0; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_FGCG_CTRL_1) = params->EmcPmacroPerbitFgcgCtrl1; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_FGCG_CTRL_2) = params->EmcPmacroPerbitFgcgCtrl2; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_FGCG_CTRL_3) = params->EmcPmacroPerbitFgcgCtrl3; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_FGCG_CTRL_4) = params->EmcPmacroPerbitFgcgCtrl4; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_FGCG_CTRL_5) = params->EmcPmacroPerbitFgcgCtrl5; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU_CTRL_0) = params->EmcPmacroPerbitRfuCtrl0; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU_CTRL_1) = params->EmcPmacroPerbitRfuCtrl1; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU_CTRL_2) = params->EmcPmacroPerbitRfuCtrl2; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU_CTRL_3) = params->EmcPmacroPerbitRfuCtrl3; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU_CTRL_4) = params->EmcPmacroPerbitRfuCtrl4; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU_CTRL_5) = params->EmcPmacroPerbitRfuCtrl5; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU1_CTRL_0) = params->EmcPmacroPerbitRfu1Ctrl0; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU1_CTRL_1) = params->EmcPmacroPerbitRfu1Ctrl1; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU1_CTRL_2) = params->EmcPmacroPerbitRfu1Ctrl2; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU1_CTRL_3) = params->EmcPmacroPerbitRfu1Ctrl3; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU1_CTRL_4) = params->EmcPmacroPerbitRfu1Ctrl4; + MAKE_EMC_REG(EMC_PMACRO_PERBIT_RFU1_CTRL_5) = params->EmcPmacroPerbitRfu1Ctrl5; + MAKE_EMC_REG(EMC_PMACRO_DATA_PI_CTRL) = params->EmcPmacroDataPiCtrl; + MAKE_EMC_REG(EMC_PMACRO_CMD_PI_CTRL) = params->EmcPmacroCmdPiCtrl; + MAKE_EMC_REG(EMC_PMACRO_DDLL_BYPASS) = params->EmcPmacroDdllBypass; + MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_0) = params->EmcPmacroDdllPwrd0; + MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_1) = params->EmcPmacroDdllPwrd1; + MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_2) = params->EmcPmacroDdllPwrd2; + MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_0) = params->EmcPmacroCmdCtrl0; + MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_1) = params->EmcPmacroCmdCtrl1; + MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_2) = params->EmcPmacroCmdCtrl2; + MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQ_0) = params->EmcPmacroIbVrefDq_0; + MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQ_1) = params->EmcPmacroIbVrefDq_1; + MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQS_0) = params->EmcPmacroIbVrefDqs_0; + MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQS_1) = params->EmcPmacroIbVrefDqs_1; + MAKE_EMC_REG(EMC_PMACRO_IB_RXRT) = params->EmcPmacroIbRxrt; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_0) = params->EmcPmacroQuseDdllRank0_0; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_1) = params->EmcPmacroQuseDdllRank0_1; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_2) = params->EmcPmacroQuseDdllRank0_2; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_3) = params->EmcPmacroQuseDdllRank0_3; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_4) = params->EmcPmacroQuseDdllRank0_4; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_5) = params->EmcPmacroQuseDdllRank0_5; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_0) = params->EmcPmacroQuseDdllRank1_0; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_1) = params->EmcPmacroQuseDdllRank1_1; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_2) = params->EmcPmacroQuseDdllRank1_2; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_3) = params->EmcPmacroQuseDdllRank1_3; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_4) = params->EmcPmacroQuseDdllRank1_4; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_5) = params->EmcPmacroQuseDdllRank1_5; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0) = params->EmcPmacroObDdllLongDqRank0_0; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1) = params->EmcPmacroObDdllLongDqRank0_1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2) = params->EmcPmacroObDdllLongDqRank0_2; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3) = params->EmcPmacroObDdllLongDqRank0_3; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4) = params->EmcPmacroObDdllLongDqRank0_4; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5) = params->EmcPmacroObDdllLongDqRank0_5; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0) = params->EmcPmacroObDdllLongDqRank1_0; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1) = params->EmcPmacroObDdllLongDqRank1_1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2) = params->EmcPmacroObDdllLongDqRank1_2; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3) = params->EmcPmacroObDdllLongDqRank1_3; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4) = params->EmcPmacroObDdllLongDqRank1_4; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5) = params->EmcPmacroObDdllLongDqRank1_5; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0) = params->EmcPmacroObDdllLongDqsRank0_0; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1) = params->EmcPmacroObDdllLongDqsRank0_1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2) = params->EmcPmacroObDdllLongDqsRank0_2; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3) = params->EmcPmacroObDdllLongDqsRank0_3; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4) = params->EmcPmacroObDdllLongDqsRank0_4; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5) = params->EmcPmacroObDdllLongDqsRank0_5; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0) = params->EmcPmacroObDdllLongDqsRank1_0; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1) = params->EmcPmacroObDdllLongDqsRank1_1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2) = params->EmcPmacroObDdllLongDqsRank1_2; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3) = params->EmcPmacroObDdllLongDqsRank1_3; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4) = params->EmcPmacroObDdllLongDqsRank1_4; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5) = params->EmcPmacroObDdllLongDqsRank1_5; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0) = params->EmcPmacroIbDdllLongDqsRank0_0; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1) = params->EmcPmacroIbDdllLongDqsRank0_1; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2) = params->EmcPmacroIbDdllLongDqsRank0_2; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3) = params->EmcPmacroIbDdllLongDqsRank0_3; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0) = params->EmcPmacroIbDdllLongDqsRank1_0; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1) = params->EmcPmacroIbDdllLongDqsRank1_1; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2) = params->EmcPmacroIbDdllLongDqsRank1_2; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3) = params->EmcPmacroIbDdllLongDqsRank1_3; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_0) = params->EmcPmacroDdllLongCmd_0; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_1) = params->EmcPmacroDdllLongCmd_1; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_2) = params->EmcPmacroDdllLongCmd_2; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_3) = params->EmcPmacroDdllLongCmd_3; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_4) = params->EmcPmacroDdllLongCmd_4; + MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_0) = params->EmcPmacroDdllShortCmd_0; + MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_1) = params->EmcPmacroDdllShortCmd_1; + MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_2) = params->EmcPmacroDdllShortCmd_2; + MAKE_EMC_REG(EMC_PMACRO_DDLL_PERIODIC_OFFSET) = params->EmcPmacroDdllPeriodicOffset; + + if (params->EmcBctSpare4) { + *(volatile uint32_t *)params->EmcBctSpare4 = params->EmcBctSpare5; + } + if (params->EmcBctSpareSecure6) { + *(volatile uint32_t *)params->EmcBctSpareSecure6 = params->EmcBctSpareSecure7; + } + if (params->EmcBctSpareSecure8) { + *(volatile uint32_t *)params->EmcBctSpareSecure8 = params->EmcBctSpareSecure9; + } + if (params->EmcBctSpareSecure10) { + *(volatile uint32_t *)params->EmcBctSpareSecure10 = params->EmcBctSpareSecure11; + } + + MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; + + MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = params->McVideoProtectBom; + MAKE_MC_REG(MC_VIDEO_PROTECT_BOM_ADR_HI) = params->McVideoProtectBomAdrHi; + MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = params->McVideoProtectSizeMb; + MAKE_MC_REG(MC_VIDEO_PROTECT_VPR_OVERRIDE) = params->McVideoProtectVprOverride; + MAKE_MC_REG(MC_VIDEO_PROTECT_VPR_OVERRIDE1) = params->McVideoProtectVprOverride1; + MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = params->McVideoProtectGpuOverride0; + MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = params->McVideoProtectGpuOverride1; + MAKE_MC_REG(MC_EMEM_ADR_CFG) = params->McEmemAdrCfg; + MAKE_MC_REG(MC_EMEM_ADR_CFG_DEV0) = params->McEmemAdrCfgDev0; + MAKE_MC_REG(MC_EMEM_ADR_CFG_DEV1) = params->McEmemAdrCfgDev1; + MAKE_MC_REG(MC_EMEM_ADR_CFG_CHANNEL_MASK) = params->McEmemAdrCfgChannelMask; + MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_0) = params->McEmemAdrCfgBankMask0; + MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_1) = params->McEmemAdrCfgBankMask1; + MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_2) = params->McEmemAdrCfgBankMask2; + MAKE_MC_REG(MC_EMEM_CFG) = params->McEmemCfg; + MAKE_MC_REG(MC_SEC_CARVEOUT_BOM) = params->McSecCarveoutBom; + MAKE_MC_REG(MC_SEC_CARVEOUT_ADR_HI) = params->McSecCarveoutAdrHi; + MAKE_MC_REG(MC_SEC_CARVEOUT_SIZE_MB) = params->McSecCarveoutSizeMb; + MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = params->McMtsCarveoutBom; + MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = params->McMtsCarveoutAdrHi; + MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = params->McMtsCarveoutSizeMb; + MAKE_MC_REG(MC_EMEM_ARB_CFG) = params->McEmemArbCfg; + MAKE_MC_REG(MC_EMEM_ARB_OUTSTANDING_REQ) = params->McEmemArbOutstandingReq; + MAKE_MC_REG(MC_EMEM_ARB_REFPB_HP_CTRL) = params->McEmemArbRefpbHpCtrl; + MAKE_MC_REG(MC_EMEM_ARB_REFPB_BANK_CTRL) = params->McEmemArbRefpbBankCtrl; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RCD) = params->McEmemArbTimingRcd; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RP) = params->McEmemArbTimingRp; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RC) = params->McEmemArbTimingRc; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RAS) = params->McEmemArbTimingRas; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_FAW) = params->McEmemArbTimingFaw; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RRD) = params->McEmemArbTimingRrd; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RAP2PRE) = params->McEmemArbTimingRap2Pre; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_WAP2PRE) = params->McEmemArbTimingWap2Pre; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_R2R) = params->McEmemArbTimingR2R; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_W2W) = params->McEmemArbTimingW2W; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_CCDMW) = params->McEmemArbTimingCcdmw; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_R2W) = params->McEmemArbTimingR2W; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_W2R) = params->McEmemArbTimingW2R; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RFCPB) = params->McEmemArbTimingRFCPB; + MAKE_MC_REG(MC_EMEM_ARB_DA_TURNS) = params->McEmemArbDaTurns; + MAKE_MC_REG(MC_EMEM_ARB_DA_COVERS) = params->McEmemArbDaCovers; + MAKE_MC_REG(MC_EMEM_ARB_MISC0) = params->McEmemArbMisc0; + MAKE_MC_REG(MC_EMEM_ARB_MISC1) = params->McEmemArbMisc1; + MAKE_MC_REG(MC_EMEM_ARB_MISC2) = params->McEmemArbMisc2; + MAKE_MC_REG(MC_EMEM_ARB_RING1_THROTTLE) = params->McEmemArbRing1Throttle; + MAKE_MC_REG(MC_EMEM_ARB_OVERRIDE) = params->McEmemArbOverride; + MAKE_MC_REG(MC_EMEM_ARB_OVERRIDE_1) = params->McEmemArbOverride1; + MAKE_MC_REG(MC_EMEM_ARB_RSV) = params->McEmemArbRsv; + MAKE_MC_REG(MC_DA_CONFIG0) = params->McDaCfg0; + MAKE_MC_REG(MC_TIMING_CONTROL) = 1; + MAKE_MC_REG(MC_CLKEN_OVERRIDE) = params->McClkenOverride; + MAKE_MC_REG(MC_STAT_CONTROL) = params->McStatControl; + + MAKE_EMC_REG(EMC_ADR_CFG) = params->EmcAdrCfg; + MAKE_EMC_REG(EMC_CLKEN_OVERRIDE) = params->EmcClkenOverride; + MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_0) = params->EmcPmacroAutocalCfg0; + MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_1) = params->EmcPmacroAutocalCfg1; + MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_2) = params->EmcPmacroAutocalCfg2; + MAKE_EMC_REG(EMC_AUTO_CAL_VREF_SEL_0) = params->EmcAutoCalVrefSel0; + MAKE_EMC_REG(EMC_AUTO_CAL_VREF_SEL_1) = params->EmcAutoCalVrefSel1; + MAKE_EMC_REG(EMC_AUTO_CAL_INTERVAL) = params->EmcAutoCalInterval; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG) = params->EmcAutoCalConfig; + udelay(params->EmcAutoCalWait); + + if (params->EmcBctSpare8) { + *(volatile uint32_t *)params->EmcBctSpare8 = params->EmcBctSpare9; + } + + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG9) = params->EmcAutoCalConfig9; + MAKE_EMC_REG(EMC_CFG_2) = params->EmcCfg2; + MAKE_EMC_REG(EMC_CFG_PIPE) = params->EmcCfgPipe; + MAKE_EMC_REG(EMC_CFG_PIPE_1) = params->EmcCfgPipe1; + MAKE_EMC_REG(EMC_CFG_PIPE_2) = params->EmcCfgPipe2; + MAKE_EMC_REG(EMC_CMDQ) = params->EmcCmdQ; + MAKE_EMC_REG(EMC_MC2EMCQ) = params->EmcMc2EmcQ; + MAKE_EMC_REG(EMC_MRS_WAIT_CNT) = params->EmcMrsWaitCnt; + MAKE_EMC_REG(EMC_MRS_WAIT_CNT2) = params->EmcMrsWaitCnt2; + MAKE_EMC_REG(EMC_FBIO_CFG5) = params->EmcFbioCfg5; + MAKE_EMC_REG(EMC_RC) = params->EmcRc; + MAKE_EMC_REG(EMC_RFC) = params->EmcRfc; + MAKE_EMC_REG(EMC_RFCPB) = params->EmcRfcPb; + MAKE_EMC_REG(EMC_REFCTRL2) = params->EmcRefctrl2; + MAKE_EMC_REG(EMC_RFC_SLR) = params->EmcRfcSlr; + MAKE_EMC_REG(EMC_RAS) = params->EmcRas; + MAKE_EMC_REG(EMC_RP) = params->EmcRp; + MAKE_EMC_REG(EMC_TPPD) = params->EmcTppd; + MAKE_EMC_REG(EMC_TRTM) = params->EmcTrtm; + MAKE_EMC_REG(EMC_TWTM) = params->EmcTwtm; + MAKE_EMC_REG(EMC_TRATM) = params->EmcTratm; + MAKE_EMC_REG(EMC_TWATM) = params->EmcTwatm; + MAKE_EMC_REG(EMC_TR2REF) = params->EmcTr2ref; + MAKE_EMC_REG(EMC_R2R) = params->EmcR2r; + MAKE_EMC_REG(EMC_W2W) = params->EmcW2w; + MAKE_EMC_REG(EMC_R2W) = params->EmcR2w; + MAKE_EMC_REG(EMC_W2R) = params->EmcW2r; + MAKE_EMC_REG(EMC_R2P) = params->EmcR2p; + MAKE_EMC_REG(EMC_W2P) = params->EmcW2p; + MAKE_EMC_REG(EMC_CCDMW) = params->EmcCcdmw; + MAKE_EMC_REG(EMC_RD_RCD) = params->EmcRdRcd; + MAKE_EMC_REG(EMC_WR_RCD) = params->EmcWrRcd; + MAKE_EMC_REG(EMC_RRD) = params->EmcRrd; + MAKE_EMC_REG(EMC_REXT) = params->EmcRext; + MAKE_EMC_REG(EMC_WEXT) = params->EmcWext; + MAKE_EMC_REG(EMC_WDV) = params->EmcWdv; + MAKE_EMC_REG(EMC_WDV_CHK) = params->EmcWdvChk; + MAKE_EMC_REG(EMC_WSV) = params->EmcWsv; + MAKE_EMC_REG(EMC_WEV) = params->EmcWev; + MAKE_EMC_REG(EMC_WDV_MASK) = params->EmcWdvMask; + MAKE_EMC_REG(EMC_WS_DURATION) = params->EmcWsDuration; + MAKE_EMC_REG(EMC_WE_DURATION) = params->EmcWeDuration; + MAKE_EMC_REG(EMC_QUSE) = params->EmcQUse; + MAKE_EMC_REG(EMC_QUSE_WIDTH) = params->EmcQuseWidth; + MAKE_EMC_REG(EMC_IBDLY) = params->EmcIbdly; + MAKE_EMC_REG(EMC_OBDLY) = params->EmcObdly; + MAKE_EMC_REG(EMC_EINPUT) = params->EmcEInput; + MAKE_EMC_REG(EMC_EINPUT_DURATION) = params->EmcEInputDuration; + MAKE_EMC_REG(EMC_PUTERM_EXTRA) = params->EmcPutermExtra; + MAKE_EMC_REG(EMC_PUTERM_WIDTH) = params->EmcPutermWidth; + MAKE_EMC_REG(EMC_DBG) = params->EmcDbg; + MAKE_EMC_REG(EMC_QRST) = params->EmcQRst; + MAKE_EMC_REG(EMC_ISSUE_QRST) = 0; + MAKE_EMC_REG(EMC_QSAFE) = params->EmcQSafe; + MAKE_EMC_REG(EMC_RDV) = params->EmcRdv; + MAKE_EMC_REG(EMC_RDV_MASK) = params->EmcRdvMask; + MAKE_EMC_REG(EMC_RDV_EARLY) = params->EmcRdvEarly; + MAKE_EMC_REG(EMC_RDV_EARLY_MASK) = params->EmcRdvEarlyMask; + MAKE_EMC_REG(EMC_QPOP) = params->EmcQpop; + MAKE_EMC_REG(EMC_REFRESH) = params->EmcRefresh; + MAKE_EMC_REG(EMC_BURST_REFRESH_NUM) = params->EmcBurstRefreshNum; + MAKE_EMC_REG(EMC_PRE_REFRESH_REQ_CNT) = params->EmcPreRefreshReqCnt; + MAKE_EMC_REG(EMC_PDEX2WR) = params->EmcPdEx2Wr; + MAKE_EMC_REG(EMC_PDEX2RD) = params->EmcPdEx2Rd; + MAKE_EMC_REG(EMC_PCHG2PDEN) = params->EmcPChg2Pden; + MAKE_EMC_REG(EMC_ACT2PDEN) = params->EmcAct2Pden; + MAKE_EMC_REG(EMC_AR2PDEN) = params->EmcAr2Pden; + MAKE_EMC_REG(EMC_RW2PDEN) = params->EmcRw2Pden; + MAKE_EMC_REG(EMC_CKE2PDEN) = params->EmcCke2Pden; + MAKE_EMC_REG(EMC_PDEX2CKE) = params->EmcPdex2Cke; + MAKE_EMC_REG(EMC_PDEX2MRR) = params->EmcPdex2Mrr; + MAKE_EMC_REG(EMC_TXSR) = params->EmcTxsr; + MAKE_EMC_REG(EMC_TXSRDLL) = params->EmcTxsrDll; + MAKE_EMC_REG(EMC_TCKE) = params->EmcTcke; + MAKE_EMC_REG(EMC_TCKESR) = params->EmcTckesr; + MAKE_EMC_REG(EMC_TPD) = params->EmcTpd; + MAKE_EMC_REG(EMC_TFAW) = params->EmcTfaw; + MAKE_EMC_REG(EMC_TRPAB) = params->EmcTrpab; + MAKE_EMC_REG(EMC_TCLKSTABLE) = params->EmcTClkStable; + MAKE_EMC_REG(EMC_TCLKSTOP) = params->EmcTClkStop; + MAKE_EMC_REG(EMC_TREFBW) = params->EmcTRefBw; + MAKE_EMC_REG(EMC_ODT_WRITE) = params->EmcOdtWrite; + MAKE_EMC_REG(EMC_CFG_DIG_DLL) = params->EmcCfgDigDll; + MAKE_EMC_REG(EMC_CFG_DIG_DLL_PERIOD) = params->EmcCfgDigDllPeriod; + MAKE_EMC_REG(EMC_FBIO_SPARE) = params->EmcFbioSpare & 0xFFFFFFFD; + MAKE_EMC_REG(EMC_CFG_RSV) = params->EmcCfgRsv; + MAKE_EMC_REG(EMC_PMC_SCRATCH1) = params->EmcPmcScratch1; + MAKE_EMC_REG(EMC_PMC_SCRATCH2) = params->EmcPmcScratch2; + MAKE_EMC_REG(EMC_PMC_SCRATCH3) = params->EmcPmcScratch3; + MAKE_EMC_REG(EMC_ACPD_CONTROL) = params->EmcAcpdControl; + MAKE_EMC_REG(EMC_TXDSRVTTGEN) = params->EmcTxdsrvttgen; + MAKE_EMC_REG(EMC_PMACRO_DSR_VTTGEN_CTRL_0) = params->EmcPmacroDsrVttgenCtrl0; + MAKE_EMC_REG(EMC_CFG) = ((((((params->EmcCfg & 4) | 0x3C00000) & 0xFFFFFFF7) | (params->EmcCfg & 8)) & 0xFFFFFFFD) | (params->EmcCfg & 2)); + + if (params->BootRomPatchControl) { + *(volatile uint32_t *)params->BootRomPatchControl = params->BootRomPatchData; + MAKE_MC_REG(MC_TIMING_CONTROL) = 1; + } + + if (params->EmcBctSpareSecure12) { + *(volatile uint32_t *)params->EmcBctSpareSecure12 = params->EmcBctSpareSecure13; + } + if (params->EmcBctSpareSecure14) { + *(volatile uint32_t *)params->EmcBctSpareSecure14 = params->EmcBctSpareSecure15; + } + if (params->EmcBctSpareSecure16) { + *(volatile uint32_t *)params->EmcBctSpareSecure16 = params->EmcBctSpareSecure17; + } + + pmc->io_dpd3_req = ((4 * params->EmcPmcScratch1 >> 2) + 0x40000000) & 0xCFFF0000; + udelay(params->PmcIoDpd3ReqWait); + MAKE_EMC_REG(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->EmcPmacroCmdPadTxCtrl; + + if (params->EmcZcalWarmColdBootEnables & 1) { + if (params->MemoryType == NvBootMemoryType_Ddr3) { + MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = 8 * params->EmcZcalWaitCnt; + } else if (params->MemoryType == NvBootMemoryType_LpDdr4) { + MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = params->EmcZcalWaitCnt; + MAKE_EMC_REG(EMC_ZCAL_MRW_CMD) = params->EmcZcalMrwCmd; + } + } + + MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; + udelay(params->EmcTimingControlWait); + + pmc->ddr_cntrl &= 0xFF78007F; + udelay(params->PmcDdrCntrlWait); + + MAKE_EMC_REG(EMC_PIN) = (params->EmcPinGpioEn << 16) | (params->EmcPinGpio << 12); + udelay(params->EmcPinExtraWait + 200); + MAKE_EMC_REG(EMC_PIN) = ((params->EmcPinGpioEn << 16) | (params->EmcPinGpio << 12)) + 256; + + if (params->MemoryType == NvBootMemoryType_Ddr3) { + udelay(params->EmcPinExtraWait + 500); + } else if (params->MemoryType == NvBootMemoryType_LpDdr4) { + udelay(params->EmcPinExtraWait + 2000); + } + + MAKE_EMC_REG(EMC_PIN) = ((params->EmcPinGpioEn << 16) | (params->EmcPinGpio << 12)) + 257; + udelay(params->EmcPinProgramWait); + + if (params->MemoryType != NvBootMemoryType_LpDdr4) { + MAKE_EMC_REG(EMC_NOP) = (params->EmcDevSelect << 30) + 1; + if (params->MemoryType == NvBootMemoryType_LpDdr2) { + udelay(params->EmcPinExtraWait + 200); + } + } else { + if (params->EmcBctSpare10) { + *(volatile uint32_t *)params->EmcBctSpare10 = params->EmcBctSpare11; + } + + MAKE_EMC_REG(EMC_MRW2) = params->EmcMrw2; + MAKE_EMC_REG(EMC_MRW) = params->EmcMrw1; + MAKE_EMC_REG(EMC_MRW3) = params->EmcMrw3; + MAKE_EMC_REG(EMC_MRW4) = params->EmcMrw4; + MAKE_EMC_REG(EMC_MRW6) = params->EmcMrw6; + MAKE_EMC_REG(EMC_MRW14) = params->EmcMrw14; + MAKE_EMC_REG(EMC_MRW8) = params->EmcMrw8; + MAKE_EMC_REG(EMC_MRW12) = params->EmcMrw12; + MAKE_EMC_REG(EMC_MRW9) = params->EmcMrw9; + MAKE_EMC_REG(EMC_MRW13) = params->EmcMrw13; + + if (params->EmcZcalWarmColdBootEnables & 1) { + MAKE_EMC_REG(EMC_ZQ_CAL) = params->EmcZcalInitDev0; + udelay(params->EmcZcalInitWait); + MAKE_EMC_REG(EMC_ZQ_CAL) = params->EmcZcalInitDev0 ^ 3; + + if (!(params->EmcDevSelect & 2)) { + MAKE_EMC_REG(EMC_ZQ_CAL) = params->EmcZcalInitDev1; + udelay(params->EmcZcalInitWait); + MAKE_EMC_REG(EMC_ZQ_CAL) = params->EmcZcalInitDev1 ^ 3; + } + } + } + + if (params->EmcBctSpareSecure18) { + *(volatile uint32_t *)params->EmcBctSpareSecure18 = params->EmcBctSpareSecure19; + } + if (params->EmcBctSpareSecure20) { + *(volatile uint32_t *)params->EmcBctSpareSecure20 = params->EmcBctSpareSecure21; + } + if (params->EmcBctSpareSecure22) { + *(volatile uint32_t *)params->EmcBctSpareSecure22 = params->EmcBctSpareSecure23; + } + + pmc->ddr_cfg = params->PmcDdrCfg; + if ((params->MemoryType == NvBootMemoryType_LpDdr2) + || (params->MemoryType == NvBootMemoryType_Ddr3) + || (params->MemoryType == NvBootMemoryType_LpDdr4)) { + MAKE_EMC_REG(EMC_ZCAL_INTERVAL) = params->EmcZcalInterval; + MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = params->EmcZcalWaitCnt; + MAKE_EMC_REG(EMC_ZCAL_MRW_CMD) = params->EmcZcalMrwCmd; + } + + if (params->EmcBctSpare12) { + *(volatile uint32_t *)params->EmcBctSpare12 = params->EmcBctSpare13; + } + + MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; + + if (params->EmcExtraRefreshNum) { + MAKE_EMC_REG(EMC_REF) = ((1 << params->EmcExtraRefreshNum << 8) - 253) | (params->EmcDevSelect << 30); + } + + MAKE_EMC_REG(EMC_REFCTRL) = params->EmcDevSelect | 0x80000000; + MAKE_EMC_REG(EMC_DYN_SELF_REF_CONTROL) = params->EmcDynSelfRefControl; + MAKE_EMC_REG(EMC_CFG) = params->EmcCfg; + MAKE_EMC_REG(EMC_FDPD_CTRL_DQ) = params->EmcFdpdCtrlDq; + MAKE_EMC_REG(EMC_FDPD_CTRL_CMD) = params->EmcFdpdCtrlCmd; + MAKE_EMC_REG(EMC_SEL_DPD_CTRL) = params->EmcSelDpdCtrl; + MAKE_EMC_REG(EMC_FBIO_SPARE) = params->EmcFbioSpare | 2; + MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; + MAKE_EMC_REG(EMC_CFG_UPDATE) = params->EmcCfgUpdate; + MAKE_EMC_REG(EMC_CFG_PIPE_CLK) = params->EmcCfgPipeClk; + MAKE_EMC_REG(EMC_FDPD_CTRL_CMD_NO_RAMP) = params->EmcFdpdCtrlCmdNoRamp; + MAKE_MC_REG(MC_UNTRANSLATED_REGION_CHECK) = params->McUntranslatedRegionCheck; + MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = params->McVideoProtectWriteAccess; + MAKE_MC_REG(MC_SEC_CARVEOUT_REG_CTRL) = params->McSecCarveoutProtectWriteAccess; + MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = params->McMtsCarveoutRegCtrl; + MAKE_MC_REG(MC_EMEM_CFG_ACCESS_CTRL) = 1; + + AHB_ARBITRATION_XBAR_CTRL_0 = ((AHB_ARBITRATION_XBAR_CTRL_0 & 0xFFFEFFFF) | ((params->AhbArbitrationXbarCtrlMemInitDone & 0xFFFF) << 16)); +} -#ifdef CONFIG_SDRAM_COMPRESS_CFG +const void *sdram_get_params_erista(uint32_t dram_id) { + uint32_t sdram_params_index = sdram_params_index_table_erista[dram_id]; +#ifdef CONFIG_SDRAM_COMPRESS uint8_t *buf = (uint8_t *)0x40030000; - LZ_Uncompress(_dram_cfg_lz, buf, sizeof(_dram_cfg_lz)); - return (const void *)&buf[sizeof(sdram_params_t) * _get_sdram_id()]; + LZ_Uncompress(sdram_params_erista_lz, buf, sizeof(sdram_params_erista_lz)); + return (const void *)&buf[sizeof(sdram_params_erista_t) * sdram_params_index]; #else - return _dram_cfgs[_get_sdram_id()]; + return sdram_params_erista[sdram_params_index]; #endif } -void sdram_init() -{ - volatile tegra_pmc_t *pmc = pmc_get_regs(); - - /* TODO: sdram_id should be in [0,4]. */ - const sdram_params_t *params = (const sdram_params_t *)sdram_get_params(); +const void *sdram_get_params_mariko(uint32_t dram_id) { + uint32_t sdram_params_index = sdram_params_index_table_mariko[dram_id]; +#ifdef CONFIG_SDRAM_COMPRESS + uint8_t *buf = (uint8_t *)0x40030000; + LZ_Uncompress(sdram_params_mariko_lz, buf, sizeof(sdram_params_mariko_lz)); + return (const void *)&buf[sizeof(sdram_params_mariko_t) * sdram_params_index]; +#else + return sdram_params_mariko[sdram_params_index]; +#endif +} +void sdram_init_erista(void) { + volatile tegra_pmc_t *pmc = pmc_get_regs(); + const sdram_params_erista_t *params = (const sdram_params_erista_t *)sdram_get_params_erista(fuse_get_dram_id()); + + /* Enable VddMemory. */ uint8_t val = 5; i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD_CFG2, &val, 1); val = 40; /* 40 = (1000 * 1100 - 600000) / 12500 -> 1.1V */ i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD1, &val, 1); - pmc->vddp_sel = params->pmc_vddp_sel; - udelay(params->pmc_vddp_sel_wait); - + pmc->vddp_sel = params->PmcVddpSel; + udelay(params->PmcVddpSelWait); pmc->ddr_pwr = pmc->ddr_pwr; - pmc->no_iopower = params->pmc_no_io_power; - pmc->reg_short = params->pmc_reg_short; - pmc->ddr_cntrl = params->pmc_ddr_ctrl; + pmc->no_iopower = params->PmcNoIoPower; + pmc->reg_short = params->PmcRegShort; + pmc->ddr_cntrl = params->PmcDdrCntrl; - if (params->emc_bct_spare0) - *(volatile uint32_t *)params->emc_bct_spare0 = params->emc_bct_spare1; - - _sdram_config(params); + if (params->EmcBctSpare0) { + *(volatile uint32_t *)params->EmcBctSpare0 = params->EmcBctSpare1; + } + + sdram_config_erista(params); } + +void sdram_init_mariko(void) { + volatile tegra_pmc_t *pmc = pmc_get_regs(); + const sdram_params_mariko_t *params = (const sdram_params_mariko_t *)sdram_get_params_mariko(fuse_get_dram_id()); + + /* Enable VddMemory. */ + uint8_t val = 5; + i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD_CFG2, &val, 1); + + pmc->vddp_sel = params->PmcVddpSel; + udelay(params->PmcVddpSelWait); + pmc->no_iopower = params->PmcNoIoPower; + pmc->reg_short = params->PmcRegShort; + pmc->ddr_cntrl = params->PmcDdrCntrl; + + if (params->EmcBctSpare0) { + *(volatile uint32_t *)params->EmcBctSpare0 = params->EmcBctSpare1; + } + + sdram_config_mariko(params); +} + +void sdram_save_params_erista(const void *save_params) { + const sdram_params_erista_t *params = (const sdram_params_erista_t *)save_params; + volatile tegra_pmc_t *pmc = pmc_get_regs(); + +#define pack(src, src_bits, dst, dst_bits) { \ + uint32_t mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \ + dst &= ~(mask << (0 ? dst_bits)); \ + dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \ +} + +#define s(param, src_bits, pmcreg, dst_bits) \ + pack(params->param, src_bits, pmc->pmcreg, dst_bits) + +#define c(value, pmcreg, dst_bits) \ + pack(value, (1 ? dst_bits) - (0 ? dst_bits) : 0, pmc->pmcreg, dst_bits) + +/* 32 bits version of s macro */ +#define s32(param, pmcreg) pmc->pmcreg = params->param + +/* 32 bits version c macro */ +#define c32(value, pmcreg) pmc->pmcreg = value + + //TODO: pkg1.1 (1.X - 3.X) reads them from MC. + // Patch carveout parameters. + /*params->McGeneralizedCarveout1Bom = 0; + params->McGeneralizedCarveout1BomHi = 0; + params->McGeneralizedCarveout1Size128kb = 0; + params->McGeneralizedCarveout1Access0 = 0; + params->McGeneralizedCarveout1Access1 = 0; + params->McGeneralizedCarveout1Access2 = 0; + params->McGeneralizedCarveout1Access3 = 0; + params->McGeneralizedCarveout1Access4 = 0; + params->McGeneralizedCarveout1ForceInternalAccess0 = 0; + params->McGeneralizedCarveout1ForceInternalAccess1 = 0; + params->McGeneralizedCarveout1ForceInternalAccess2 = 0; + params->McGeneralizedCarveout1ForceInternalAccess3 = 0; + params->McGeneralizedCarveout1ForceInternalAccess4 = 0; + params->McGeneralizedCarveout1Cfg0 = 0; + params->McGeneralizedCarveout2Bom = 0x80020000; + params->McGeneralizedCarveout2BomHi = 0; + params->McGeneralizedCarveout2Size128kb = 2; + params->McGeneralizedCarveout2Access0 = 0; + params->McGeneralizedCarveout2Access1 = 0; + params->McGeneralizedCarveout2Access2 = 0x3000000; + params->McGeneralizedCarveout2Access3 = 0; + params->McGeneralizedCarveout2Access4 = 0x300; + params->McGeneralizedCarveout2ForceInternalAccess0 = 0; + params->McGeneralizedCarveout2ForceInternalAccess1 = 0; + params->McGeneralizedCarveout2ForceInternalAccess2 = 0; + params->McGeneralizedCarveout2ForceInternalAccess3 = 0; + params->McGeneralizedCarveout2ForceInternalAccess4 = 0; + params->McGeneralizedCarveout2Cfg0 = 0x440167E; + params->McGeneralizedCarveout3Bom = 0; + params->McGeneralizedCarveout3BomHi = 0; + params->McGeneralizedCarveout3Size128kb = 0; + params->McGeneralizedCarveout3Access0 = 0; + params->McGeneralizedCarveout3Access1 = 0; + params->McGeneralizedCarveout3Access2 = 0x3000000; + params->McGeneralizedCarveout3Access3 = 0; + params->McGeneralizedCarveout3Access4 = 0x300; + params->McGeneralizedCarveout3ForceInternalAccess0 = 0; + params->McGeneralizedCarveout3ForceInternalAccess1 = 0; + params->McGeneralizedCarveout3ForceInternalAccess2 = 0; + params->McGeneralizedCarveout3ForceInternalAccess3 = 0; + params->McGeneralizedCarveout3ForceInternalAccess4 = 0; + params->McGeneralizedCarveout3Cfg0 = 0x4401E7E; + params->McGeneralizedCarveout4Bom = 0; + params->McGeneralizedCarveout4BomHi = 0; + params->McGeneralizedCarveout4Size128kb = 0; + params->McGeneralizedCarveout4Access0 = 0; + params->McGeneralizedCarveout4Access1 = 0; + params->McGeneralizedCarveout4Access2 = 0; + params->McGeneralizedCarveout4Access3 = 0; + params->McGeneralizedCarveout4Access4 = 0; + params->McGeneralizedCarveout4ForceInternalAccess0 = 0; + params->McGeneralizedCarveout4ForceInternalAccess1 = 0; + params->McGeneralizedCarveout4ForceInternalAccess2 = 0; + params->McGeneralizedCarveout4ForceInternalAccess3 = 0; + params->McGeneralizedCarveout4ForceInternalAccess4 = 0; + params->McGeneralizedCarveout4Cfg0 = 0x8F; + params->McGeneralizedCarveout5Bom = 0; + params->McGeneralizedCarveout5BomHi = 0; + params->McGeneralizedCarveout5Size128kb = 0; + params->McGeneralizedCarveout5Access0 = 0; + params->McGeneralizedCarveout5Access1 = 0; + params->McGeneralizedCarveout5Access2 = 0; + params->McGeneralizedCarveout5Access3 = 0; + params->McGeneralizedCarveout5Access4 = 0; + params->McGeneralizedCarveout5ForceInternalAccess0 = 0; + params->McGeneralizedCarveout5ForceInternalAccess1 = 0; + params->McGeneralizedCarveout5ForceInternalAccess2 = 0; + params->McGeneralizedCarveout5ForceInternalAccess3 = 0; + params->McGeneralizedCarveout5ForceInternalAccess4 = 0; + params->McGeneralizedCarveout5Cfg0 = 0x8F;*/ + + //TODO: this is 4.X+ behaviour which seems to work fine for < 4.X. + // Patch carveout parameters. + *(volatile uint32_t *)params->McGeneralizedCarveout1Cfg0 = 0; + *(volatile uint32_t *)params->McGeneralizedCarveout2Cfg0 = 0; + *(volatile uint32_t *)params->McGeneralizedCarveout3Cfg0 = 0; + *(volatile uint32_t *)params->McGeneralizedCarveout4Cfg0 = 0; + *(volatile uint32_t *)params->McGeneralizedCarveout5Cfg0 = 0; + + // Patch SDRAM parameters. + uint32_t t0 = params->EmcSwizzleRank0Byte0 << 5 >> 29 > params->EmcSwizzleRank0Byte0 << 1 >> 29; + uint32_t t1 = (t0 & 0xFFFFFFEF) | ((params->EmcSwizzleRank1Byte0 << 5 >> 29 > params->EmcSwizzleRank1Byte0 << 1 >> 29) << 4); + uint32_t t2 = (t1 & 0xFFFFFFFD) | ((params->EmcSwizzleRank0Byte1 << 5 >> 29 > params->EmcSwizzleRank0Byte1 << 1 >> 29) << 1); + uint32_t t3 = (t2 & 0xFFFFFFDF) | ((params->EmcSwizzleRank1Byte1 << 5 >> 29 > params->EmcSwizzleRank1Byte1 << 1 >> 29) << 5); + uint32_t t4 = (t3 & 0xFFFFFFFB) | ((params->EmcSwizzleRank0Byte2 << 5 >> 29 > params->EmcSwizzleRank0Byte2 << 1 >> 29) << 2); + uint32_t t5 = (t4 & 0xFFFFFFBF) | ((params->EmcSwizzleRank1Byte2 << 5 >> 29 > params->EmcSwizzleRank1Byte2 << 1 >> 29) << 6); + uint32_t t6 = (t5 & 0xFFFFFFF7) | ((params->EmcSwizzleRank0Byte3 << 5 >> 29 > params->EmcSwizzleRank0Byte3 << 1 >> 29) << 3); + uint32_t t7 = (t6 & 0xFFFFFF7F) | ((params->EmcSwizzleRank1Byte3 << 5 >> 29 > params->EmcSwizzleRank1Byte3 << 1 >> 29) << 7); + *(volatile uint32_t *)params->SwizzleRankByteEncode = t7; + *(volatile uint32_t *)params->EmcBctSpare2 = 0x40000DD8; + *(volatile uint32_t *)params->EmcBctSpare3 = t7; + + s(EmcClockSource, 7:0, scratch6, 15:8); + s(EmcClockSourceDll, 7:0, scratch6, 23:16); + s(EmcClockSource, 31:29, scratch6, 26:24); + s(EmcClockSourceDll, 31:29, scratch6, 29:27); + s(EmcClockSourceDll, 11:10, scratch6, 31:30); + s(ClkRstControllerPllmMisc2Override, 9:8, scratch7, 1:0); + s(ClkRstControllerPllmMisc2Override, 2:1, scratch7, 3:2); + s(EmcZqCalLpDdr4WarmBoot, 31:30, scratch7, 5:4); + s(EmcClockSource, 15:15, scratch7, 6:6); + s(EmcClockSource, 26:26, scratch7, 7:7); + s(EmcClockSource, 20:20, scratch7, 8:8); + s(EmcClockSource, 19:19, scratch7, 9:9); + s(ClkRstControllerPllmMisc2Override, 13:13, scratch7, 10:10); + s(ClkRstControllerPllmMisc2Override, 12:12, scratch7, 11:11); + s(ClkRstControllerPllmMisc2Override, 11:11, scratch7, 12:12); + s(ClkRstControllerPllmMisc2Override, 10:10, scratch7, 13:13); + s(ClkRstControllerPllmMisc2Override, 5:5, scratch7, 14:14); + s(ClkRstControllerPllmMisc2Override, 4:4, scratch7, 15:15); + s(ClkRstControllerPllmMisc2Override, 3:3, scratch7, 16:16); + s(ClkRstControllerPllmMisc2Override, 0:0, scratch7, 17:17); + s(EmcZqCalLpDdr4WarmBoot, 1:0, scratch7, 19:18); + s(EmcZqCalLpDdr4WarmBoot, 4:4, scratch7, 20:20); + s(EmcOdtWrite, 5:0, scratch7, 26:21); + s(EmcOdtWrite, 11:8, scratch7, 30:27); + s(EmcOdtWrite, 31:31, scratch7, 31:31); + s(EmcFdpdCtrlCmdNoRamp, 0:0, scratch13, 30:30); + s(EmcCfgPipeClk, 0:0, scratch13, 31:31); + s(McEmemArbMisc2, 0:0, scratch14, 30:30); + s(McDaCfg0, 0:0, scratch14, 31:31); + s(EmcQRst, 6:0, scratch15, 26:20); + s(EmcQRst, 20:16, scratch15, 31:27); + s(EmcPmacroCmdTxDrv, 5:0, scratch16, 25:20); + s(EmcPmacroCmdTxDrv, 13:8, scratch16, 31:26); + s(EmcPmacroAutocalCfg0, 2:0, scratch17, 22:20); + s(EmcPmacroAutocalCfg0, 10:8, scratch17, 25:23); + s(EmcPmacroAutocalCfg0, 18:16, scratch17, 28:26); + s(EmcPmacroAutocalCfg0, 26:24, scratch17, 31:29); + s(EmcPmacroAutocalCfg1, 2:0, scratch18, 22:20); + s(EmcPmacroAutocalCfg1, 10:8, scratch18, 25:23); + s(EmcPmacroAutocalCfg1, 18:16, scratch18, 28:26); + s(EmcPmacroAutocalCfg1, 26:24, scratch18, 31:29); + s(EmcPmacroAutocalCfg2, 2:0, scratch19, 22:20); + s(EmcPmacroAutocalCfg2, 10:8, scratch19, 25:23); + s(EmcPmacroAutocalCfg2, 18:16, scratch19, 28:26); + s(EmcPmacroAutocalCfg2, 26:24, scratch19, 31:29); + s32(EmcCfgRsv,scratch22); + s32(EmcAutoCalConfig, scratch23); + s32(EmcAutoCalVrefSel0, scratch24); + s32(EmcPmacroBrickCtrlRfu1, scratch25); + s32(EmcPmacroBrickCtrlRfu2, scratch26); + s32(EmcPmcScratch1, scratch27); + s32(EmcPmcScratch2, scratch28); + s32(EmcPmcScratch3, scratch29); + s32(McEmemArbDaTurns, scratch30); + s(EmcFbioSpare, 31:24, scratch58, 7:0); + s(EmcFbioSpare, 23:16, scratch58, 15:8); + s(EmcFbioSpare, 15:8, scratch58, 23:16); + s(EmcFbioSpare, 7:2, scratch58, 29:24); + s(EmcFbioSpare, 0:0, scratch58, 30:30); + s(EmcDllCfg0, 29:0, scratch59, 29:0); + s(EmcPmacroDdllBypass, 11:0, scratch60, 11:0); + s(EmcPmacroDdllBypass, 27:13, scratch60, 26:12); + s(EmcPmacroDdllBypass, 31:29, scratch60, 29:27); + s(McEmemArbMisc0, 14:0, scratch61, 14:0); + s(McEmemArbMisc0, 30:16, scratch61, 29:15); + s(EmcFdpdCtrlCmd, 16:0, scratch62, 16:0); + s(EmcFdpdCtrlCmd, 31:20, scratch62, 28:17); + s(EmcAutoCalConfig2, 27:0, scratch63, 27:0); + s(EmcBurstRefreshNum, 3:0, scratch63, 31:28); + s(EmcPmacroZctrl, 27:0, scratch64, 27:0); + s(EmcTppd, 3:0, scratch64, 31:28); + s(EmcCfgDigDll, 10:0, scratch65, 10:0); + s(EmcCfgDigDll, 25:12, scratch65, 24:11); + s(EmcCfgDigDll, 27:27, scratch65, 25:25); + s(EmcCfgDigDll, 31:30, scratch65, 27:26); + s(EmcR2r, 3:0, scratch65, 31:28); + s(EmcFdpdCtrlDq, 16:0, scratch66, 16:0); + s(EmcFdpdCtrlDq, 28:20, scratch66, 25:17); + s(EmcFdpdCtrlDq, 31:30, scratch66, 27:26); + s(EmcW2w, 3:0, scratch66, 31:28); + s(EmcPmacroTxPwrd4, 13:0, scratch67, 13:0); + s(EmcPmacroTxPwrd4, 29:16, scratch67, 27:14); + s(EmcPmacroCommonPadTxCtrl, 3:0, scratch67, 31:28); + s(EmcPmacroTxPwrd5, 13:0, scratch68, 13:0); + s(EmcPmacroTxPwrd5, 29:16, scratch68, 27:14); + s(EmcPmacroDdllPwrd0, 4:0, scratch69, 4:0); + s(EmcPmacroDdllPwrd0, 12:6, scratch69, 11:5); + s(EmcPmacroDdllPwrd0, 20:14, scratch69, 18:12); + s(EmcPmacroDdllPwrd0, 28:22, scratch69, 25:19); + s(EmcPmacroDdllPwrd0, 31:30, scratch69, 27:26); + s(EmcCfg, 4:4, scratch69, 31:31); + s(EmcPmacroDdllPwrd1, 4:0, scratch70, 4:0); + s(EmcPmacroDdllPwrd1, 12:6, scratch70, 11:5); + s(EmcPmacroDdllPwrd1, 20:14, scratch70, 18:12); + s(EmcPmacroDdllPwrd1, 28:22, scratch70, 25:19); + s(EmcPmacroDdllPwrd1, 31:30, scratch70, 27:26); + s(EmcCfg, 5:5, scratch70, 31:31); + s(EmcPmacroDdllPwrd2, 4:0, scratch71, 4:0); + s(EmcPmacroDdllPwrd2, 12:6, scratch71, 11:5); + s(EmcPmacroDdllPwrd2, 20:14, scratch71, 18:12); + s(EmcPmacroDdllPwrd2, 28:22, scratch71, 25:19); + s(EmcPmacroDdllPwrd2, 31:30, scratch71, 27:26); + s(EmcFbioCfg5, 23:20, scratch71, 31:28); + s(EmcPmacroIbVrefDq_0, 6:0, scratch72, 6:0); + s(EmcPmacroIbVrefDq_0, 14:8, scratch72, 13:7); + s(EmcPmacroIbVrefDq_0, 22:16, scratch72, 20:14); + s(EmcPmacroIbVrefDq_0, 30:24, scratch72, 27:21); + s(EmcFbioCfg5, 15:13, scratch72, 30:28); + s(EmcCfg, 6:6, scratch72, 31:31); + s(EmcPmacroIbVrefDq_1, 6:0, scratch73, 6:0); + s(EmcPmacroIbVrefDq_1, 14:8, scratch73, 13:7); + s(EmcPmacroIbVrefDq_1, 22:16, scratch73, 20:14); + s(EmcPmacroIbVrefDq_1, 30:24, scratch73, 27:21); + s(EmcCfg2, 5:3, scratch73, 30:28); + s(EmcCfg, 7:7, scratch73, 31:31); + s(EmcPmacroIbVrefDqs_0, 6:0, scratch74, 6:0); + s(EmcPmacroIbVrefDqs_0, 14:8, scratch74, 13:7); + s(EmcPmacroIbVrefDqs_0, 22:16, scratch74, 20:14); + s(EmcPmacroIbVrefDqs_0, 30:24, scratch74, 27:21); + s(EmcCfg, 17:16, scratch74, 29:28); + s(EmcFbioCfg5, 1:0, scratch74, 31:30); + s(EmcPmacroIbVrefDqs_1, 6:0, scratch75, 6:0); + s(EmcPmacroIbVrefDqs_1, 14:8, scratch75, 13:7); + s(EmcPmacroIbVrefDqs_1, 22:16, scratch75, 20:14); + s(EmcPmacroIbVrefDqs_1, 30:24, scratch75, 27:21); + s(EmcFbioCfg5, 3:2, scratch75, 29:28); + s(EmcCfg2, 27:26, scratch75, 31:30); + s(EmcPmacroDdllShortCmd_0, 6:0, scratch76, 6:0); + s(EmcPmacroDdllShortCmd_0, 14:8, scratch76, 13:7); + s(EmcPmacroDdllShortCmd_0, 22:16, scratch76, 20:14); + s(EmcPmacroDdllShortCmd_0, 30:24, scratch76, 27:21); + s(EmcPmacroCmdPadTxCtrl, 3:2, scratch76, 29:28); + s(EmcPmacroCmdPadTxCtrl, 7:6, scratch76, 31:30); + s(EmcPmacroDdllShortCmd_1, 6:0, scratch77, 6:0); + s(EmcPmacroDdllShortCmd_1, 14:8, scratch77, 13:7); + s(EmcPmacroDdllShortCmd_1, 22:16, scratch77, 20:14); + s(EmcPmacroDdllShortCmd_1, 30:24, scratch77, 27:21); + s(EmcPmacroCmdPadTxCtrl, 11:10, scratch77, 29:28); + s(EmcPmacroCmdPadTxCtrl, 15:14, scratch77, 31:30); + s(EmcAutoCalChannel, 5:0, scratch78, 5:0); + s(EmcAutoCalChannel, 11:8, scratch78, 9:6); + s(EmcAutoCalChannel, 27:16, scratch78, 21:10); + s(EmcAutoCalChannel, 31:29, scratch78, 24:22); + s(EmcConfigSampleDelay, 6:0, scratch78, 31:25); + s(EmcPmacroRxTerm, 5:0, scratch79, 5:0); + s(EmcPmacroRxTerm, 13:8, scratch79, 11:6); + s(EmcPmacroRxTerm, 21:16, scratch79, 17:12); + s(EmcPmacroRxTerm, 29:24, scratch79, 23:18); + s(EmcRc, 7:0, scratch79, 31:24); + s(EmcPmacroDqTxDrv, 5:0, scratch80, 5:0); + s(EmcPmacroDqTxDrv, 13:8, scratch80, 11:6); + s(EmcPmacroDqTxDrv, 21:16, scratch80, 17:12); + s(EmcPmacroDqTxDrv, 29:24, scratch80, 23:18); + s(EmcSelDpdCtrl, 5:2, scratch80, 27:24); + s(EmcSelDpdCtrl, 8:8, scratch80, 28:28); + s(EmcSelDpdCtrl, 18:16, scratch80, 31:29); + s(EmcPmacroCaTxDrv, 5:0, scratch81, 5:0); + s(EmcPmacroCaTxDrv, 13:8, scratch81, 11:6); + s(EmcPmacroCaTxDrv, 21:16, scratch81, 17:12); + s(EmcPmacroCaTxDrv, 29:24, scratch81, 23:18); + s(EmcObdly, 5:0, scratch81, 29:24); + s(EmcObdly, 29:28, scratch81, 31:30); + s(EmcZcalInterval, 23:10, scratch82, 13:0); + s(EmcZcalInterval, 9:0, scratch82, 23:14); + s(EmcPmacroCmdRxTermMode, 1:0, scratch82, 25:24); + s(EmcPmacroCmdRxTermMode, 5:4, scratch82, 27:26); + s(EmcPmacroCmdRxTermMode, 9:8, scratch82, 29:28); + s(EmcPmacroCmdRxTermMode, 13:12, scratch82, 31:30); + s(EmcDataBrlshft0, 23:0, scratch83, 23:0); + s(EmcPmacroDataRxTermMode, 1:0, scratch83, 25:24); + s(EmcPmacroDataRxTermMode, 5:4, scratch83, 27:26); + s(EmcPmacroDataRxTermMode, 9:8, scratch83, 29:28); + s(EmcPmacroDataRxTermMode, 13:12, scratch83, 31:30); + s(EmcDataBrlshft1, 23:0, scratch84, 23:0); + s(McEmemArbTimingRc, 7:0, scratch84, 31:24); + s(EmcDqsBrlshft0, 23:0, scratch85, 23:0); + s(McEmemArbRsv, 7:0, scratch85, 31:24); + s(EmcDqsBrlshft1, 23:0, scratch86, 23:0); + s(EmcCfgPipe2, 11:0, scratch87, 11:0); + s(EmcCfgPipe2, 27:16, scratch87, 23:12); + s(EmcCfgPipe1, 11:0, scratch88, 11:0); + s(EmcCfgPipe1, 27:16, scratch88, 23:12); + s(EmcPmacroCmdCtrl0, 5:0, scratch89, 5:0); + s(EmcPmacroCmdCtrl0, 13:8, scratch89, 11:6); + s(EmcPmacroCmdCtrl0, 21:16, scratch89, 17:12); + s(EmcPmacroCmdCtrl0, 29:24, scratch89, 23:18); + s(EmcPmacroCmdCtrl1, 5:0, scratch90, 5:0); + s(EmcPmacroCmdCtrl1, 13:8, scratch90, 11:6); + s(EmcPmacroCmdCtrl1, 21:16, scratch90, 17:12); + s(EmcPmacroCmdCtrl1, 29:24, scratch90, 23:18); + s(EmcRas, 6:0, scratch90, 30:24); + s(EmcCfg, 8:8, scratch90, 31:31); + s(EmcPmacroVttgenCtrl2, 23:0, scratch91, 23:0); + s(EmcW2p, 6:0, scratch91, 30:24); + s(EmcCfg, 9:9, scratch91, 31:31); + s(EmcPmacroCmdPadRxCtrl, 2:0, scratch92, 2:0); + s(EmcPmacroCmdPadRxCtrl, 5:4, scratch92, 4:3); + s(EmcPmacroCmdPadRxCtrl, 10:8, scratch92, 7:5); + s(EmcPmacroCmdPadRxCtrl, 22:12, scratch92, 18:8); + s(EmcPmacroCmdPadRxCtrl, 28:24, scratch92, 23:19); + s(EmcQSafe, 6:0, scratch92, 30:24); + s(EmcCfg, 18:18, scratch92, 31:31); + s(EmcPmacroDataPadRxCtrl, 2:0, scratch93, 2:0); + s(EmcPmacroDataPadRxCtrl, 5:4, scratch93, 4:3); + s(EmcPmacroDataPadRxCtrl, 10:8, scratch93, 7:5); + s(EmcPmacroDataPadRxCtrl, 22:12, scratch93, 18:8); + s(EmcPmacroDataPadRxCtrl, 28:24, scratch93, 23:19); + s(EmcRdv, 6:0, scratch93, 30:24); + s(EmcCfg, 21:21, scratch93, 31:31); + s(McEmemArbDaCovers, 23:0, scratch94, 23:0); + s(EmcRw2Pden, 6:0, scratch94, 30:24); + s(EmcCfg, 22:22, scratch94, 31:31); + s(EmcPmacroCmdCtrl2, 5:0, scratch95, 5:0); + s(EmcPmacroCmdCtrl2, 13:9, scratch95, 10:6); + s(EmcPmacroCmdCtrl2, 21:16, scratch95, 16:11); + s(EmcPmacroCmdCtrl2, 29:24, scratch95, 22:17); + s(EmcRfcPb, 8:0, scratch95, 31:23); + s(EmcPmacroQuseDdllRank0_0, 10:0, scratch96, 10:0); + s(EmcPmacroQuseDdllRank0_0, 26:16, scratch96, 21:11); + s(EmcCfgUpdate, 2:0, scratch96, 24:22); + s(EmcCfgUpdate, 10:8, scratch96, 27:25); + s(EmcCfgUpdate, 31:28, scratch96, 31:28); + s(EmcPmacroQuseDdllRank0_1, 10:0, scratch97, 10:0); + s(EmcPmacroQuseDdllRank0_1, 26:16, scratch97, 21:11); + s(EmcRfc, 9:0, scratch97, 31:22); + s(EmcPmacroQuseDdllRank0_2, 10:0, scratch98, 10:0); + s(EmcPmacroQuseDdllRank0_2, 26:16, scratch98, 21:11); + s(EmcTxsr, 9:0, scratch98, 31:22); + s(EmcPmacroQuseDdllRank0_3, 10:0, scratch99, 10:0); + s(EmcPmacroQuseDdllRank0_3, 26:16, scratch99, 21:11); + s(EmcMc2EmcQ, 2:0, scratch99, 24:22); + s(EmcMc2EmcQ, 10:8, scratch99, 27:25); + s(EmcMc2EmcQ, 27:24, scratch99, 31:28); + s(EmcPmacroQuseDdllRank0_4, 10:0, scratch100, 10:0); + s(EmcPmacroQuseDdllRank0_4, 26:16, scratch100, 21:11); + s(McEmemArbRing1Throttle, 4:0, scratch100, 26:22); + s(McEmemArbRing1Throttle, 20:16, scratch100, 31:27); + s(EmcPmacroQuseDdllRank0_5, 10:0, scratch101, 10:0); + s(EmcPmacroQuseDdllRank0_5, 26:16, scratch101, 21:11); + s(EmcPmacroQuseDdllRank1_0, 10:0, scratch102, 10:0); + s(EmcPmacroQuseDdllRank1_0, 26:16, scratch102, 21:11); + s(EmcAr2Pden, 8:0, scratch102, 30:22); + s(EmcCfg, 23:23, scratch102, 31:31); + s(EmcPmacroQuseDdllRank1_1, 10:0, scratch103, 10:0); + s(EmcPmacroQuseDdllRank1_1, 26:16, scratch103, 21:11); + s(EmcRfcSlr, 8:0, scratch103, 30:22); + s(EmcCfg, 24:24, scratch103, 31:31); + s(EmcPmacroQuseDdllRank1_2, 10:0, scratch104, 10:0); + s(EmcPmacroQuseDdllRank1_2, 26:16, scratch104, 21:11); + s(EmcIbdly, 6:0, scratch104, 28:22); + s(EmcIbdly, 29:28, scratch104, 30:29); + s(EmcCfg, 25:25, scratch104, 31:31); + s(EmcPmacroQuseDdllRank1_3, 10:0, scratch105, 10:0); + s(EmcPmacroQuseDdllRank1_3, 26:16, scratch105, 21:11); + s(McEmemArbTimingRFCPB, 8:0, scratch105, 30:22); + s(EmcCfg, 26:26, scratch105, 31:31); + s(EmcPmacroQuseDdllRank1_4, 10:0, scratch106, 10:0); + s(EmcPmacroQuseDdllRank1_4, 26:16, scratch106, 21:11); + s(EmcTfaw, 6:0, scratch106, 28:22); + s(EmcPmacroDataPadTxCtrl, 3:2, scratch106, 30:29); + s(EmcCfg, 28:28, scratch106, 31:31); + s(EmcPmacroQuseDdllRank1_5, 10:0, scratch107, 10:0); + s(EmcPmacroQuseDdllRank1_5, 26:16, scratch107, 21:11); + s(EmcTClkStable, 6:0, scratch107, 28:22); + s(EmcPmacroDataPadTxCtrl, 7:6, scratch107, 30:29); + s(EmcCfg, 29:29, scratch107, 31:31); + s(EmcPmacroObDdllLongDqRank0_0, 10:0, scratch108, 10:0); + s(EmcPmacroObDdllLongDqRank0_0, 26:16, scratch108, 21:11); + s(EmcPdex2Mrr, 6:0, scratch108, 28:22); + s(EmcPmacroDataPadTxCtrl, 11:10, scratch108, 30:29); + s(EmcCfg, 30:30, scratch108, 31:31); + s(EmcPmacroObDdllLongDqRank0_1, 10:0, scratch109, 10:0); + s(EmcPmacroObDdllLongDqRank0_1, 26:16, scratch109, 21:11); + s(EmcRdvMask, 6:0, scratch109, 28:22); + s(EmcPmacroDataPadTxCtrl, 15:14, scratch109, 30:29); + s(EmcCfg, 31:31, scratch109, 31:31); + s(EmcPmacroObDdllLongDqRank0_2, 10:0, scratch110, 10:0); + s(EmcPmacroObDdllLongDqRank0_2, 26:16, scratch110, 21:11); + s(EmcRdvEarlyMask, 6:0, scratch110, 28:22); + s(EmcFbioCfg5, 4:4, scratch110, 29:29); + s(EmcFbioCfg5, 8:8, scratch110, 30:30); + s(EmcFbioCfg5, 10:10, scratch110, 31:31); + s(EmcPmacroObDdllLongDqRank0_3, 10:0, scratch111, 10:0); + s(EmcPmacroObDdllLongDqRank0_3, 26:16, scratch111, 21:11); + s(EmcRdvEarly, 6:0, scratch111, 28:22); + s(EmcFbioCfg5, 12:12, scratch111, 29:29); + s(EmcFbioCfg5, 25:24, scratch111, 31:30); + s(EmcPmacroObDdllLongDqRank0_4, 10:0, scratch112, 10:0); + s(EmcPmacroObDdllLongDqRank0_4, 26:16, scratch112, 21:11); + s(EmcPmacroDdllShortCmd_2, 6:0, scratch112, 28:22); + s(EmcFbioCfg5, 28:26, scratch112, 31:29); + s(EmcPmacroObDdllLongDqRank0_5, 10:0, scratch113, 10:0); + s(EmcPmacroObDdllLongDqRank0_5, 26:16, scratch113, 21:11); + s(McEmemArbTimingRp, 6:0, scratch113, 28:22); + s(EmcFbioCfg5, 31:30, scratch113, 30:29); + s(EmcCfg2, 0:0, scratch113, 31:31); + s(EmcPmacroObDdllLongDqRank1_0, 10:0, scratch114, 10:0); + s(EmcPmacroObDdllLongDqRank1_0, 26:16, scratch114, 21:11); + s(McEmemArbTimingRas, 6:0, scratch114, 28:22); + s(EmcCfg2, 2:1, scratch114, 30:29); + s(EmcCfg2, 7:7, scratch114, 31:31); + s(EmcPmacroObDdllLongDqRank1_1, 10:0, scratch115, 10:0); + s(EmcPmacroObDdllLongDqRank1_1, 26:16, scratch115, 21:11); + s(McEmemArbTimingFaw, 6:0, scratch115, 28:22); + s(EmcCfg2, 11:10, scratch115, 30:29); + s(EmcCfg2, 14:14, scratch115, 31:31); + s(EmcPmacroObDdllLongDqRank1_2, 10:0, scratch123, 10:0); + s(EmcPmacroObDdllLongDqRank1_2, 26:16, scratch123, 21:11); + s(McEmemArbTimingRap2Pre, 6:0, scratch123, 28:22); + s(EmcCfg2, 16:15, scratch123, 30:29); + s(EmcCfg2, 20:20, scratch123, 31:31); + s(EmcPmacroObDdllLongDqRank1_3, 10:0, scratch124, 10:0); + s(EmcPmacroObDdllLongDqRank1_3, 26:16, scratch124, 21:11); + s(McEmemArbTimingWap2Pre, 6:0, scratch124, 28:22); + s(EmcCfg2, 24:22, scratch124, 31:29); + s(EmcPmacroObDdllLongDqRank1_4, 10:0, scratch125, 10:0); + s(EmcPmacroObDdllLongDqRank1_4, 26:16, scratch125, 21:11); + s(McEmemArbTimingR2W, 6:0, scratch125, 28:22); + s(EmcCfg2, 25:25, scratch125, 29:29); + s(EmcCfg2, 29:28, scratch125, 31:30); + s(EmcPmacroObDdllLongDqRank1_5, 10:0, scratch126, 10:0); + s(EmcPmacroObDdllLongDqRank1_5, 26:16, scratch126, 21:11); + s(McEmemArbTimingW2R, 6:0, scratch126, 28:22); + s(EmcCfg2, 31:30, scratch126, 30:29); + s(EmcCfgPipe, 0:0, scratch126, 31:31); + s(EmcPmacroObDdllLongDqsRank0_0, 10:0, scratch127, 10:0); + s(EmcPmacroObDdllLongDqsRank0_0, 26:16, scratch127, 21:11); + s(EmcRp, 5:0, scratch127, 27:22); + s(EmcCfgPipe, 4:1, scratch127, 31:28); + s(EmcPmacroObDdllLongDqsRank0_1, 10:0, scratch128, 10:0); + s(EmcPmacroObDdllLongDqsRank0_1, 26:16, scratch128, 21:11); + s(EmcR2w, 5:0, scratch128, 27:22); + s(EmcCfgPipe, 8:5, scratch128, 31:28); + s(EmcPmacroObDdllLongDqsRank0_2, 10:0, scratch129, 10:0); + s(EmcPmacroObDdllLongDqsRank0_2, 26:16, scratch129, 21:11); + s(EmcW2r, 5:0, scratch129, 27:22); + s(EmcCfgPipe, 11:9, scratch129, 30:28); + s(EmcCfgPipe, 16:16, scratch129, 31:31); + s(EmcPmacroObDdllLongDqsRank0_3, 10:0, scratch130, 10:0); + s(EmcPmacroObDdllLongDqsRank0_3, 26:16, scratch130, 21:11); + s(EmcR2p, 5:0, scratch130, 27:22); + s(EmcCfgPipe, 20:17, scratch130, 31:28); + s(EmcPmacroObDdllLongDqsRank0_4, 10:0, scratch131, 10:0); + s(EmcPmacroObDdllLongDqsRank0_4, 26:16, scratch131, 21:11); + s(EmcCcdmw, 5:0, scratch131, 27:22); + s(EmcCfgPipe, 24:21, scratch131, 31:28); + s(EmcPmacroObDdllLongDqsRank0_5, 10:0, scratch132, 10:0); + s(EmcPmacroObDdllLongDqsRank0_5, 26:16, scratch132, 21:11); + s(EmcRdRcd, 5:0, scratch132, 27:22); + s(EmcCfgPipe, 27:25, scratch132, 30:28); + s(EmcPmacroTxPwrd0, 0:0, scratch132, 31:31); + s(EmcPmacroObDdllLongDqsRank1_0, 10:0, scratch133, 10:0); + s(EmcPmacroObDdllLongDqsRank1_0, 26:16, scratch133, 21:11); + s(EmcWrRcd, 5:0, scratch133, 27:22); + s(EmcPmacroTxPwrd0, 4:1, scratch133, 31:28); + s(EmcPmacroObDdllLongDqsRank1_1, 10:0, scratch134, 10:0); + s(EmcPmacroObDdllLongDqsRank1_1, 26:16, scratch134, 21:11); + s(EmcWdv, 5:0, scratch134, 27:22); + s(EmcPmacroTxPwrd0, 8:5, scratch134, 31:28); + s(EmcPmacroObDdllLongDqsRank1_2, 10:0, scratch135, 10:0); + s(EmcPmacroObDdllLongDqsRank1_2, 26:16, scratch135, 21:11); + s(EmcQUse, 5:0, scratch135, 27:22); + s(EmcPmacroTxPwrd0, 12:9, scratch135, 31:28); + s(EmcPmacroObDdllLongDqsRank1_3, 10:0, scratch136, 10:0); + s(EmcPmacroObDdllLongDqsRank1_3, 26:16, scratch136, 21:11); + s(EmcPdEx2Wr, 5:0, scratch136, 27:22); + s(EmcPmacroTxPwrd0, 13:13, scratch136, 28:28); + s(EmcPmacroTxPwrd0, 18:16, scratch136, 31:29); + s(EmcPmacroObDdllLongDqsRank1_4, 10:0, scratch137, 10:0); + s(EmcPmacroObDdllLongDqsRank1_4, 26:16, scratch137, 21:11); + s(EmcPdEx2Rd, 5:0, scratch137, 27:22); + s(EmcPmacroTxPwrd0, 22:19, scratch137, 31:28); + s(EmcPmacroObDdllLongDqsRank1_5, 10:0, scratch138, 10:0); + s(EmcPmacroObDdllLongDqsRank1_5, 26:16, scratch138, 21:11); + s(EmcPdex2Cke, 5:0, scratch138, 27:22); + s(EmcPmacroTxPwrd0, 26:23, scratch138, 31:28); + s(EmcPmacroIbDdllLongDqsRank0_0, 10:0, scratch139, 10:0); + s(EmcPmacroIbDdllLongDqsRank0_0, 26:16, scratch139, 21:11); + s(EmcPChg2Pden, 5:0, scratch139, 27:22); + s(EmcPmacroTxPwrd0, 29:27, scratch139, 30:28); + s(EmcPmacroTxPwrd1, 0:0, scratch139, 31:31); + s(EmcPmacroIbDdllLongDqsRank0_1, 10:0, scratch140, 10:0); + s(EmcPmacroIbDdllLongDqsRank0_1, 26:16, scratch140, 21:11); + s(EmcAct2Pden, 5:0, scratch140, 27:22); + s(EmcPmacroTxPwrd1, 4:1, scratch140, 31:28); + s(EmcPmacroIbDdllLongDqsRank0_2, 10:0, scratch141, 10:0); + s(EmcPmacroIbDdllLongDqsRank0_2, 26:16, scratch141, 21:11); + s(EmcCke2Pden, 5:0, scratch141, 27:22); + s(EmcPmacroTxPwrd1, 8:5, scratch141, 31:28); + s(EmcPmacroIbDdllLongDqsRank0_3, 10:0, scratch142, 10:0); + s(EmcPmacroIbDdllLongDqsRank0_3, 26:16, scratch142, 21:11); + s(EmcTcke, 5:0, scratch142, 27:22); + s(EmcPmacroTxPwrd1, 12:9, scratch142, 31:28); + s(EmcPmacroIbDdllLongDqsRank1_0, 10:0, scratch143, 10:0); + s(EmcPmacroIbDdllLongDqsRank1_0, 26:16, scratch143, 21:11); + s(EmcTrpab, 5:0, scratch143, 27:22); + s(EmcPmacroTxPwrd1, 13:13, scratch143, 28:28); + s(EmcPmacroTxPwrd1, 18:16, scratch143, 31:29); + s(EmcPmacroIbDdllLongDqsRank1_1, 10:0, scratch144, 10:0); + s(EmcPmacroIbDdllLongDqsRank1_1, 26:16, scratch144, 21:11); + s(EmcClkenOverride, 3:1, scratch144, 24:22); + s(EmcClkenOverride, 8:6, scratch144, 27:25); + s(EmcPmacroTxPwrd1, 22:19, scratch144, 31:28); + s(EmcPmacroIbDdllLongDqsRank1_2, 10:0, scratch145, 10:0); + s(EmcPmacroIbDdllLongDqsRank1_2, 26:16, scratch145, 21:11); + s(EmcEInput, 5:0, scratch145, 27:22); + s(EmcPmacroTxPwrd1, 26:23, scratch145, 31:28); + s(EmcPmacroIbDdllLongDqsRank1_3, 10:0, scratch146, 10:0); + s(EmcPmacroIbDdllLongDqsRank1_3, 26:16, scratch146, 21:11); + s(EmcEInputDuration, 5:0, scratch146, 27:22); + s(EmcPmacroTxPwrd1, 29:27, scratch146, 30:28); + s(EmcPmacroTxPwrd2, 0:0, scratch146, 31:31); + s(EmcPmacroDdllLongCmd_0, 10:0, scratch147, 10:0); + s(EmcPmacroDdllLongCmd_0, 26:16, scratch147, 21:11); + s(EmcPutermExtra, 5:0, scratch147, 27:22); + s(EmcPmacroTxPwrd2, 4:1, scratch147, 31:28); + s(EmcPmacroDdllLongCmd_1, 10:0, scratch148, 10:0); + s(EmcPmacroDdllLongCmd_1, 26:16, scratch148, 21:11); + s(EmcTckesr, 5:0, scratch148, 27:22); + s(EmcPmacroTxPwrd2, 8:5, scratch148, 31:28); + s(EmcPmacroDdllLongCmd_2, 10:0, scratch149, 10:0); + s(EmcPmacroDdllLongCmd_2, 26:16, scratch149, 21:11); + s(EmcTpd, 5:0, scratch149, 27:22); + s(EmcPmacroTxPwrd2, 12:9, scratch149, 31:28); + s(EmcPmacroDdllLongCmd_3, 10:0, scratch150, 10:0); + s(EmcPmacroDdllLongCmd_3, 26:16, scratch150, 21:11); + s(EmcWdvMask, 5:0, scratch150, 27:22); + s(EmcPmacroTxPwrd2, 13:13, scratch150, 28:28); + s(EmcPmacroTxPwrd2, 18:16, scratch150, 31:29); + s(McEmemArbCfg, 8:0, scratch151, 8:0); + s(McEmemArbCfg, 20:16, scratch151, 13:9); + s(McEmemArbCfg, 31:24, scratch151, 21:14); + s(EmcWdvChk, 5:0, scratch151, 27:22); + s(EmcPmacroTxPwrd2, 22:19, scratch151, 31:28); + s(McEmemArbMisc1, 12:0, scratch152, 12:0); + s(McEmemArbMisc1, 25:21, scratch152, 17:13); + s(McEmemArbMisc1, 31:28, scratch152, 21:18); + s(EmcCmdBrlshft0, 5:0, scratch152, 27:22); + s(EmcPmacroTxPwrd2, 26:23, scratch152, 31:28); + s(EmcMrsWaitCnt2, 9:0, scratch153, 9:0); + s(EmcMrsWaitCnt2, 26:16, scratch153, 20:10); + s(EmcPmacroIbRxrt, 10:0, scratch153, 31:21); + s(EmcMrsWaitCnt, 9:0, scratch154, 9:0); + s(EmcMrsWaitCnt, 26:16, scratch154, 20:10); + s(EmcPmacroDdllLongCmd_4, 10:0, scratch154, 31:21); + s(EmcAutoCalInterval, 20:0, scratch155, 20:0); + s(McEmemArbOutstandingReq, 8:0, scratch155, 29:21); + s(McEmemArbOutstandingReq, 31:30, scratch155, 31:30); + s(McEmemArbRefpbHpCtrl, 6:0, scratch156, 6:0); + s(McEmemArbRefpbHpCtrl, 14:8, scratch156, 13:7); + s(McEmemArbRefpbHpCtrl, 22:16, scratch156, 20:14); + s(EmcCmdBrlshft1, 5:0, scratch156, 26:21); + s(EmcRrd, 4:0, scratch156, 31:27); + s(EmcQuseBrlshft0, 19:0, scratch157, 19:0); + s(EmcFbioCfg8, 27:16, scratch157, 31:20); + s(EmcQuseBrlshft1, 19:0, scratch158, 19:0); + s(EmcTxsrDll, 11:0, scratch158, 31:20); + s(EmcQuseBrlshft2, 19:0, scratch159, 19:0); + s(EmcTxdsrvttgen, 11:0, scratch159, 31:20); + s(EmcQuseBrlshft3, 19:0, scratch160, 19:0); + s(EmcPmacroVttgenCtrl0, 3:0, scratch160, 23:20); + s(EmcPmacroVttgenCtrl0, 11:8, scratch160, 27:24); + s(EmcPmacroVttgenCtrl0, 19:16, scratch160, 31:28); + s(EmcPmacroVttgenCtrl1, 19:0, scratch161, 19:0); + s(EmcCmdBrlshft2, 5:0, scratch161, 25:20); + s(EmcCmdBrlshft3, 5:0, scratch161, 31:26); + s(EmcAutoCalConfig3, 5:0, scratch162, 5:0); + s(EmcAutoCalConfig3, 13:8, scratch162, 11:6); + s(EmcAutoCalConfig3, 18:16, scratch162, 14:12); + s(EmcAutoCalConfig3, 22:20, scratch162, 17:15); + s(EmcTRefBw, 13:0, scratch162, 31:18); + s(EmcAutoCalConfig4, 5:0, scratch163, 5:0); + s(EmcAutoCalConfig4, 13:8, scratch163, 11:6); + s(EmcAutoCalConfig4, 18:16, scratch163, 14:12); + s(EmcAutoCalConfig4, 22:20, scratch163, 17:15); + s(EmcQpop, 6:0, scratch163, 24:18); + s(EmcQpop, 22:16, scratch163, 31:25); + s(EmcAutoCalConfig5, 5:0, scratch164, 5:0); + s(EmcAutoCalConfig5, 13:8, scratch164, 11:6); + s(EmcAutoCalConfig5, 18:16, scratch164, 14:12); + s(EmcAutoCalConfig5, 22:20, scratch164, 17:15); + s(EmcPmacroAutocalCfgCommon, 5:0, scratch164, 23:18); + s(EmcPmacroAutocalCfgCommon, 13:8, scratch164, 29:24); + s(EmcPmacroAutocalCfgCommon, 16:16, scratch164, 30:30); + s(EmcPmacroTxPwrd2, 27:27, scratch164, 31:31); + s(EmcAutoCalConfig6, 5:0, scratch165, 5:0); + s(EmcAutoCalConfig6, 13:8, scratch165, 11:6); + s(EmcAutoCalConfig6, 18:16, scratch165, 14:12); + s(EmcAutoCalConfig6, 22:20, scratch165, 17:15); + s(EmcWev, 5:0, scratch165, 23:18); + s(EmcWsv, 5:0, scratch165, 29:24); + s(EmcPmacroTxPwrd2, 29:28, scratch165, 31:30); + s(EmcAutoCalConfig7, 5:0, scratch166, 5:0); + s(EmcAutoCalConfig7, 13:8, scratch166, 11:6); + s(EmcAutoCalConfig7, 18:16, scratch166, 14:12); + s(EmcAutoCalConfig7, 22:20, scratch166, 17:15); + s(EmcCfg3, 2:0, scratch166, 20:18); + s(EmcCfg3, 6:4, scratch166, 23:21); + s(EmcQuseWidth, 3:0, scratch166, 27:24); + s(EmcQuseWidth, 29:28, scratch166, 29:28); + s(EmcPmacroTxPwrd3, 1:0, scratch166, 31:30); + s(EmcAutoCalConfig8, 5:0, scratch167, 5:0); + s(EmcAutoCalConfig8, 13:8, scratch167, 11:6); + s(EmcAutoCalConfig8, 18:16, scratch167, 14:12); + s(EmcAutoCalConfig8, 22:20, scratch167, 17:15); + s(EmcPmacroBgBiasCtrl0, 2:0, scratch167, 20:18); + s(EmcPmacroBgBiasCtrl0, 6:4, scratch167, 23:21); + s(McEmemArbTimingRcd, 5:0, scratch167, 29:24); + s(EmcPmacroTxPwrd3, 3:2, scratch167, 31:30); + s(EmcXm2CompPadCtrl2, 17:0, scratch168, 17:0); + s(McEmemArbTimingCcdmw, 5:0, scratch168, 23:18); + s(McEmemArbOverride, 27:27, scratch168, 24:24); + s(McEmemArbOverride, 26:26, scratch168, 25:25); + s(McEmemArbOverride, 16:16, scratch168, 26:26); + s(McEmemArbOverride, 10:10, scratch168, 27:27); + s(McEmemArbOverride, 4:4, scratch168, 28:28); + s(McEmemArbOverride, 3:3, scratch168, 29:29); + s(EmcPmacroTxPwrd3, 5:4, scratch168, 31:30); + s(EmcXm2CompPadCtrl3, 17:0, scratch169, 17:0); + s(EmcRext, 4:0, scratch169, 22:18); + s(EmcTClkStop, 4:0, scratch169, 27:23); + s(EmcPmacroTxPwrd3, 9:6, scratch169, 31:28); + s(EmcZcalWaitCnt, 10:0, scratch170, 10:0); + s(EmcZcalWaitCnt, 21:16, scratch170, 16:11); + s(EmcZcalWaitCnt, 31:31, scratch170, 17:17); + s(EmcWext, 4:0, scratch170, 22:18); + s(EmcRefctrl2, 0:0, scratch170, 23:23); + s(EmcRefctrl2, 26:24, scratch170, 26:24); + s(EmcRefctrl2, 31:31, scratch170, 27:27); + s(EmcPmacroTxPwrd3, 13:10, scratch170, 31:28); + s(EmcZcalMrwCmd, 7:0, scratch171, 7:0); + s(EmcZcalMrwCmd, 23:16, scratch171, 15:8); + s(EmcZcalMrwCmd, 31:30, scratch171, 17:16); + s(EmcWeDuration, 4:0, scratch171, 22:18); + s(EmcWsDuration, 4:0, scratch171, 27:23); + s(EmcPmacroTxPwrd3, 19:16, scratch171, 31:28); + s(EmcSwizzleRank0Byte0, 2:0, scratch172, 2:0); + s(EmcSwizzleRank0Byte0, 6:4, scratch172, 5:3); + s(EmcSwizzleRank0Byte0, 10:8, scratch172, 8:6); + s(EmcSwizzleRank0Byte0, 14:12, scratch172, 11:9); + s(EmcSwizzleRank0Byte0, 18:16, scratch172, 14:12); + s(EmcSwizzleRank0Byte0, 22:20, scratch172, 17:15); + s(EmcPutermWidth, 31:31, scratch172, 18:18); + s(EmcPutermWidth, 3:0, scratch172, 22:19); + s(McEmemArbTimingRrd, 4:0, scratch172, 27:23); + s(EmcPmacroTxPwrd3, 23:20, scratch172, 31:28); + s(EmcSwizzleRank0Byte1, 2:0, scratch173, 2:0); + s(EmcSwizzleRank0Byte1, 6:4, scratch173, 5:3); + s(EmcSwizzleRank0Byte1, 10:8, scratch173, 8:6); + s(EmcSwizzleRank0Byte1, 14:12, scratch173, 11:9); + s(EmcSwizzleRank0Byte1, 18:16, scratch173, 14:12); + s(EmcSwizzleRank0Byte1, 22:20, scratch173, 17:15); + s(McEmemArbTimingR2R, 4:0, scratch173, 22:18); + s(McEmemArbTimingW2W, 4:0, scratch173, 27:23); + s(EmcPmacroTxPwrd3, 27:24, scratch173, 31:28); + s(EmcSwizzleRank0Byte2, 2:0, scratch174, 2:0); + s(EmcSwizzleRank0Byte2, 6:4, scratch174, 5:3); + s(EmcSwizzleRank0Byte2, 10:8, scratch174, 8:6); + s(EmcSwizzleRank0Byte2, 14:12, scratch174, 11:9); + s(EmcSwizzleRank0Byte2, 18:16, scratch174, 14:12); + s(EmcSwizzleRank0Byte2, 22:20, scratch174, 17:15); + s(EmcPmacroTxPwrd3, 29:28, scratch174, 19:18); + s(EmcPmacroTxSelClkSrc0, 11:0, scratch174, 31:20); + s(EmcSwizzleRank0Byte3, 2:0, scratch175, 2:0); + s(EmcSwizzleRank0Byte3, 6:4, scratch175, 5:3); + s(EmcSwizzleRank0Byte3, 10:8, scratch175, 8:6); + s(EmcSwizzleRank0Byte3, 14:12, scratch175, 11:9); + s(EmcSwizzleRank0Byte3, 18:16, scratch175, 14:12); + s(EmcSwizzleRank0Byte3, 22:20, scratch175, 17:15); + s(EmcPmacroTxSelClkSrc0, 27:16, scratch175, 29:18); + s(EmcPmacroTxSelClkSrc1, 1:0, scratch175, 31:30); + s(EmcSwizzleRank1Byte0, 2:0, scratch176, 2:0); + s(EmcSwizzleRank1Byte0, 6:4, scratch176, 5:3); + s(EmcSwizzleRank1Byte0, 10:8, scratch176, 8:6); + s(EmcSwizzleRank1Byte0, 14:12, scratch176, 11:9); + s(EmcSwizzleRank1Byte0, 18:16, scratch176, 14:12); + s(EmcSwizzleRank1Byte0, 22:20, scratch176, 17:15); + s(EmcPmacroTxSelClkSrc1, 11:2, scratch176, 27:18); + s(EmcPmacroTxSelClkSrc1, 19:16, scratch176, 31:28); + s(EmcSwizzleRank1Byte1, 2:0, scratch177, 2:0); + s(EmcSwizzleRank1Byte1, 6:4, scratch177, 5:3); + s(EmcSwizzleRank1Byte1, 10:8, scratch177, 8:6); + s(EmcSwizzleRank1Byte1, 14:12, scratch177, 11:9); + s(EmcSwizzleRank1Byte1, 18:16, scratch177, 14:12); + s(EmcSwizzleRank1Byte1, 22:20, scratch177, 17:15); + s(EmcPmacroTxSelClkSrc1, 27:20, scratch177, 25:18); + s(EmcPmacroTxSelClkSrc3, 5:0, scratch177, 31:26); + s(EmcSwizzleRank1Byte2, 2:0, scratch178, 2:0); + s(EmcSwizzleRank1Byte2, 6:4, scratch178, 5:3); + s(EmcSwizzleRank1Byte2, 10:8, scratch178, 8:6); + s(EmcSwizzleRank1Byte2, 14:12, scratch178, 11:9); + s(EmcSwizzleRank1Byte2, 18:16, scratch178, 14:12); + s(EmcSwizzleRank1Byte2, 22:20, scratch178, 17:15); + s(EmcPmacroTxSelClkSrc3, 11:6, scratch178, 23:18); + s(EmcPmacroTxSelClkSrc3, 23:16, scratch178, 31:24); + s(EmcSwizzleRank1Byte3, 2:0, scratch179, 2:0); + s(EmcSwizzleRank1Byte3, 6:4, scratch179, 5:3); + s(EmcSwizzleRank1Byte3, 10:8, scratch179, 8:6); + s(EmcSwizzleRank1Byte3, 14:12, scratch179, 11:9); + s(EmcSwizzleRank1Byte3, 18:16, scratch179, 14:12); + s(EmcSwizzleRank1Byte3, 22:20, scratch179, 17:15); + s(EmcPmacroTxSelClkSrc3, 27:24, scratch179, 21:18); + s(EmcPmacroTxSelClkSrc2, 9:0, scratch179, 31:22); + s(EmcPmacroCmdBrickCtrlFdpd, 17:0, scratch180, 17:0); + s(EmcPmacroTxSelClkSrc2, 11:10, scratch180, 19:18); + s(EmcPmacroTxSelClkSrc2, 27:16, scratch180, 31:20); + s(EmcPmacroDataBrickCtrlFdpd, 17:0, scratch181, 17:0); + s(EmcPmacroTxSelClkSrc4, 11:0, scratch181, 29:18); + s(EmcPmacroTxSelClkSrc4, 17:16, scratch181, 31:30); + s(EmcFbioCfg7, 16:0, scratch182, 16:0); + s(McEmemArbRefpbBankCtrl, 6:0, scratch182, 23:17); + s(McEmemArbRefpbBankCtrl, 14:8, scratch182, 30:24); + s(McEmemArbRefpbBankCtrl, 31:31, scratch182, 31:31); + s(EmcDynSelfRefControl, 15:0, scratch183, 15:0); + s(EmcDynSelfRefControl, 31:31, scratch183, 16:16); + s(EmcPmacroTxSelClkSrc4, 27:18, scratch183, 26:17); + s(EmcPmacroTxSelClkSrc5, 4:0, scratch183, 31:27); + s(EmcDllCfg1, 16:0, scratch184, 16:0); + s(EmcPmacroTxSelClkSrc5, 11:5, scratch184, 23:17); + s(EmcPmacroTxSelClkSrc5, 23:16, scratch184, 31:24); + s(EmcPmacroPadCfgCtrl, 1:0, scratch185, 1:0); + s(EmcPmacroPadCfgCtrl, 6:5, scratch185, 3:2); + s(EmcPmacroPadCfgCtrl, 11:9, scratch185, 6:4); + s(EmcPmacroPadCfgCtrl, 13:13, scratch185, 7:7); + s(EmcPmacroPadCfgCtrl, 17:16, scratch185, 9:8); + s(EmcPmacroPadCfgCtrl, 21:20, scratch185, 11:10); + s(EmcPmacroPadCfgCtrl, 25:24, scratch185, 13:12); + s(EmcPmacroPadCfgCtrl, 30:28, scratch185, 16:14); + s(EmcPmacroTxSelClkSrc5, 27:24, scratch185, 20:17); + s(EmcPmacroCmdPadTxCtrl, 1:0, scratch185, 22:21); + s(EmcPmacroCmdPadTxCtrl, 5:4, scratch185, 24:23); + s(EmcPmacroCmdPadTxCtrl, 9:8, scratch185, 26:25); + s(EmcPmacroCmdPadTxCtrl, 13:12, scratch185, 28:27); + s(EmcPmacroCmdPadTxCtrl, 16:16, scratch185, 29:29); + s(EmcPmacroCmdPadTxCtrl, 21:20, scratch185, 31:30); + s(EmcRefresh, 15:0, scratch186, 15:0); + s(EmcCmdQ, 4:0, scratch186, 20:16); + s(EmcCmdQ, 10:8, scratch186, 23:21); + s(EmcCmdQ, 14:12, scratch186, 26:24); + s(EmcCmdQ, 28:24, scratch186, 31:27); + s(EmcAcpdControl, 15:0, scratch187, 15:0); + s(EmcAutoCalVrefSel1, 15:0, scratch187, 31:16); + s(EmcXm2CompPadCtrl, 1:0, scratch188, 1:0); + s(EmcXm2CompPadCtrl, 6:3, scratch188, 5:2); + s(EmcXm2CompPadCtrl, 9:9, scratch188, 6:6); + s(EmcXm2CompPadCtrl, 19:11, scratch188, 15:7); + s(EmcCfgDigDllPeriod, 15:0, scratch188, 31:16); + s(EmcCfgDigDll_1, 15:0, scratch189, 15:0); + s(EmcPreRefreshReqCnt, 15:0, scratch189, 31:16); + s(EmcPmacroCmdPadTxCtrl, 27:24, scratch190, 19:16); + s(EmcPmacroDataPadTxCtrl, 1:0, scratch190, 21:20); + s(EmcPmacroDataPadTxCtrl, 5:4, scratch190, 23:22); + s(EmcPmacroDataPadTxCtrl, 9:8, scratch190, 25:24); + s(EmcPmacroDataPadTxCtrl, 13:12, scratch190, 27:26); + s(EmcPmacroDataPadTxCtrl, 16:16, scratch190, 28:28); + s(EmcPmacroDataPadTxCtrl, 21:20, scratch190, 30:29); + s(EmcPmacroDataPadTxCtrl, 24:24, scratch190, 31:31); + s(EmcPmacroDataPadTxCtrl, 27:25, scratch191, 2:0); + + s(EmcPinGpio, 1:0, scratch8, 31:30); + s(EmcPinGpioEn, 1:0, scratch9, 31:30); + s(EmcDevSelect, 1:0, scratch10, 31:30); + s(EmcZcalWarmColdBootEnables, 1:0, scratch11, 31:30); + s(EmcCfgDigDllPeriodWarmBoot, 1:0, scratch12, 31:30); + s32(EmcBctSpare13, scratch31); + s32(EmcBctSpare12, scratch32); + s32(EmcBctSpare7, scratch33); + s32(EmcBctSpare6, scratch40); + s32(EmcBctSpare5, scratch42); + s32(EmcBctSpare4, scratch44); + s32(EmcBctSpare3, scratch45); + s32(EmcBctSpare2, scratch46); + s32(EmcBctSpare1, scratch47); + s32(EmcBctSpare0, scratch48); + s32(EmcBctSpare9, scratch50); + s32(EmcBctSpare8, scratch51); + s32(BootRomPatchData, scratch56); + s32(BootRomPatchControl, scratch57); + s(McClkenOverrideAllWarmBoot, 0:0, scratch58, 31:31); + s(EmcClkenOverrideAllWarmBoot, 0:0, scratch59, 30:30); + s(EmcMrsWarmBootEnable, 0:0, scratch59, 31:31); + s(ClearClk2Mc1, 0:0, scratch60, 30:30); + s(EmcWarmBootExtraModeRegWriteEnable, 0:0, scratch60, 31:31); + s(ClkRstControllerPllmMisc2OverrideEnable, 0:0, scratch61, 30:30); + s(EmcDbgWriteMux, 0:0, scratch61, 31:31); + s(EmcExtraRefreshNum, 2:0, scratch62, 31:29); + s(PmcIoDpd3ReqWait, 2:0, scratch68, 30:28); + s(AhbArbitrationXbarCtrlMemInitDone, 0:0, scratch68, 31:31); + s(MemoryType, 2:0, scratch69, 30:28); + s(PmcIoDpd4ReqWait, 2:0, scratch70, 30:28); + s(EmcTimingControlWait, 7:0, scratch86, 31:24); + s(EmcZcalWarmBootWait, 7:0, scratch87, 31:24); + s(WarmBootWait, 7:0, scratch88, 31:24); + s(EmcPinProgramWait, 7:0, scratch89, 31:24); + s(EmcAutoCalWait, 9:0, scratch101, 31:22); + s(SwizzleRankByteEncode, 15:0, scratch190, 15:0); + + switch (params->MemoryType) { + case NvBootMemoryType_LpDdr2: + case NvBootMemoryType_LpDdr4: + s(EmcMrwLpddr2ZcalWarmBoot, 23:16, scratch5, 7:0); + s(EmcMrwLpddr2ZcalWarmBoot, 7:0, scratch5, 15:8); + s(EmcWarmBootMrwExtra, 23:16, scratch5, 23:16); + s(EmcWarmBootMrwExtra, 7:0, scratch5, 31:24); + s(EmcMrwLpddr2ZcalWarmBoot, 31:30, scratch6, 1:0); + s(EmcWarmBootMrwExtra, 31:30, scratch6, 3:2); + s(EmcMrwLpddr2ZcalWarmBoot, 27:26, scratch6, 5:4); + s(EmcWarmBootMrwExtra, 27:26, scratch6, 7:6); + s(EmcMrw6, 27:0, scratch8, 27:0); + s(EmcMrw6, 31:30, scratch8, 29:28); + s(EmcMrw8, 27:0, scratch9, 27:0); + s(EmcMrw8, 31:30, scratch9, 29:28); + s(EmcMrw9, 27:0, scratch10, 27:0); + s(EmcMrw9, 31:30, scratch10, 29:28); + s(EmcMrw10, 27:0, scratch11, 27:0); + s(EmcMrw10, 31:30, scratch11, 29:28); + s(EmcMrw12, 27:0, scratch12, 27:0); + s(EmcMrw12, 31:30, scratch12, 29:28); + s(EmcMrw13, 27:0, scratch13, 27:0); + s(EmcMrw13, 31:30, scratch13, 29:28); + s(EmcMrw14, 27:0, scratch14, 27:0); + s(EmcMrw14, 31:30, scratch14, 29:28); + s(EmcMrw1, 7:0, scratch15, 7:0); + s(EmcMrw1, 23:16, scratch15, 15:8); + s(EmcMrw1, 27:26, scratch15, 17:16); + s(EmcMrw1, 31:30, scratch15, 19:18); + s(EmcWarmBootMrwExtra, 7:0, scratch16, 7:0); + s(EmcWarmBootMrwExtra, 23:16, scratch16, 15:8); + s(EmcWarmBootMrwExtra, 27:26, scratch16, 17:16); + s(EmcWarmBootMrwExtra, 31:30, scratch16, 19:18); + s(EmcMrw2, 7:0, scratch17, 7:0); + s(EmcMrw2, 23:16, scratch17, 15:8); + s(EmcMrw2, 27:26, scratch17, 17:16); + s(EmcMrw2, 31:30, scratch17, 19:18); + s(EmcMrw3, 7:0, scratch18, 7:0); + s(EmcMrw3, 23:16, scratch18, 15:8); + s(EmcMrw3, 27:26, scratch18, 17:16); + s(EmcMrw3, 31:30, scratch18, 19:18); + s(EmcMrw4, 7:0, scratch19, 7:0); + s(EmcMrw4, 23:16, scratch19, 15:8); + s(EmcMrw4, 27:26, scratch19, 17:16); + s(EmcMrw4, 31:30, scratch19, 19:18); + break; + case NvBootMemoryType_Ddr3: + s(EmcMrs, 13:0, scratch5, 13:0); + s(EmcEmrs, 13:0, scratch5, 27:14); + s(EmcMrs, 21:20, scratch5, 29:28); + s(EmcMrs, 31:30, scratch5, 31:30); + s(EmcEmrs2, 13:0, scratch8, 13:0); + s(EmcEmrs3, 13:0, scratch8, 27:14); + s(EmcEmrs, 21:20, scratch8, 29:28); + s(EmcWarmBootMrsExtra, 13:0, scratch9, 13:0); + s(EmcEmrs, 31:30, scratch9, 15:14); + s(EmcEmrs2, 21:20, scratch9, 17:16); + s(EmcEmrs2, 31:30, scratch9, 19:18); + s(EmcEmrs3, 21:20, scratch9, 21:20); + s(EmcEmrs3, 31:30, scratch9, 23:22); + s(EmcWarmBootMrsExtra, 31:30, scratch9, 25:24); + s(EmcWarmBootMrsExtra, 21:20, scratch9, 27:26); + s(EmcZqCalDdr3WarmBoot, 31:30, scratch9, 29:28); + s(EmcMrs, 27:26, scratch10, 1:0); + s(EmcEmrs, 27:26, scratch10, 3:2); + s(EmcEmrs2, 27:26, scratch10, 5:4); + s(EmcEmrs3, 27:26, scratch10, 7:6); + s(EmcWarmBootMrsExtra, 27:27, scratch10, 8:8); + s(EmcWarmBootMrsExtra, 26:26, scratch10, 9:9); + s(EmcZqCalDdr3WarmBoot, 0:0, scratch10, 10:10); + s(EmcZqCalDdr3WarmBoot, 4:4, scratch10, 11:11); + break; + default: break; + } + + s32(EmcCmdMappingByte, secure_scratch8); + s32(EmcPmacroBrickMapping0, secure_scratch9); + s32(EmcPmacroBrickMapping1, secure_scratch10); + s32(EmcPmacroBrickMapping2, secure_scratch11); + s32(McVideoProtectGpuOverride0, secure_scratch12); + s(EmcCmdMappingCmd0_0, 6:0, secure_scratch13, 6:0); + s(EmcCmdMappingCmd0_0, 14:8, secure_scratch13, 13:7); + s(EmcCmdMappingCmd0_0, 22:16, secure_scratch13, 20:14); + s(EmcCmdMappingCmd0_0, 30:24, secure_scratch13, 27:21); + s(McVideoProtectBomAdrHi, 1:0, secure_scratch13, 29:28); + s(McVideoProtectWriteAccess, 1:0, secure_scratch13, 31:30); + s(EmcCmdMappingCmd0_1, 6:0, secure_scratch14, 6:0); + s(EmcCmdMappingCmd0_1, 14:8, secure_scratch14, 13:7); + s(EmcCmdMappingCmd0_1, 22:16, secure_scratch14, 20:14); + s(EmcCmdMappingCmd0_1, 30:24, secure_scratch14, 27:21); + s(McSecCarveoutAdrHi, 1:0, secure_scratch14, 29:28); + s(McMtsCarveoutAdrHi, 1:0, secure_scratch14, 31:30); + s(EmcCmdMappingCmd1_0, 6:0, secure_scratch15, 6:0); + s(EmcCmdMappingCmd1_0, 14:8, secure_scratch15, 13:7); + s(EmcCmdMappingCmd1_0, 22:16, secure_scratch15, 20:14); + s(EmcCmdMappingCmd1_0, 30:24, secure_scratch15, 27:21); + s(McGeneralizedCarveout5BomHi, 1:0, secure_scratch15, 29:28); + s(McGeneralizedCarveout3BomHi, 1:0, secure_scratch15, 31:30); + s(EmcCmdMappingCmd1_1, 6:0, secure_scratch16, 6:0); + s(EmcCmdMappingCmd1_1, 14:8, secure_scratch16, 13:7); + s(EmcCmdMappingCmd1_1, 22:16, secure_scratch16, 20:14); + s(EmcCmdMappingCmd1_1, 30:24, secure_scratch16, 27:21); + s(McGeneralizedCarveout2BomHi, 1:0, secure_scratch16, 29:28); + s(McGeneralizedCarveout4BomHi, 1:0, secure_scratch16, 31:30); + s(EmcCmdMappingCmd2_0, 6:0, secure_scratch17, 6:0); + s(EmcCmdMappingCmd2_0, 14:8, secure_scratch17, 13:7); + s(EmcCmdMappingCmd2_0, 22:16, secure_scratch17, 20:14); + s(EmcCmdMappingCmd2_0, 30:24, secure_scratch17, 27:21); + s(McGeneralizedCarveout1BomHi, 1:0, secure_scratch17, 29:28); + s(EmcAdrCfg, 0:0, secure_scratch17, 30:30); + s(EmcFbioSpare, 1:1, secure_scratch17, 31:31); + s(EmcCmdMappingCmd2_1, 6:0, secure_scratch18, 6:0); + s(EmcCmdMappingCmd2_1, 14:8, secure_scratch18, 13:7); + s(EmcCmdMappingCmd2_1, 22:16, secure_scratch18, 20:14); + s(EmcCmdMappingCmd2_1, 30:24, secure_scratch18, 27:21); + s(EmcFbioCfg8, 15:15, secure_scratch18, 28:28); + s(McEmemAdrCfg, 0:0, secure_scratch18, 29:29); + s(McSecCarveoutProtectWriteAccess, 0:0, secure_scratch18, 30:30); + s(McMtsCarveoutRegCtrl, 0:0, secure_scratch18, 31:31); + s(EmcCmdMappingCmd3_0, 6:0, secure_scratch19, 6:0); + s(EmcCmdMappingCmd3_0, 14:8, secure_scratch19, 13:7); + s(EmcCmdMappingCmd3_0, 22:16, secure_scratch19, 20:14); + s(EmcCmdMappingCmd3_0, 30:24, secure_scratch19, 27:21); + s(McGeneralizedCarveout2Cfg0, 6:3, secure_scratch19, 31:28); + s(EmcCmdMappingCmd3_1, 6:0, secure_scratch20, 6:0); + s(EmcCmdMappingCmd3_1, 14:8, secure_scratch20, 13:7); + s(EmcCmdMappingCmd3_1, 22:16, secure_scratch20, 20:14); + s(EmcCmdMappingCmd3_1, 30:24, secure_scratch20, 27:21); + s(McGeneralizedCarveout2Cfg0, 10:7, secure_scratch20, 31:28); + s(McGeneralizedCarveout4Cfg0, 26:0, secure_scratch39, 26:0); + s(McGeneralizedCarveout2Cfg0, 17:14, secure_scratch39, 30:27); + s(McVideoProtectVprOverride, 0:0, secure_scratch39, 31:31); + s(McGeneralizedCarveout5Cfg0, 26:0, secure_scratch40, 26:0); + s(McGeneralizedCarveout2Cfg0, 21:18, secure_scratch40, 30:27); + s(McVideoProtectVprOverride, 1:1, secure_scratch40, 31:31); + s(EmcCmdMappingCmd0_2, 6:0, secure_scratch41, 6:0); + s(EmcCmdMappingCmd0_2, 14:8, secure_scratch41, 13:7); + s(EmcCmdMappingCmd0_2, 22:16, secure_scratch41, 20:14); + s(EmcCmdMappingCmd0_2, 27:24, secure_scratch41, 24:21); + s(McGeneralizedCarveout1Cfg0, 6:3, secure_scratch41, 28:25); + s(McGeneralizedCarveout2Cfg0, 13:11, secure_scratch41, 31:29); + s(EmcCmdMappingCmd1_2, 6:0, secure_scratch42, 6:0); + s(EmcCmdMappingCmd1_2, 14:8, secure_scratch42, 13:7); + s(EmcCmdMappingCmd1_2, 22:16, secure_scratch42, 20:14); + s(EmcCmdMappingCmd1_2, 27:24, secure_scratch42, 24:21); + s(McGeneralizedCarveout1Cfg0, 13:7, secure_scratch42, 31:25); + s(EmcCmdMappingCmd2_2, 6:0, secure_scratch43, 6:0); + s(EmcCmdMappingCmd2_2, 14:8, secure_scratch43, 13:7); + s(EmcCmdMappingCmd2_2, 22:16, secure_scratch43, 20:14); + s(EmcCmdMappingCmd2_2, 27:24, secure_scratch43, 24:21); + s(McGeneralizedCarveout1Cfg0, 17:14, secure_scratch43, 28:25); + s(McGeneralizedCarveout3Cfg0, 13:11, secure_scratch43, 31:29); + s(EmcCmdMappingCmd3_2, 6:0, secure_scratch44, 6:0); + s(EmcCmdMappingCmd3_2, 14:8, secure_scratch44, 13:7); + s(EmcCmdMappingCmd3_2, 22:16, secure_scratch44, 20:14); + s(EmcCmdMappingCmd3_2, 27:24, secure_scratch44, 24:21); + s(McGeneralizedCarveout1Cfg0, 21:18, secure_scratch44, 28:25); + s(McVideoProtectVprOverride, 3:2, secure_scratch44, 30:29); + s(McVideoProtectVprOverride, 6:6, secure_scratch44, 31:31); + s(McEmemAdrCfgChannelMask, 31:9, secure_scratch45, 22:0); + s(McEmemAdrCfgDev0, 2:0, secure_scratch45, 25:23); + s(McEmemAdrCfgDev0, 9:8, secure_scratch45, 27:26); + s(McEmemAdrCfgDev0, 19:16, secure_scratch45, 31:28); + s(McEmemAdrCfgBankMask0, 31:10, secure_scratch46, 21:0); + s(McEmemAdrCfgDev1, 2:0, secure_scratch46, 24:22); + s(McEmemAdrCfgDev1, 9:8, secure_scratch46, 26:25); + s(McEmemAdrCfgDev1, 19:16, secure_scratch46, 30:27); + s(McVideoProtectVprOverride, 7:7, secure_scratch46, 31:31); + s(McEmemAdrCfgBankMask1, 31:10, secure_scratch47, 21:0); + s(McGeneralizedCarveout3Cfg0, 10:3, secure_scratch47, 29:22); + s(McVideoProtectVprOverride, 9:8, secure_scratch47, 31:30); + s(McEmemAdrCfgBankMask2, 31:10, secure_scratch48, 21:0); + s(McGeneralizedCarveout3Cfg0, 21:14, secure_scratch48, 29:22); + s(McVideoProtectVprOverride, 11:11, secure_scratch48, 30:30); + s(McVideoProtectVprOverride, 14:14, secure_scratch48, 31:31); + s(McVideoProtectGpuOverride1, 15:0, secure_scratch49, 15:0); + s(McEmemCfg, 13:0, secure_scratch49, 29:16); + s(McEmemCfg, 31:31, secure_scratch49, 30:30); + s(McVideoProtectVprOverride, 15:15, secure_scratch49, 31:31); + s(McGeneralizedCarveout3Bom, 31:17, secure_scratch50, 14:0); + s(McGeneralizedCarveout1Bom, 31:17, secure_scratch50, 29:15); + s(McVideoProtectVprOverride, 18:17, secure_scratch50, 31:30); + s(McGeneralizedCarveout4Bom, 31:17, secure_scratch51, 14:0); + s(McGeneralizedCarveout2Bom, 31:17, secure_scratch51, 29:15); + s(McVideoProtectVprOverride, 20:19, secure_scratch51, 31:30); + s(McGeneralizedCarveout5Bom, 31:17, secure_scratch52, 14:0); + s(McVideoProtectBom, 31:20, secure_scratch52, 26:15); + s(McVideoProtectVprOverride, 23:21, secure_scratch52, 29:27); + s(McVideoProtectVprOverride, 26:26, secure_scratch52, 30:30); + s(McVideoProtectVprOverride, 29:29, secure_scratch52, 31:31); + s(McVideoProtectSizeMb, 11:0, secure_scratch53, 11:0); + s(McSecCarveoutBom, 31:20, secure_scratch53, 23:12); + s(McVideoProtectVprOverride, 31:30, secure_scratch53, 25:24); + s(McVideoProtectVprOverride1, 1:0, secure_scratch53, 27:26); + s(McVideoProtectVprOverride1, 7:4, secure_scratch53, 31:28); + s(McSecCarveoutSizeMb, 11:0, secure_scratch54, 11:0); + s(McMtsCarveoutBom, 31:20, secure_scratch54, 23:12); + s(McVideoProtectVprOverride1, 15:8, secure_scratch54, 31:24); + s(McMtsCarveoutSizeMb, 11:0, secure_scratch55, 11:0); + s(McGeneralizedCarveout4Size128kb, 11:0, secure_scratch55, 23:12); + s(McVideoProtectVprOverride1, 16:16, secure_scratch55, 24:24); + s(McGeneralizedCarveout2Cfg0, 2:0, secure_scratch55, 27:25); + s(McGeneralizedCarveout2Cfg0, 25:22, secure_scratch55, 31:28); + s(McGeneralizedCarveout3Size128kb, 11:0, secure_scratch56, 11:0); + s(McGeneralizedCarveout2Size128kb, 11:0, secure_scratch56, 23:12); + s(McGeneralizedCarveout2Cfg0, 26:26, secure_scratch56, 24:24); + s(McGeneralizedCarveout1Cfg0, 2:0, secure_scratch56, 27:25); + s(McGeneralizedCarveout1Cfg0, 25:22, secure_scratch56, 31:28); + s(McGeneralizedCarveout1Size128kb, 11:0, secure_scratch57, 11:0); + s(McGeneralizedCarveout5Size128kb, 11:0, secure_scratch57, 23:12); + s(McGeneralizedCarveout1Cfg0, 26:26, secure_scratch57, 24:24); + s(McGeneralizedCarveout3Cfg0, 2:0, secure_scratch57, 27:25); + s(McGeneralizedCarveout3Cfg0, 25:22, secure_scratch57, 31:28); + s(McGeneralizedCarveout3Cfg0, 26:26, secure_scratch58, 0:0); + + s32(McGeneralizedCarveout1Access0, secure_scratch59); + s32(McGeneralizedCarveout1Access1, secure_scratch60); + s32(McGeneralizedCarveout1Access2, secure_scratch61); + s32(McGeneralizedCarveout1Access3, secure_scratch62); + s32(McGeneralizedCarveout1Access4, secure_scratch63); + s32(McGeneralizedCarveout2Access0, secure_scratch64); + s32(McGeneralizedCarveout2Access1, secure_scratch65); + s32(McGeneralizedCarveout2Access2, secure_scratch66); + s32(McGeneralizedCarveout2Access3, secure_scratch67); + s32(McGeneralizedCarveout2Access4, secure_scratch68); + s32(McGeneralizedCarveout3Access0, secure_scratch69); + s32(McGeneralizedCarveout3Access1, secure_scratch70); + s32(McGeneralizedCarveout3Access2, secure_scratch71); + s32(McGeneralizedCarveout3Access3, secure_scratch72); + s32(McGeneralizedCarveout3Access4, secure_scratch73); + s32(McGeneralizedCarveout4Access0, secure_scratch74); + s32(McGeneralizedCarveout4Access1, secure_scratch75); + s32(McGeneralizedCarveout4Access2, secure_scratch76); + s32(McGeneralizedCarveout4Access3, secure_scratch77); + s32(McGeneralizedCarveout4Access4, secure_scratch78); + s32(McGeneralizedCarveout5Access0, secure_scratch79); + s32(McGeneralizedCarveout5Access1, secure_scratch80); + s32(McGeneralizedCarveout5Access2, secure_scratch81); + s32(McGeneralizedCarveout5Access3, secure_scratch82); + s32(McGeneralizedCarveout1ForceInternalAccess0, secure_scratch84); + s32(McGeneralizedCarveout1ForceInternalAccess1, secure_scratch85); + s32(McGeneralizedCarveout1ForceInternalAccess2, secure_scratch86); + s32(McGeneralizedCarveout1ForceInternalAccess3, secure_scratch87); + s32(McGeneralizedCarveout1ForceInternalAccess4, secure_scratch88); + s32(McGeneralizedCarveout2ForceInternalAccess0, secure_scratch89); + s32(McGeneralizedCarveout2ForceInternalAccess1, secure_scratch90); + s32(McGeneralizedCarveout2ForceInternalAccess2, secure_scratch91); + s32(McGeneralizedCarveout2ForceInternalAccess3, secure_scratch92); + s32(McGeneralizedCarveout2ForceInternalAccess4, secure_scratch93); + s32(McGeneralizedCarveout3ForceInternalAccess0, secure_scratch94); + s32(McGeneralizedCarveout3ForceInternalAccess1, secure_scratch95); + s32(McGeneralizedCarveout3ForceInternalAccess2, secure_scratch96); + s32(McGeneralizedCarveout3ForceInternalAccess3, secure_scratch97); + s32(McGeneralizedCarveout3ForceInternalAccess4, secure_scratch98); + s32(McGeneralizedCarveout4ForceInternalAccess0, secure_scratch99); + s32(McGeneralizedCarveout4ForceInternalAccess1, secure_scratch100); + s32(McGeneralizedCarveout4ForceInternalAccess2, secure_scratch101); + s32(McGeneralizedCarveout4ForceInternalAccess3, secure_scratch102); + s32(McGeneralizedCarveout4ForceInternalAccess4, secure_scratch103); + s32(McGeneralizedCarveout5ForceInternalAccess0, secure_scratch104); + s32(McGeneralizedCarveout5ForceInternalAccess1, secure_scratch105); + s32(McGeneralizedCarveout5ForceInternalAccess2, secure_scratch106); + s32(McGeneralizedCarveout5ForceInternalAccess3, secure_scratch107); + + c32(0, scratch2); + s(PllMInputDivider, 7:0, scratch2, 7:0); + s(PllMFeedbackDivider, 7:0, scratch2, 15:8); + s(PllMPostDivider, 4:0, scratch2, 20:16); + s(PllMKVCO, 0:0, scratch2, 21:21); + s(PllMKCP, 1:0, scratch2, 23:22); + + c32(0, scratch35); + s(PllMSetupControl, 15:0, scratch35, 15:0); + + c32(0, scratch3); + s(PllMInputDivider, 7:0, scratch3, 7:0); + c(0x3e, scratch3, 15:8); + c(0, scratch3, 20:16); + s(PllMKVCO, 0:0, scratch3, 21:21); + s(PllMKCP, 1:0, scratch3, 23:22); + + c32(0, scratch36); + s(PllMSetupControl, 23:0, scratch36, 23:0); + + c32(0, scratch4); + s(PllMStableTime, 9:0, scratch4, 9:0); +} + +void sdram_save_params_mariko(const void *save_params) { + /* TODO */ +} \ No newline at end of file diff --git a/sept/sept-secondary/src/sdram.h b/sept/sept-secondary/src/sdram.h index 98e3b0990..5e81ac279 100644 --- a/sept/sept-secondary/src/sdram.h +++ b/sept/sept-secondary/src/sdram.h @@ -18,8 +18,11 @@ #ifndef FUSEE_SDRAM_H_ #define FUSEE_SDRAM_H_ -void sdram_init(); -const void *sdram_get_params(); -void sdram_lp0_save_params(const void *params); +void sdram_init_erista(void); +void sdram_init_mariko(void); +const void *sdram_get_params_erista(uint32_t dram_id); +const void *sdram_get_params_mariko(uint32_t dram_id); +void sdram_save_params_erista(const void *save_params); +void sdram_save_params_mariko(const void *save_params); #endif diff --git a/sept/sept-secondary/src/sdram.inl b/sept/sept-secondary/src/sdram.inl index 845ad1161..0036c0ca7 100644 --- a/sept/sept-secondary/src/sdram.inl +++ b/sept/sept-secondary/src/sdram.inl @@ -1,5 +1,6 @@ /* * Copyright (c) 2018 naehrwert + * Copyright (c) 2018-2020 Atmosphère-NX * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -14,7 +15,7 @@ * along with this program. If not, see . */ -static const uint8_t _dram_cfg_0[1896] = { +static const uint8_t sdram_params_erista_0[1896] = { 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -175,7 +176,7 @@ static const uint8_t _dram_cfg_0[1896] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -static const uint8_t _dram_cfg_1[1896] = { +static const uint8_t sdram_params_erista_1[1896] = { 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -336,7 +337,7 @@ static const uint8_t _dram_cfg_1[1896] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -static const uint8_t _dram_cfg_2[1896] = { +static const uint8_t sdram_params_erista_2[1896] = { 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -497,7 +498,7 @@ static const uint8_t _dram_cfg_2[1896] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -static const uint8_t _dram_cfg_3[1896] = { +static const uint8_t sdram_params_erista_3[1896] = { 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -658,7 +659,7 @@ static const uint8_t _dram_cfg_3[1896] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -static const uint8_t _dram_cfg_4[1896] = { +static const uint8_t sdram_params_erista_4[1896] = { 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -819,7 +820,7 @@ static const uint8_t _dram_cfg_4[1896] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -static const uint8_t _dram_cfg_5[1896] = { +static const uint8_t sdram_params_erista_5[1896] = { 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -980,7 +981,7 @@ static const uint8_t _dram_cfg_5[1896] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -static const uint8_t _dram_cfg_6[1896] = { +static const uint8_t sdram_params_erista_6[1896] = { 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1141,12 +1142,2237 @@ static const uint8_t _dram_cfg_6[1896] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -static const uint32_t *_dram_cfgs[7] = { - (const uint32_t *)_dram_cfg_0, - (const uint32_t *)_dram_cfg_1, - (const uint32_t *)_dram_cfg_2, - (const uint32_t *)_dram_cfg_3, - (const uint32_t *)_dram_cfg_4, - (const uint32_t *)_dram_cfg_5, - (const uint32_t *)_dram_cfg_6 +static const uint8_t sdram_params_mariko_0[2104] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x40, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00, 0x20, 0x12, 0x00, 0x00, + 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xBC, 0xBC, 0xC5, 0xB3, 0x3C, 0x9E, 0x00, 0x00, + 0x02, 0x03, 0xE0, 0xC1, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, + 0x04, 0x04, 0x04, 0x04, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x3F, 0x3F, 0x20, 0x12, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, + 0x50, 0x50, 0x50, 0x00, 0xA1, 0x01, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, + 0x00, 0x10, 0x00, 0x16, 0x00, 0x10, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, + 0x3A, 0x00, 0x00, 0x00, 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, + 0x17, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x20, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, + 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x0E, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, + 0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, + 0x1A, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, + 0x0A, 0x00, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xC1, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x14, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x2C, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t sdram_params_mariko_1[2104] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x2C, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t sdram_params_mariko_2[2104] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 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0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x2C, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t sdram_params_mariko_3[2104] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, + 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00, 0x20, 0x12, 0x00, 0x00, + 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xBC, 0xBC, 0xC5, 0xB3, 0x3C, 0x9E, 0x00, 0x00, + 0x02, 0x03, 0xE0, 0xC1, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, + 0x04, 0x04, 0x04, 0x04, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x3F, 0x3F, 0x20, 0x12, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, + 0x50, 0x50, 0x50, 0x00, 0xA1, 0x01, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, + 0x00, 0x10, 0x00, 0x16, 0x00, 0x10, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, + 0x3A, 0x00, 0x00, 0x00, 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x08, 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0x00, + 0x03, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x14, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x3B, 0x00, 0x00, 0x00, 0x3B, 0x00, 0x00, 0x00, + 0x05, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91, + 0x3F, 0x3A, 0x00, 0x00, 0x00, 0x00, 0xF3, 0x0C, 0x04, 0x05, 0x1B, 0x06, + 0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A, + 0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03, 0x02, 0x1B, 0x1C, 0x23, + 0x03, 0x04, 0x07, 0x05, 0x06, 0x25, 0x25, 0x02, 0x0A, 0x0B, 0x1D, 0x0D, + 0x08, 0x0C, 0x09, 0x1E, 0x24, 0x26, 0x26, 0x08, 0x24, 0x06, 0x07, 0x9A, + 0x12, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x01, 0x88, 0x00, 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0x29, + 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x16, 0x00, 0x0D, 0x00, 0x0B, 0x00, 0x17, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x16, 0x00, 0x0D, 0x00, 0x0B, 0x00, 0x17, 0x00, + 0x43, 0x00, 0x45, 0x00, 0x45, 0x00, 0x43, 0x00, 0x46, 0x00, 0x47, 0x00, + 0x41, 0x00, 0x46, 0x00, 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0D, 0x00, + 0x43, 0x00, 0x45, 0x00, 0x45, 0x00, 0x43, 0x00, 0x46, 0x00, 0x47, 0x00, + 0x41, 0x00, 0x46, 0x00, 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0D, 0x00, + 0x28, 0x00, 0x28, 0x00, 0x28, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x2C, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t sdram_params_mariko_4[2104] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x2C, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t sdram_params_mariko_5[2104] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 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0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x2C, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t sdram_params_mariko_9[2104] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 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0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x76, 0x0C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x16, 0x40, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x7E, 0x1E, 0x40, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x2C, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t sdram_params_mariko_10[2104] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x40, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 0x50, 0x05, + 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00, 0x20, 0x12, 0x00, 0x00, + 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x88, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xBC, 0xBC, 0xAF, 0xC9, 0x3C, 0x9E, 0x00, 0x00, + 0x02, 0x03, 0xE0, 0xC1, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, + 0x04, 0x04, 0x04, 0x04, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x3F, 0x3F, 0x20, 0x12, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, + 0x50, 0x50, 0x50, 0x00, 0xA1, 0x01, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, + 0x00, 0x10, 0x00, 0x16, 0x00, 0x10, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, + 0x3A, 0x00, 0x00, 0x00, 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, + 0x17, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x20, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, + 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x0E, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, + 0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, + 0x1A, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, + 0x0A, 0x00, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xC1, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x14, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x3B, 0x00, 0x00, 0x00, 0x3B, 0x00, 0x00, 0x00, + 0x05, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91, + 0x3F, 0x3A, 0x00, 0x00, 0x00, 0x00, 0xF3, 0x0C, 0x06, 0x1B, 0x04, 0x1C, + 0x07, 0x03, 0x05, 0x02, 0x00, 0x25, 0x25, 0x03, 0x00, 0x1E, 0x1D, 0x08, + 0x0D, 0x0A, 0x0C, 0x09, 0x0B, 0x26, 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0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t sdram_params_mariko_11[2104] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const uint32_t sdram_params_index_table_erista[28] = { + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, +}; + +static const uint32_t *sdram_params_erista[7] = { + (const uint32_t *)sdram_params_erista_0, + (const uint32_t *)sdram_params_erista_1, + (const uint32_t *)sdram_params_erista_2, + (const uint32_t *)sdram_params_erista_3, + (const uint32_t *)sdram_params_erista_4, + (const uint32_t *)sdram_params_erista_5, + (const uint32_t *)sdram_params_erista_6, +}; + +static const uint32_t sdram_params_index_table_mariko[28] = { + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0, + 1, + 2, + 3, + 4, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 6, + 8, + 9, + 0xA, + 7, + 6, + 0xB, + 0xB, + 0xB, +}; + +static const uint32_t *sdram_params_mariko[12] = { + (const uint32_t *)sdram_params_mariko_0, + (const uint32_t *)sdram_params_mariko_1, + (const uint32_t *)sdram_params_mariko_2, + (const uint32_t *)sdram_params_mariko_3, + (const uint32_t *)sdram_params_mariko_4, + (const uint32_t *)sdram_params_mariko_5, + (const uint32_t *)sdram_params_mariko_6, + (const uint32_t *)sdram_params_mariko_7, + (const uint32_t *)sdram_params_mariko_8, + (const uint32_t *)sdram_params_mariko_9, + (const uint32_t *)sdram_params_mariko_10, + (const uint32_t *)sdram_params_mariko_11, }; diff --git a/sept/sept-secondary/src/sdram_lp0.c b/sept/sept-secondary/src/sdram_lp0.c deleted file mode 100644 index 12864e63c..000000000 --- a/sept/sept-secondary/src/sdram_lp0.c +++ /dev/null @@ -1,1125 +0,0 @@ -/* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * Copyright 2014 Google Inc. - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 CTCaer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include "pmc.h" -#include "sdram_param_t210_lp0.h" - -/* - * This function reads SDRAM parameters from the common BCT format and - * writes them into PMC scratch registers (where the BootROM expects them - * on LP0 resume). - */ -void sdram_lp0_save_params(const void *params) -{ - struct sdram_params *sdram = (struct sdram_params *)params; - volatile tegra_pmc_t *pmc = pmc_get_regs(); - -#define pack(src, src_bits, dst, dst_bits) { \ - uint32_t mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \ - dst &= ~(mask << (0 ? dst_bits)); \ - dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \ -} - -#define s(param, src_bits, pmcreg, dst_bits) \ - pack(sdram->param, src_bits, pmc->pmcreg, dst_bits) - -#define c(value, pmcreg, dst_bits) \ - pack(value, (1 ? dst_bits) - (0 ? dst_bits) : 0, pmc->pmcreg, dst_bits) - -/* 32 bits version of s macro */ -#define s32(param, pmcreg) pmc->pmcreg = sdram->param - -/* 32 bits version c macro */ -#define c32(value, pmcreg) pmc->pmcreg = value - - //TODO: pkg1.1 (1.X - 3.X) reads them from MC. - // Patch carveout parameters. - /*sdram->McGeneralizedCarveout1Bom = 0; - sdram->McGeneralizedCarveout1BomHi = 0; - sdram->McGeneralizedCarveout1Size128kb = 0; - sdram->McGeneralizedCarveout1Access0 = 0; - sdram->McGeneralizedCarveout1Access1 = 0; - sdram->McGeneralizedCarveout1Access2 = 0; - sdram->McGeneralizedCarveout1Access3 = 0; - sdram->McGeneralizedCarveout1Access4 = 0; - sdram->McGeneralizedCarveout1ForceInternalAccess0 = 0; - sdram->McGeneralizedCarveout1ForceInternalAccess1 = 0; - sdram->McGeneralizedCarveout1ForceInternalAccess2 = 0; - sdram->McGeneralizedCarveout1ForceInternalAccess3 = 0; - sdram->McGeneralizedCarveout1ForceInternalAccess4 = 0; - sdram->McGeneralizedCarveout1Cfg0 = 0; - sdram->McGeneralizedCarveout2Bom = 0x80020000; - sdram->McGeneralizedCarveout2BomHi = 0; - sdram->McGeneralizedCarveout2Size128kb = 2; - sdram->McGeneralizedCarveout2Access0 = 0; - sdram->McGeneralizedCarveout2Access1 = 0; - sdram->McGeneralizedCarveout2Access2 = 0x3000000; - sdram->McGeneralizedCarveout2Access3 = 0; - sdram->McGeneralizedCarveout2Access4 = 0x300; - sdram->McGeneralizedCarveout2ForceInternalAccess0 = 0; - sdram->McGeneralizedCarveout2ForceInternalAccess1 = 0; - sdram->McGeneralizedCarveout2ForceInternalAccess2 = 0; - sdram->McGeneralizedCarveout2ForceInternalAccess3 = 0; - sdram->McGeneralizedCarveout2ForceInternalAccess4 = 0; - sdram->McGeneralizedCarveout2Cfg0 = 0x440167E; - sdram->McGeneralizedCarveout3Bom = 0; - sdram->McGeneralizedCarveout3BomHi = 0; - sdram->McGeneralizedCarveout3Size128kb = 0; - sdram->McGeneralizedCarveout3Access0 = 0; - sdram->McGeneralizedCarveout3Access1 = 0; - sdram->McGeneralizedCarveout3Access2 = 0x3000000; - sdram->McGeneralizedCarveout3Access3 = 0; - sdram->McGeneralizedCarveout3Access4 = 0x300; - sdram->McGeneralizedCarveout3ForceInternalAccess0 = 0; - sdram->McGeneralizedCarveout3ForceInternalAccess1 = 0; - sdram->McGeneralizedCarveout3ForceInternalAccess2 = 0; - sdram->McGeneralizedCarveout3ForceInternalAccess3 = 0; - sdram->McGeneralizedCarveout3ForceInternalAccess4 = 0; - sdram->McGeneralizedCarveout3Cfg0 = 0x4401E7E; - sdram->McGeneralizedCarveout4Bom = 0; - sdram->McGeneralizedCarveout4BomHi = 0; - sdram->McGeneralizedCarveout4Size128kb = 0; - sdram->McGeneralizedCarveout4Access0 = 0; - sdram->McGeneralizedCarveout4Access1 = 0; - sdram->McGeneralizedCarveout4Access2 = 0; - sdram->McGeneralizedCarveout4Access3 = 0; - sdram->McGeneralizedCarveout4Access4 = 0; - sdram->McGeneralizedCarveout4ForceInternalAccess0 = 0; - sdram->McGeneralizedCarveout4ForceInternalAccess1 = 0; - sdram->McGeneralizedCarveout4ForceInternalAccess2 = 0; - sdram->McGeneralizedCarveout4ForceInternalAccess3 = 0; - sdram->McGeneralizedCarveout4ForceInternalAccess4 = 0; - sdram->McGeneralizedCarveout4Cfg0 = 0x8F; - sdram->McGeneralizedCarveout5Bom = 0; - sdram->McGeneralizedCarveout5BomHi = 0; - sdram->McGeneralizedCarveout5Size128kb = 0; - sdram->McGeneralizedCarveout5Access0 = 0; - sdram->McGeneralizedCarveout5Access1 = 0; - sdram->McGeneralizedCarveout5Access2 = 0; - sdram->McGeneralizedCarveout5Access3 = 0; - sdram->McGeneralizedCarveout5Access4 = 0; - sdram->McGeneralizedCarveout5ForceInternalAccess0 = 0; - sdram->McGeneralizedCarveout5ForceInternalAccess1 = 0; - sdram->McGeneralizedCarveout5ForceInternalAccess2 = 0; - sdram->McGeneralizedCarveout5ForceInternalAccess3 = 0; - sdram->McGeneralizedCarveout5ForceInternalAccess4 = 0; - sdram->McGeneralizedCarveout5Cfg0 = 0x8F;*/ - - //TODO: this is 4.X+ behaviour which seems to work fine for < 4.X. - // Patch carveout parameters. - sdram->McGeneralizedCarveout1Cfg0 = 0; - sdram->McGeneralizedCarveout2Cfg0 = 0; - sdram->McGeneralizedCarveout3Cfg0 = 0; - sdram->McGeneralizedCarveout4Cfg0 = 0; - sdram->McGeneralizedCarveout5Cfg0 = 0; - - // Patch SDRAM parameters. - uint32_t t0 = sdram->EmcSwizzleRank0Byte0 << 5 >> 29 > sdram->EmcSwizzleRank0Byte0 << 1 >> 29; - uint32_t t1 = (t0 & 0xFFFFFFEF) | ((sdram->EmcSwizzleRank1Byte0 << 5 >> 29 > sdram->EmcSwizzleRank1Byte0 << 1 >> 29) << 4); - uint32_t t2 = (t1 & 0xFFFFFFFD) | ((sdram->EmcSwizzleRank0Byte1 << 5 >> 29 > sdram->EmcSwizzleRank0Byte1 << 1 >> 29) << 1); - uint32_t t3 = (t2 & 0xFFFFFFDF) | ((sdram->EmcSwizzleRank1Byte1 << 5 >> 29 > sdram->EmcSwizzleRank1Byte1 << 1 >> 29) << 5); - uint32_t t4 = (t3 & 0xFFFFFFFB) | ((sdram->EmcSwizzleRank0Byte2 << 5 >> 29 > sdram->EmcSwizzleRank0Byte2 << 1 >> 29) << 2); - uint32_t t5 = (t4 & 0xFFFFFFBF) | ((sdram->EmcSwizzleRank1Byte2 << 5 >> 29 > sdram->EmcSwizzleRank1Byte2 << 1 >> 29) << 6); - uint32_t t6 = (t5 & 0xFFFFFFF7) | ((sdram->EmcSwizzleRank0Byte3 << 5 >> 29 > sdram->EmcSwizzleRank0Byte3 << 1 >> 29) << 3); - uint32_t t7 = (t6 & 0xFFFFFF7F) | ((sdram->EmcSwizzleRank1Byte3 << 5 >> 29 > sdram->EmcSwizzleRank1Byte3 << 1 >> 29) << 7); - sdram->SwizzleRankByteEncode = t7; - sdram->EmcBctSpare2 = 0x40000DD8; - sdram->EmcBctSpare3 = t7; - - s(EmcClockSource, 7:0, scratch6, 15:8); - s(EmcClockSourceDll, 7:0, scratch6, 23:16); - s(EmcClockSource, 31:29, scratch6, 26:24); - s(EmcClockSourceDll, 31:29, scratch6, 29:27); - s(EmcClockSourceDll, 11:10, scratch6, 31:30); - s(ClkRstControllerPllmMisc2Override, 9:8, scratch7, 1:0); - s(ClkRstControllerPllmMisc2Override, 2:1, scratch7, 3:2); - s(EmcZqCalLpDdr4WarmBoot, 31:30, scratch7, 5:4); - s(EmcClockSource, 15:15, scratch7, 6:6); - s(EmcClockSource, 26:26, scratch7, 7:7); - s(EmcClockSource, 20:20, scratch7, 8:8); - s(EmcClockSource, 19:19, scratch7, 9:9); - s(ClkRstControllerPllmMisc2Override, 13:13, scratch7, 10:10); - s(ClkRstControllerPllmMisc2Override, 12:12, scratch7, 11:11); - s(ClkRstControllerPllmMisc2Override, 11:11, scratch7, 12:12); - s(ClkRstControllerPllmMisc2Override, 10:10, scratch7, 13:13); - s(ClkRstControllerPllmMisc2Override, 5:5, scratch7, 14:14); - s(ClkRstControllerPllmMisc2Override, 4:4, scratch7, 15:15); - s(ClkRstControllerPllmMisc2Override, 3:3, scratch7, 16:16); - s(ClkRstControllerPllmMisc2Override, 0:0, scratch7, 17:17); - s(EmcZqCalLpDdr4WarmBoot, 1:0, scratch7, 19:18); - s(EmcZqCalLpDdr4WarmBoot, 4:4, scratch7, 20:20); - s(EmcOdtWrite, 5:0, scratch7, 26:21); - s(EmcOdtWrite, 11:8, scratch7, 30:27); - s(EmcOdtWrite, 31:31, scratch7, 31:31); - s(EmcFdpdCtrlCmdNoRamp, 0:0, scratch13, 30:30); - s(EmcCfgPipeClk, 0:0, scratch13, 31:31); - s(McEmemArbMisc2, 0:0, scratch14, 30:30); - s(McDaCfg0, 0:0, scratch14, 31:31); - s(EmcQRst, 6:0, scratch15, 26:20); - s(EmcQRst, 20:16, scratch15, 31:27); - s(EmcPmacroCmdTxDrv, 5:0, scratch16, 25:20); - s(EmcPmacroCmdTxDrv, 13:8, scratch16, 31:26); - s(EmcPmacroAutocalCfg0, 2:0, scratch17, 22:20); - s(EmcPmacroAutocalCfg0, 10:8, scratch17, 25:23); - s(EmcPmacroAutocalCfg0, 18:16, scratch17, 28:26); - s(EmcPmacroAutocalCfg0, 26:24, scratch17, 31:29); - s(EmcPmacroAutocalCfg1, 2:0, scratch18, 22:20); - s(EmcPmacroAutocalCfg1, 10:8, scratch18, 25:23); - s(EmcPmacroAutocalCfg1, 18:16, scratch18, 28:26); - s(EmcPmacroAutocalCfg1, 26:24, scratch18, 31:29); - s(EmcPmacroAutocalCfg2, 2:0, scratch19, 22:20); - s(EmcPmacroAutocalCfg2, 10:8, scratch19, 25:23); - s(EmcPmacroAutocalCfg2, 18:16, scratch19, 28:26); - s(EmcPmacroAutocalCfg2, 26:24, scratch19, 31:29); - s32(EmcCfgRsv,scratch22); - s32(EmcAutoCalConfig, scratch23); - s32(EmcAutoCalVrefSel0, scratch24); - s32(EmcPmacroBrickCtrlRfu1, scratch25); - s32(EmcPmacroBrickCtrlRfu2, scratch26); - s32(EmcPmcScratch1, scratch27); - s32(EmcPmcScratch2, scratch28); - s32(EmcPmcScratch3, scratch29); - s32(McEmemArbDaTurns, scratch30); - s(EmcFbioSpare, 31:24, scratch58, 7:0); - s(EmcFbioSpare, 23:16, scratch58, 15:8); - s(EmcFbioSpare, 15:8, scratch58, 23:16); - s(EmcFbioSpare, 7:2, scratch58, 29:24); - s(EmcFbioSpare, 0:0, scratch58, 30:30); - s(EmcDllCfg0, 29:0, scratch59, 29:0); - s(EmcPmacroDdllBypass, 11:0, scratch60, 11:0); - s(EmcPmacroDdllBypass, 27:13, scratch60, 26:12); - s(EmcPmacroDdllBypass, 31:29, scratch60, 29:27); - s(McEmemArbMisc0, 14:0, scratch61, 14:0); - s(McEmemArbMisc0, 30:16, scratch61, 29:15); - s(EmcFdpdCtrlCmd, 16:0, scratch62, 16:0); - s(EmcFdpdCtrlCmd, 31:20, scratch62, 28:17); - s(EmcAutoCalConfig2, 27:0, scratch63, 27:0); - s(EmcBurstRefreshNum, 3:0, scratch63, 31:28); - s(EmcPmacroZctrl, 27:0, scratch64, 27:0); - s(EmcTppd, 3:0, scratch64, 31:28); - s(EmcCfgDigDll, 10:0, scratch65, 10:0); - s(EmcCfgDigDll, 25:12, scratch65, 24:11); - s(EmcCfgDigDll, 27:27, scratch65, 25:25); - s(EmcCfgDigDll, 31:30, scratch65, 27:26); - s(EmcR2r, 3:0, scratch65, 31:28); - s(EmcFdpdCtrlDq, 16:0, scratch66, 16:0); - s(EmcFdpdCtrlDq, 28:20, scratch66, 25:17); - s(EmcFdpdCtrlDq, 31:30, scratch66, 27:26); - s(EmcW2w, 3:0, scratch66, 31:28); - s(EmcPmacroTxPwrd4, 13:0, scratch67, 13:0); - s(EmcPmacroTxPwrd4, 29:16, scratch67, 27:14); - s(EmcPmacroCommonPadTxCtrl, 3:0, scratch67, 31:28); - s(EmcPmacroTxPwrd5, 13:0, scratch68, 13:0); - s(EmcPmacroTxPwrd5, 29:16, scratch68, 27:14); - s(EmcPmacroDdllPwrd0, 4:0, scratch69, 4:0); - s(EmcPmacroDdllPwrd0, 12:6, scratch69, 11:5); - s(EmcPmacroDdllPwrd0, 20:14, scratch69, 18:12); - s(EmcPmacroDdllPwrd0, 28:22, scratch69, 25:19); - s(EmcPmacroDdllPwrd0, 31:30, scratch69, 27:26); - s(EmcCfg, 4:4, scratch69, 31:31); - s(EmcPmacroDdllPwrd1, 4:0, scratch70, 4:0); - s(EmcPmacroDdllPwrd1, 12:6, scratch70, 11:5); - s(EmcPmacroDdllPwrd1, 20:14, scratch70, 18:12); - s(EmcPmacroDdllPwrd1, 28:22, scratch70, 25:19); - s(EmcPmacroDdllPwrd1, 31:30, scratch70, 27:26); - s(EmcCfg, 5:5, scratch70, 31:31); - s(EmcPmacroDdllPwrd2, 4:0, scratch71, 4:0); - s(EmcPmacroDdllPwrd2, 12:6, scratch71, 11:5); - s(EmcPmacroDdllPwrd2, 20:14, scratch71, 18:12); - s(EmcPmacroDdllPwrd2, 28:22, scratch71, 25:19); - s(EmcPmacroDdllPwrd2, 31:30, scratch71, 27:26); - s(EmcFbioCfg5, 23:20, scratch71, 31:28); - s(EmcPmacroIbVrefDq_0, 6:0, scratch72, 6:0); - s(EmcPmacroIbVrefDq_0, 14:8, scratch72, 13:7); - s(EmcPmacroIbVrefDq_0, 22:16, scratch72, 20:14); - s(EmcPmacroIbVrefDq_0, 30:24, scratch72, 27:21); - s(EmcFbioCfg5, 15:13, scratch72, 30:28); - s(EmcCfg, 6:6, scratch72, 31:31); - s(EmcPmacroIbVrefDq_1, 6:0, scratch73, 6:0); - s(EmcPmacroIbVrefDq_1, 14:8, scratch73, 13:7); - s(EmcPmacroIbVrefDq_1, 22:16, scratch73, 20:14); - s(EmcPmacroIbVrefDq_1, 30:24, scratch73, 27:21); - s(EmcCfg2, 5:3, scratch73, 30:28); - s(EmcCfg, 7:7, scratch73, 31:31); - s(EmcPmacroIbVrefDqs_0, 6:0, scratch74, 6:0); - s(EmcPmacroIbVrefDqs_0, 14:8, scratch74, 13:7); - s(EmcPmacroIbVrefDqs_0, 22:16, scratch74, 20:14); - s(EmcPmacroIbVrefDqs_0, 30:24, scratch74, 27:21); - s(EmcCfg, 17:16, scratch74, 29:28); - s(EmcFbioCfg5, 1:0, scratch74, 31:30); - s(EmcPmacroIbVrefDqs_1, 6:0, scratch75, 6:0); - s(EmcPmacroIbVrefDqs_1, 14:8, scratch75, 13:7); - s(EmcPmacroIbVrefDqs_1, 22:16, scratch75, 20:14); - s(EmcPmacroIbVrefDqs_1, 30:24, scratch75, 27:21); - s(EmcFbioCfg5, 3:2, scratch75, 29:28); - s(EmcCfg2, 27:26, scratch75, 31:30); - s(EmcPmacroDdllShortCmd_0, 6:0, scratch76, 6:0); - s(EmcPmacroDdllShortCmd_0, 14:8, scratch76, 13:7); - s(EmcPmacroDdllShortCmd_0, 22:16, scratch76, 20:14); - s(EmcPmacroDdllShortCmd_0, 30:24, scratch76, 27:21); - s(EmcPmacroCmdPadTxCtrl, 3:2, scratch76, 29:28); - s(EmcPmacroCmdPadTxCtrl, 7:6, scratch76, 31:30); - s(EmcPmacroDdllShortCmd_1, 6:0, scratch77, 6:0); - s(EmcPmacroDdllShortCmd_1, 14:8, scratch77, 13:7); - s(EmcPmacroDdllShortCmd_1, 22:16, scratch77, 20:14); - s(EmcPmacroDdllShortCmd_1, 30:24, scratch77, 27:21); - s(EmcPmacroCmdPadTxCtrl, 11:10, scratch77, 29:28); - s(EmcPmacroCmdPadTxCtrl, 15:14, scratch77, 31:30); - s(EmcAutoCalChannel, 5:0, scratch78, 5:0); - s(EmcAutoCalChannel, 11:8, scratch78, 9:6); - s(EmcAutoCalChannel, 27:16, scratch78, 21:10); - s(EmcAutoCalChannel, 31:29, scratch78, 24:22); - s(EmcConfigSampleDelay, 6:0, scratch78, 31:25); - s(EmcPmacroRxTerm, 5:0, scratch79, 5:0); - s(EmcPmacroRxTerm, 13:8, scratch79, 11:6); - s(EmcPmacroRxTerm, 21:16, scratch79, 17:12); - s(EmcPmacroRxTerm, 29:24, scratch79, 23:18); - s(EmcRc, 7:0, scratch79, 31:24); - s(EmcPmacroDqTxDrv, 5:0, scratch80, 5:0); - s(EmcPmacroDqTxDrv, 13:8, scratch80, 11:6); - s(EmcPmacroDqTxDrv, 21:16, scratch80, 17:12); - s(EmcPmacroDqTxDrv, 29:24, scratch80, 23:18); - s(EmcSelDpdCtrl, 5:2, scratch80, 27:24); - s(EmcSelDpdCtrl, 8:8, scratch80, 28:28); - s(EmcSelDpdCtrl, 18:16, scratch80, 31:29); - s(EmcPmacroCaTxDrv, 5:0, scratch81, 5:0); - s(EmcPmacroCaTxDrv, 13:8, scratch81, 11:6); - s(EmcPmacroCaTxDrv, 21:16, scratch81, 17:12); - s(EmcPmacroCaTxDrv, 29:24, scratch81, 23:18); - s(EmcObdly, 5:0, scratch81, 29:24); - s(EmcObdly, 29:28, scratch81, 31:30); - s(EmcZcalInterval, 23:10, scratch82, 13:0); - s(EmcZcalInterval, 9:0, scratch82, 23:14); - s(EmcPmacroCmdRxTermMode, 1:0, scratch82, 25:24); - s(EmcPmacroCmdRxTermMode, 5:4, scratch82, 27:26); - s(EmcPmacroCmdRxTermMode, 9:8, scratch82, 29:28); - s(EmcPmacroCmdRxTermMode, 13:12, scratch82, 31:30); - s(EmcDataBrlshft0, 23:0, scratch83, 23:0); - s(EmcPmacroDataRxTermMode, 1:0, scratch83, 25:24); - s(EmcPmacroDataRxTermMode, 5:4, scratch83, 27:26); - s(EmcPmacroDataRxTermMode, 9:8, scratch83, 29:28); - s(EmcPmacroDataRxTermMode, 13:12, scratch83, 31:30); - s(EmcDataBrlshft1, 23:0, scratch84, 23:0); - s(McEmemArbTimingRc, 7:0, scratch84, 31:24); - s(EmcDqsBrlshft0, 23:0, scratch85, 23:0); - s(McEmemArbRsv, 7:0, scratch85, 31:24); - s(EmcDqsBrlshft1, 23:0, scratch86, 23:0); - s(EmcCfgPipe2, 11:0, scratch87, 11:0); - s(EmcCfgPipe2, 27:16, scratch87, 23:12); - s(EmcCfgPipe1, 11:0, scratch88, 11:0); - s(EmcCfgPipe1, 27:16, scratch88, 23:12); - s(EmcPmacroCmdCtrl0, 5:0, scratch89, 5:0); - s(EmcPmacroCmdCtrl0, 13:8, scratch89, 11:6); - s(EmcPmacroCmdCtrl0, 21:16, scratch89, 17:12); - s(EmcPmacroCmdCtrl0, 29:24, scratch89, 23:18); - s(EmcPmacroCmdCtrl1, 5:0, scratch90, 5:0); - s(EmcPmacroCmdCtrl1, 13:8, scratch90, 11:6); - s(EmcPmacroCmdCtrl1, 21:16, scratch90, 17:12); - s(EmcPmacroCmdCtrl1, 29:24, scratch90, 23:18); - s(EmcRas, 6:0, scratch90, 30:24); - s(EmcCfg, 8:8, scratch90, 31:31); - s(EmcPmacroVttgenCtrl2, 23:0, scratch91, 23:0); - s(EmcW2p, 6:0, scratch91, 30:24); - s(EmcCfg, 9:9, scratch91, 31:31); - s(EmcPmacroCmdPadRxCtrl, 2:0, scratch92, 2:0); - s(EmcPmacroCmdPadRxCtrl, 5:4, scratch92, 4:3); - s(EmcPmacroCmdPadRxCtrl, 10:8, scratch92, 7:5); - s(EmcPmacroCmdPadRxCtrl, 22:12, scratch92, 18:8); - s(EmcPmacroCmdPadRxCtrl, 28:24, scratch92, 23:19); - s(EmcQSafe, 6:0, scratch92, 30:24); - s(EmcCfg, 18:18, scratch92, 31:31); - s(EmcPmacroDataPadRxCtrl, 2:0, scratch93, 2:0); - s(EmcPmacroDataPadRxCtrl, 5:4, scratch93, 4:3); - s(EmcPmacroDataPadRxCtrl, 10:8, scratch93, 7:5); - s(EmcPmacroDataPadRxCtrl, 22:12, scratch93, 18:8); - s(EmcPmacroDataPadRxCtrl, 28:24, scratch93, 23:19); - s(EmcRdv, 6:0, scratch93, 30:24); - s(EmcCfg, 21:21, scratch93, 31:31); - s(McEmemArbDaCovers, 23:0, scratch94, 23:0); - s(EmcRw2Pden, 6:0, scratch94, 30:24); - s(EmcCfg, 22:22, scratch94, 31:31); - s(EmcPmacroCmdCtrl2, 5:0, scratch95, 5:0); - s(EmcPmacroCmdCtrl2, 13:9, scratch95, 10:6); - s(EmcPmacroCmdCtrl2, 21:16, scratch95, 16:11); - s(EmcPmacroCmdCtrl2, 29:24, scratch95, 22:17); - s(EmcRfcPb, 8:0, scratch95, 31:23); - s(EmcPmacroQuseDdllRank0_0, 10:0, scratch96, 10:0); - s(EmcPmacroQuseDdllRank0_0, 26:16, scratch96, 21:11); - s(EmcCfgUpdate, 2:0, scratch96, 24:22); - s(EmcCfgUpdate, 10:8, scratch96, 27:25); - s(EmcCfgUpdate, 31:28, scratch96, 31:28); - s(EmcPmacroQuseDdllRank0_1, 10:0, scratch97, 10:0); - s(EmcPmacroQuseDdllRank0_1, 26:16, scratch97, 21:11); - s(EmcRfc, 9:0, scratch97, 31:22); - s(EmcPmacroQuseDdllRank0_2, 10:0, scratch98, 10:0); - s(EmcPmacroQuseDdllRank0_2, 26:16, scratch98, 21:11); - s(EmcTxsr, 9:0, scratch98, 31:22); - s(EmcPmacroQuseDdllRank0_3, 10:0, scratch99, 10:0); - s(EmcPmacroQuseDdllRank0_3, 26:16, scratch99, 21:11); - s(EmcMc2EmcQ, 2:0, scratch99, 24:22); - s(EmcMc2EmcQ, 10:8, scratch99, 27:25); - s(EmcMc2EmcQ, 27:24, scratch99, 31:28); - s(EmcPmacroQuseDdllRank0_4, 10:0, scratch100, 10:0); - s(EmcPmacroQuseDdllRank0_4, 26:16, scratch100, 21:11); - s(McEmemArbRing1Throttle, 4:0, scratch100, 26:22); - s(McEmemArbRing1Throttle, 20:16, scratch100, 31:27); - s(EmcPmacroQuseDdllRank0_5, 10:0, scratch101, 10:0); - s(EmcPmacroQuseDdllRank0_5, 26:16, scratch101, 21:11); - s(EmcPmacroQuseDdllRank1_0, 10:0, scratch102, 10:0); - s(EmcPmacroQuseDdllRank1_0, 26:16, scratch102, 21:11); - s(EmcAr2Pden, 8:0, scratch102, 30:22); - s(EmcCfg, 23:23, scratch102, 31:31); - s(EmcPmacroQuseDdllRank1_1, 10:0, scratch103, 10:0); - s(EmcPmacroQuseDdllRank1_1, 26:16, scratch103, 21:11); - s(EmcRfcSlr, 8:0, scratch103, 30:22); - s(EmcCfg, 24:24, scratch103, 31:31); - s(EmcPmacroQuseDdllRank1_2, 10:0, scratch104, 10:0); - s(EmcPmacroQuseDdllRank1_2, 26:16, scratch104, 21:11); - s(EmcIbdly, 6:0, scratch104, 28:22); - s(EmcIbdly, 29:28, scratch104, 30:29); - s(EmcCfg, 25:25, scratch104, 31:31); - s(EmcPmacroQuseDdllRank1_3, 10:0, scratch105, 10:0); - s(EmcPmacroQuseDdllRank1_3, 26:16, scratch105, 21:11); - s(McEmemArbTimingRFCPB, 8:0, scratch105, 30:22); - s(EmcCfg, 26:26, scratch105, 31:31); - s(EmcPmacroQuseDdllRank1_4, 10:0, scratch106, 10:0); - s(EmcPmacroQuseDdllRank1_4, 26:16, scratch106, 21:11); - s(EmcTfaw, 6:0, scratch106, 28:22); - s(EmcPmacroDataPadTxCtrl, 3:2, scratch106, 30:29); - s(EmcCfg, 28:28, scratch106, 31:31); - s(EmcPmacroQuseDdllRank1_5, 10:0, scratch107, 10:0); - s(EmcPmacroQuseDdllRank1_5, 26:16, scratch107, 21:11); - s(EmcTClkStable, 6:0, scratch107, 28:22); - s(EmcPmacroDataPadTxCtrl, 7:6, scratch107, 30:29); - s(EmcCfg, 29:29, scratch107, 31:31); - s(EmcPmacroObDdllLongDqRank0_0, 10:0, scratch108, 10:0); - s(EmcPmacroObDdllLongDqRank0_0, 26:16, scratch108, 21:11); - s(EmcPdex2Mrr, 6:0, scratch108, 28:22); - s(EmcPmacroDataPadTxCtrl, 11:10, scratch108, 30:29); - s(EmcCfg, 30:30, scratch108, 31:31); - s(EmcPmacroObDdllLongDqRank0_1, 10:0, scratch109, 10:0); - s(EmcPmacroObDdllLongDqRank0_1, 26:16, scratch109, 21:11); - s(EmcRdvMask, 6:0, scratch109, 28:22); - s(EmcPmacroDataPadTxCtrl, 15:14, scratch109, 30:29); - s(EmcCfg, 31:31, scratch109, 31:31); - s(EmcPmacroObDdllLongDqRank0_2, 10:0, scratch110, 10:0); - s(EmcPmacroObDdllLongDqRank0_2, 26:16, scratch110, 21:11); - s(EmcRdvEarlyMask, 6:0, scratch110, 28:22); - s(EmcFbioCfg5, 4:4, scratch110, 29:29); - s(EmcFbioCfg5, 8:8, scratch110, 30:30); - s(EmcFbioCfg5, 10:10, scratch110, 31:31); - s(EmcPmacroObDdllLongDqRank0_3, 10:0, scratch111, 10:0); - s(EmcPmacroObDdllLongDqRank0_3, 26:16, scratch111, 21:11); - s(EmcRdvEarly, 6:0, scratch111, 28:22); - s(EmcFbioCfg5, 12:12, scratch111, 29:29); - s(EmcFbioCfg5, 25:24, scratch111, 31:30); - s(EmcPmacroObDdllLongDqRank0_4, 10:0, scratch112, 10:0); - s(EmcPmacroObDdllLongDqRank0_4, 26:16, scratch112, 21:11); - s(EmcPmacroDdllShortCmd_2, 6:0, scratch112, 28:22); - s(EmcFbioCfg5, 28:26, scratch112, 31:29); - s(EmcPmacroObDdllLongDqRank0_5, 10:0, scratch113, 10:0); - s(EmcPmacroObDdllLongDqRank0_5, 26:16, scratch113, 21:11); - s(McEmemArbTimingRp, 6:0, scratch113, 28:22); - s(EmcFbioCfg5, 31:30, scratch113, 30:29); - s(EmcCfg2, 0:0, scratch113, 31:31); - s(EmcPmacroObDdllLongDqRank1_0, 10:0, scratch114, 10:0); - s(EmcPmacroObDdllLongDqRank1_0, 26:16, scratch114, 21:11); - s(McEmemArbTimingRas, 6:0, scratch114, 28:22); - s(EmcCfg2, 2:1, scratch114, 30:29); - s(EmcCfg2, 7:7, scratch114, 31:31); - s(EmcPmacroObDdllLongDqRank1_1, 10:0, scratch115, 10:0); - s(EmcPmacroObDdllLongDqRank1_1, 26:16, scratch115, 21:11); - s(McEmemArbTimingFaw, 6:0, scratch115, 28:22); - s(EmcCfg2, 11:10, scratch115, 30:29); - s(EmcCfg2, 14:14, scratch115, 31:31); - s(EmcPmacroObDdllLongDqRank1_2, 10:0, scratch123, 10:0); - s(EmcPmacroObDdllLongDqRank1_2, 26:16, scratch123, 21:11); - s(McEmemArbTimingRap2Pre, 6:0, scratch123, 28:22); - s(EmcCfg2, 16:15, scratch123, 30:29); - s(EmcCfg2, 20:20, scratch123, 31:31); - s(EmcPmacroObDdllLongDqRank1_3, 10:0, scratch124, 10:0); - s(EmcPmacroObDdllLongDqRank1_3, 26:16, scratch124, 21:11); - s(McEmemArbTimingWap2Pre, 6:0, scratch124, 28:22); - s(EmcCfg2, 24:22, scratch124, 31:29); - s(EmcPmacroObDdllLongDqRank1_4, 10:0, scratch125, 10:0); - s(EmcPmacroObDdllLongDqRank1_4, 26:16, scratch125, 21:11); - s(McEmemArbTimingR2W, 6:0, scratch125, 28:22); - s(EmcCfg2, 25:25, scratch125, 29:29); - s(EmcCfg2, 29:28, scratch125, 31:30); - s(EmcPmacroObDdllLongDqRank1_5, 10:0, scratch126, 10:0); - s(EmcPmacroObDdllLongDqRank1_5, 26:16, scratch126, 21:11); - s(McEmemArbTimingW2R, 6:0, scratch126, 28:22); - s(EmcCfg2, 31:30, scratch126, 30:29); - s(EmcCfgPipe, 0:0, scratch126, 31:31); - s(EmcPmacroObDdllLongDqsRank0_0, 10:0, scratch127, 10:0); - s(EmcPmacroObDdllLongDqsRank0_0, 26:16, scratch127, 21:11); - s(EmcRp, 5:0, scratch127, 27:22); - s(EmcCfgPipe, 4:1, scratch127, 31:28); - s(EmcPmacroObDdllLongDqsRank0_1, 10:0, scratch128, 10:0); - s(EmcPmacroObDdllLongDqsRank0_1, 26:16, scratch128, 21:11); - s(EmcR2w, 5:0, scratch128, 27:22); - s(EmcCfgPipe, 8:5, scratch128, 31:28); - s(EmcPmacroObDdllLongDqsRank0_2, 10:0, scratch129, 10:0); - s(EmcPmacroObDdllLongDqsRank0_2, 26:16, scratch129, 21:11); - s(EmcW2r, 5:0, scratch129, 27:22); - s(EmcCfgPipe, 11:9, scratch129, 30:28); - s(EmcCfgPipe, 16:16, scratch129, 31:31); - s(EmcPmacroObDdllLongDqsRank0_3, 10:0, scratch130, 10:0); - s(EmcPmacroObDdllLongDqsRank0_3, 26:16, scratch130, 21:11); - s(EmcR2p, 5:0, scratch130, 27:22); - s(EmcCfgPipe, 20:17, scratch130, 31:28); - s(EmcPmacroObDdllLongDqsRank0_4, 10:0, scratch131, 10:0); - s(EmcPmacroObDdllLongDqsRank0_4, 26:16, scratch131, 21:11); - s(EmcCcdmw, 5:0, scratch131, 27:22); - s(EmcCfgPipe, 24:21, scratch131, 31:28); - s(EmcPmacroObDdllLongDqsRank0_5, 10:0, scratch132, 10:0); - s(EmcPmacroObDdllLongDqsRank0_5, 26:16, scratch132, 21:11); - s(EmcRdRcd, 5:0, scratch132, 27:22); - s(EmcCfgPipe, 27:25, scratch132, 30:28); - s(EmcPmacroTxPwrd0, 0:0, scratch132, 31:31); - s(EmcPmacroObDdllLongDqsRank1_0, 10:0, scratch133, 10:0); - s(EmcPmacroObDdllLongDqsRank1_0, 26:16, scratch133, 21:11); - s(EmcWrRcd, 5:0, scratch133, 27:22); - s(EmcPmacroTxPwrd0, 4:1, scratch133, 31:28); - s(EmcPmacroObDdllLongDqsRank1_1, 10:0, scratch134, 10:0); - s(EmcPmacroObDdllLongDqsRank1_1, 26:16, scratch134, 21:11); - s(EmcWdv, 5:0, scratch134, 27:22); - s(EmcPmacroTxPwrd0, 8:5, scratch134, 31:28); - s(EmcPmacroObDdllLongDqsRank1_2, 10:0, scratch135, 10:0); - s(EmcPmacroObDdllLongDqsRank1_2, 26:16, scratch135, 21:11); - s(EmcQUse, 5:0, scratch135, 27:22); - s(EmcPmacroTxPwrd0, 12:9, scratch135, 31:28); - s(EmcPmacroObDdllLongDqsRank1_3, 10:0, scratch136, 10:0); - s(EmcPmacroObDdllLongDqsRank1_3, 26:16, scratch136, 21:11); - s(EmcPdEx2Wr, 5:0, scratch136, 27:22); - s(EmcPmacroTxPwrd0, 13:13, scratch136, 28:28); - s(EmcPmacroTxPwrd0, 18:16, scratch136, 31:29); - s(EmcPmacroObDdllLongDqsRank1_4, 10:0, scratch137, 10:0); - s(EmcPmacroObDdllLongDqsRank1_4, 26:16, scratch137, 21:11); - s(EmcPdEx2Rd, 5:0, scratch137, 27:22); - s(EmcPmacroTxPwrd0, 22:19, scratch137, 31:28); - s(EmcPmacroObDdllLongDqsRank1_5, 10:0, scratch138, 10:0); - s(EmcPmacroObDdllLongDqsRank1_5, 26:16, scratch138, 21:11); - s(EmcPdex2Cke, 5:0, scratch138, 27:22); - s(EmcPmacroTxPwrd0, 26:23, scratch138, 31:28); - s(EmcPmacroIbDdllLongDqsRank0_0, 10:0, scratch139, 10:0); - s(EmcPmacroIbDdllLongDqsRank0_0, 26:16, scratch139, 21:11); - s(EmcPChg2Pden, 5:0, scratch139, 27:22); - s(EmcPmacroTxPwrd0, 29:27, scratch139, 30:28); - s(EmcPmacroTxPwrd1, 0:0, scratch139, 31:31); - s(EmcPmacroIbDdllLongDqsRank0_1, 10:0, scratch140, 10:0); - s(EmcPmacroIbDdllLongDqsRank0_1, 26:16, scratch140, 21:11); - s(EmcAct2Pden, 5:0, scratch140, 27:22); - s(EmcPmacroTxPwrd1, 4:1, scratch140, 31:28); - s(EmcPmacroIbDdllLongDqsRank0_2, 10:0, scratch141, 10:0); - s(EmcPmacroIbDdllLongDqsRank0_2, 26:16, scratch141, 21:11); - s(EmcCke2Pden, 5:0, scratch141, 27:22); - s(EmcPmacroTxPwrd1, 8:5, scratch141, 31:28); - s(EmcPmacroIbDdllLongDqsRank0_3, 10:0, scratch142, 10:0); - s(EmcPmacroIbDdllLongDqsRank0_3, 26:16, scratch142, 21:11); - s(EmcTcke, 5:0, scratch142, 27:22); - s(EmcPmacroTxPwrd1, 12:9, scratch142, 31:28); - s(EmcPmacroIbDdllLongDqsRank1_0, 10:0, scratch143, 10:0); - s(EmcPmacroIbDdllLongDqsRank1_0, 26:16, scratch143, 21:11); - s(EmcTrpab, 5:0, scratch143, 27:22); - s(EmcPmacroTxPwrd1, 13:13, scratch143, 28:28); - s(EmcPmacroTxPwrd1, 18:16, scratch143, 31:29); - s(EmcPmacroIbDdllLongDqsRank1_1, 10:0, scratch144, 10:0); - s(EmcPmacroIbDdllLongDqsRank1_1, 26:16, scratch144, 21:11); - s(EmcClkenOverride, 3:1, scratch144, 24:22); - s(EmcClkenOverride, 8:6, scratch144, 27:25); - s(EmcPmacroTxPwrd1, 22:19, scratch144, 31:28); - s(EmcPmacroIbDdllLongDqsRank1_2, 10:0, scratch145, 10:0); - s(EmcPmacroIbDdllLongDqsRank1_2, 26:16, scratch145, 21:11); - s(EmcEInput, 5:0, scratch145, 27:22); - s(EmcPmacroTxPwrd1, 26:23, scratch145, 31:28); - s(EmcPmacroIbDdllLongDqsRank1_3, 10:0, scratch146, 10:0); - s(EmcPmacroIbDdllLongDqsRank1_3, 26:16, scratch146, 21:11); - s(EmcEInputDuration, 5:0, scratch146, 27:22); - s(EmcPmacroTxPwrd1, 29:27, scratch146, 30:28); - s(EmcPmacroTxPwrd2, 0:0, scratch146, 31:31); - s(EmcPmacroDdllLongCmd_0, 10:0, scratch147, 10:0); - s(EmcPmacroDdllLongCmd_0, 26:16, scratch147, 21:11); - s(EmcPutermExtra, 5:0, scratch147, 27:22); - s(EmcPmacroTxPwrd2, 4:1, scratch147, 31:28); - s(EmcPmacroDdllLongCmd_1, 10:0, scratch148, 10:0); - s(EmcPmacroDdllLongCmd_1, 26:16, scratch148, 21:11); - s(EmcTckesr, 5:0, scratch148, 27:22); - s(EmcPmacroTxPwrd2, 8:5, scratch148, 31:28); - s(EmcPmacroDdllLongCmd_2, 10:0, scratch149, 10:0); - s(EmcPmacroDdllLongCmd_2, 26:16, scratch149, 21:11); - s(EmcTpd, 5:0, scratch149, 27:22); - s(EmcPmacroTxPwrd2, 12:9, scratch149, 31:28); - s(EmcPmacroDdllLongCmd_3, 10:0, scratch150, 10:0); - s(EmcPmacroDdllLongCmd_3, 26:16, scratch150, 21:11); - s(EmcWdvMask, 5:0, scratch150, 27:22); - s(EmcPmacroTxPwrd2, 13:13, scratch150, 28:28); - s(EmcPmacroTxPwrd2, 18:16, scratch150, 31:29); - s(McEmemArbCfg, 8:0, scratch151, 8:0); - s(McEmemArbCfg, 20:16, scratch151, 13:9); - s(McEmemArbCfg, 31:24, scratch151, 21:14); - s(EmcWdvChk, 5:0, scratch151, 27:22); - s(EmcPmacroTxPwrd2, 22:19, scratch151, 31:28); - s(McEmemArbMisc1, 12:0, scratch152, 12:0); - s(McEmemArbMisc1, 25:21, scratch152, 17:13); - s(McEmemArbMisc1, 31:28, scratch152, 21:18); - s(EmcCmdBrlshft0, 5:0, scratch152, 27:22); - s(EmcPmacroTxPwrd2, 26:23, scratch152, 31:28); - s(EmcMrsWaitCnt2, 9:0, scratch153, 9:0); - s(EmcMrsWaitCnt2, 26:16, scratch153, 20:10); - s(EmcPmacroIbRxrt, 10:0, scratch153, 31:21); - s(EmcMrsWaitCnt, 9:0, scratch154, 9:0); - s(EmcMrsWaitCnt, 26:16, scratch154, 20:10); - s(EmcPmacroDdllLongCmd_4, 10:0, scratch154, 31:21); - s(EmcAutoCalInterval, 20:0, scratch155, 20:0); - s(McEmemArbOutstandingReq, 8:0, scratch155, 29:21); - s(McEmemArbOutstandingReq, 31:30, scratch155, 31:30); - s(McEmemArbRefpbHpCtrl, 6:0, scratch156, 6:0); - s(McEmemArbRefpbHpCtrl, 14:8, scratch156, 13:7); - s(McEmemArbRefpbHpCtrl, 22:16, scratch156, 20:14); - s(EmcCmdBrlshft1, 5:0, scratch156, 26:21); - s(EmcRrd, 4:0, scratch156, 31:27); - s(EmcQuseBrlshft0, 19:0, scratch157, 19:0); - s(EmcFbioCfg8, 27:16, scratch157, 31:20); - s(EmcQuseBrlshft1, 19:0, scratch158, 19:0); - s(EmcTxsrDll, 11:0, scratch158, 31:20); - s(EmcQuseBrlshft2, 19:0, scratch159, 19:0); - s(EmcTxdsrvttgen, 11:0, scratch159, 31:20); - s(EmcQuseBrlshft3, 19:0, scratch160, 19:0); - s(EmcPmacroVttgenCtrl0, 3:0, scratch160, 23:20); - s(EmcPmacroVttgenCtrl0, 11:8, scratch160, 27:24); - s(EmcPmacroVttgenCtrl0, 19:16, scratch160, 31:28); - s(EmcPmacroVttgenCtrl1, 19:0, scratch161, 19:0); - s(EmcCmdBrlshft2, 5:0, scratch161, 25:20); - s(EmcCmdBrlshft3, 5:0, scratch161, 31:26); - s(EmcAutoCalConfig3, 5:0, scratch162, 5:0); - s(EmcAutoCalConfig3, 13:8, scratch162, 11:6); - s(EmcAutoCalConfig3, 18:16, scratch162, 14:12); - s(EmcAutoCalConfig3, 22:20, scratch162, 17:15); - s(EmcTRefBw, 13:0, scratch162, 31:18); - s(EmcAutoCalConfig4, 5:0, scratch163, 5:0); - s(EmcAutoCalConfig4, 13:8, scratch163, 11:6); - s(EmcAutoCalConfig4, 18:16, scratch163, 14:12); - s(EmcAutoCalConfig4, 22:20, scratch163, 17:15); - s(EmcQpop, 6:0, scratch163, 24:18); - s(EmcQpop, 22:16, scratch163, 31:25); - s(EmcAutoCalConfig5, 5:0, scratch164, 5:0); - s(EmcAutoCalConfig5, 13:8, scratch164, 11:6); - s(EmcAutoCalConfig5, 18:16, scratch164, 14:12); - s(EmcAutoCalConfig5, 22:20, scratch164, 17:15); - s(EmcPmacroAutocalCfgCommon, 5:0, scratch164, 23:18); - s(EmcPmacroAutocalCfgCommon, 13:8, scratch164, 29:24); - s(EmcPmacroAutocalCfgCommon, 16:16, scratch164, 30:30); - s(EmcPmacroTxPwrd2, 27:27, scratch164, 31:31); - s(EmcAutoCalConfig6, 5:0, scratch165, 5:0); - s(EmcAutoCalConfig6, 13:8, scratch165, 11:6); - s(EmcAutoCalConfig6, 18:16, scratch165, 14:12); - s(EmcAutoCalConfig6, 22:20, scratch165, 17:15); - s(EmcWev, 5:0, scratch165, 23:18); - s(EmcWsv, 5:0, scratch165, 29:24); - s(EmcPmacroTxPwrd2, 29:28, scratch165, 31:30); - s(EmcAutoCalConfig7, 5:0, scratch166, 5:0); - s(EmcAutoCalConfig7, 13:8, scratch166, 11:6); - s(EmcAutoCalConfig7, 18:16, scratch166, 14:12); - s(EmcAutoCalConfig7, 22:20, scratch166, 17:15); - s(EmcCfg3, 2:0, scratch166, 20:18); - s(EmcCfg3, 6:4, scratch166, 23:21); - s(EmcQuseWidth, 3:0, scratch166, 27:24); - s(EmcQuseWidth, 29:28, scratch166, 29:28); - s(EmcPmacroTxPwrd3, 1:0, scratch166, 31:30); - s(EmcAutoCalConfig8, 5:0, scratch167, 5:0); - s(EmcAutoCalConfig8, 13:8, scratch167, 11:6); - s(EmcAutoCalConfig8, 18:16, scratch167, 14:12); - s(EmcAutoCalConfig8, 22:20, scratch167, 17:15); - s(EmcPmacroBgBiasCtrl0, 2:0, scratch167, 20:18); - s(EmcPmacroBgBiasCtrl0, 6:4, scratch167, 23:21); - s(McEmemArbTimingRcd, 5:0, scratch167, 29:24); - s(EmcPmacroTxPwrd3, 3:2, scratch167, 31:30); - s(EmcXm2CompPadCtrl2, 17:0, scratch168, 17:0); - s(McEmemArbTimingCcdmw, 5:0, scratch168, 23:18); - s(McEmemArbOverride, 27:27, scratch168, 24:24); - s(McEmemArbOverride, 26:26, scratch168, 25:25); - s(McEmemArbOverride, 16:16, scratch168, 26:26); - s(McEmemArbOverride, 10:10, scratch168, 27:27); - s(McEmemArbOverride, 4:4, scratch168, 28:28); - s(McEmemArbOverride, 3:3, scratch168, 29:29); - s(EmcPmacroTxPwrd3, 5:4, scratch168, 31:30); - s(EmcXm2CompPadCtrl3, 17:0, scratch169, 17:0); - s(EmcRext, 4:0, scratch169, 22:18); - s(EmcTClkStop, 4:0, scratch169, 27:23); - s(EmcPmacroTxPwrd3, 9:6, scratch169, 31:28); - s(EmcZcalWaitCnt, 10:0, scratch170, 10:0); - s(EmcZcalWaitCnt, 21:16, scratch170, 16:11); - s(EmcZcalWaitCnt, 31:31, scratch170, 17:17); - s(EmcWext, 4:0, scratch170, 22:18); - s(EmcRefctrl2, 0:0, scratch170, 23:23); - s(EmcRefctrl2, 26:24, scratch170, 26:24); - s(EmcRefctrl2, 31:31, scratch170, 27:27); - s(EmcPmacroTxPwrd3, 13:10, scratch170, 31:28); - s(EmcZcalMrwCmd, 7:0, scratch171, 7:0); - s(EmcZcalMrwCmd, 23:16, scratch171, 15:8); - s(EmcZcalMrwCmd, 31:30, scratch171, 17:16); - s(EmcWeDuration, 4:0, scratch171, 22:18); - s(EmcWsDuration, 4:0, scratch171, 27:23); - s(EmcPmacroTxPwrd3, 19:16, scratch171, 31:28); - s(EmcSwizzleRank0Byte0, 2:0, scratch172, 2:0); - s(EmcSwizzleRank0Byte0, 6:4, scratch172, 5:3); - s(EmcSwizzleRank0Byte0, 10:8, scratch172, 8:6); - s(EmcSwizzleRank0Byte0, 14:12, scratch172, 11:9); - s(EmcSwizzleRank0Byte0, 18:16, scratch172, 14:12); - s(EmcSwizzleRank0Byte0, 22:20, scratch172, 17:15); - s(EmcPutermWidth, 31:31, scratch172, 18:18); - s(EmcPutermWidth, 3:0, scratch172, 22:19); - s(McEmemArbTimingRrd, 4:0, scratch172, 27:23); - s(EmcPmacroTxPwrd3, 23:20, scratch172, 31:28); - s(EmcSwizzleRank0Byte1, 2:0, scratch173, 2:0); - s(EmcSwizzleRank0Byte1, 6:4, scratch173, 5:3); - s(EmcSwizzleRank0Byte1, 10:8, scratch173, 8:6); - s(EmcSwizzleRank0Byte1, 14:12, scratch173, 11:9); - s(EmcSwizzleRank0Byte1, 18:16, scratch173, 14:12); - s(EmcSwizzleRank0Byte1, 22:20, scratch173, 17:15); - s(McEmemArbTimingR2R, 4:0, scratch173, 22:18); - s(McEmemArbTimingW2W, 4:0, scratch173, 27:23); - s(EmcPmacroTxPwrd3, 27:24, scratch173, 31:28); - s(EmcSwizzleRank0Byte2, 2:0, scratch174, 2:0); - s(EmcSwizzleRank0Byte2, 6:4, scratch174, 5:3); - s(EmcSwizzleRank0Byte2, 10:8, scratch174, 8:6); - s(EmcSwizzleRank0Byte2, 14:12, scratch174, 11:9); - s(EmcSwizzleRank0Byte2, 18:16, scratch174, 14:12); - s(EmcSwizzleRank0Byte2, 22:20, scratch174, 17:15); - s(EmcPmacroTxPwrd3, 29:28, scratch174, 19:18); - s(EmcPmacroTxSelClkSrc0, 11:0, scratch174, 31:20); - s(EmcSwizzleRank0Byte3, 2:0, scratch175, 2:0); - s(EmcSwizzleRank0Byte3, 6:4, scratch175, 5:3); - s(EmcSwizzleRank0Byte3, 10:8, scratch175, 8:6); - s(EmcSwizzleRank0Byte3, 14:12, scratch175, 11:9); - s(EmcSwizzleRank0Byte3, 18:16, scratch175, 14:12); - s(EmcSwizzleRank0Byte3, 22:20, scratch175, 17:15); - s(EmcPmacroTxSelClkSrc0, 27:16, scratch175, 29:18); - s(EmcPmacroTxSelClkSrc1, 1:0, scratch175, 31:30); - s(EmcSwizzleRank1Byte0, 2:0, scratch176, 2:0); - s(EmcSwizzleRank1Byte0, 6:4, scratch176, 5:3); - s(EmcSwizzleRank1Byte0, 10:8, scratch176, 8:6); - s(EmcSwizzleRank1Byte0, 14:12, scratch176, 11:9); - s(EmcSwizzleRank1Byte0, 18:16, scratch176, 14:12); - s(EmcSwizzleRank1Byte0, 22:20, scratch176, 17:15); - s(EmcPmacroTxSelClkSrc1, 11:2, scratch176, 27:18); - s(EmcPmacroTxSelClkSrc1, 19:16, scratch176, 31:28); - s(EmcSwizzleRank1Byte1, 2:0, scratch177, 2:0); - s(EmcSwizzleRank1Byte1, 6:4, scratch177, 5:3); - s(EmcSwizzleRank1Byte1, 10:8, scratch177, 8:6); - s(EmcSwizzleRank1Byte1, 14:12, scratch177, 11:9); - s(EmcSwizzleRank1Byte1, 18:16, scratch177, 14:12); - s(EmcSwizzleRank1Byte1, 22:20, scratch177, 17:15); - s(EmcPmacroTxSelClkSrc1, 27:20, scratch177, 25:18); - s(EmcPmacroTxSelClkSrc3, 5:0, scratch177, 31:26); - s(EmcSwizzleRank1Byte2, 2:0, scratch178, 2:0); - s(EmcSwizzleRank1Byte2, 6:4, scratch178, 5:3); - s(EmcSwizzleRank1Byte2, 10:8, scratch178, 8:6); - s(EmcSwizzleRank1Byte2, 14:12, scratch178, 11:9); - s(EmcSwizzleRank1Byte2, 18:16, scratch178, 14:12); - s(EmcSwizzleRank1Byte2, 22:20, scratch178, 17:15); - s(EmcPmacroTxSelClkSrc3, 11:6, scratch178, 23:18); - s(EmcPmacroTxSelClkSrc3, 23:16, scratch178, 31:24); - s(EmcSwizzleRank1Byte3, 2:0, scratch179, 2:0); - s(EmcSwizzleRank1Byte3, 6:4, scratch179, 5:3); - s(EmcSwizzleRank1Byte3, 10:8, scratch179, 8:6); - s(EmcSwizzleRank1Byte3, 14:12, scratch179, 11:9); - s(EmcSwizzleRank1Byte3, 18:16, scratch179, 14:12); - s(EmcSwizzleRank1Byte3, 22:20, scratch179, 17:15); - s(EmcPmacroTxSelClkSrc3, 27:24, scratch179, 21:18); - s(EmcPmacroTxSelClkSrc2, 9:0, scratch179, 31:22); - s(EmcPmacroCmdBrickCtrlFdpd, 17:0, scratch180, 17:0); - s(EmcPmacroTxSelClkSrc2, 11:10, scratch180, 19:18); - s(EmcPmacroTxSelClkSrc2, 27:16, scratch180, 31:20); - s(EmcPmacroDataBrickCtrlFdpd, 17:0, scratch181, 17:0); - s(EmcPmacroTxSelClkSrc4, 11:0, scratch181, 29:18); - s(EmcPmacroTxSelClkSrc4, 17:16, scratch181, 31:30); - s(EmcFbioCfg7, 16:0, scratch182, 16:0); - s(McEmemArbRefpbBankCtrl, 6:0, scratch182, 23:17); - s(McEmemArbRefpbBankCtrl, 14:8, scratch182, 30:24); - s(McEmemArbRefpbBankCtrl, 31:31, scratch182, 31:31); - s(EmcDynSelfRefControl, 15:0, scratch183, 15:0); - s(EmcDynSelfRefControl, 31:31, scratch183, 16:16); - s(EmcPmacroTxSelClkSrc4, 27:18, scratch183, 26:17); - s(EmcPmacroTxSelClkSrc5, 4:0, scratch183, 31:27); - s(EmcDllCfg1, 16:0, scratch184, 16:0); - s(EmcPmacroTxSelClkSrc5, 11:5, scratch184, 23:17); - s(EmcPmacroTxSelClkSrc5, 23:16, scratch184, 31:24); - s(EmcPmacroPadCfgCtrl, 1:0, scratch185, 1:0); - s(EmcPmacroPadCfgCtrl, 6:5, scratch185, 3:2); - s(EmcPmacroPadCfgCtrl, 11:9, scratch185, 6:4); - s(EmcPmacroPadCfgCtrl, 13:13, scratch185, 7:7); - s(EmcPmacroPadCfgCtrl, 17:16, scratch185, 9:8); - s(EmcPmacroPadCfgCtrl, 21:20, scratch185, 11:10); - s(EmcPmacroPadCfgCtrl, 25:24, scratch185, 13:12); - s(EmcPmacroPadCfgCtrl, 30:28, scratch185, 16:14); - s(EmcPmacroTxSelClkSrc5, 27:24, scratch185, 20:17); - s(EmcPmacroCmdPadTxCtrl, 1:0, scratch185, 22:21); - s(EmcPmacroCmdPadTxCtrl, 5:4, scratch185, 24:23); - s(EmcPmacroCmdPadTxCtrl, 9:8, scratch185, 26:25); - s(EmcPmacroCmdPadTxCtrl, 13:12, scratch185, 28:27); - s(EmcPmacroCmdPadTxCtrl, 16:16, scratch185, 29:29); - s(EmcPmacroCmdPadTxCtrl, 21:20, scratch185, 31:30); - s(EmcRefresh, 15:0, scratch186, 15:0); - s(EmcCmdQ, 4:0, scratch186, 20:16); - s(EmcCmdQ, 10:8, scratch186, 23:21); - s(EmcCmdQ, 14:12, scratch186, 26:24); - s(EmcCmdQ, 28:24, scratch186, 31:27); - s(EmcAcpdControl, 15:0, scratch187, 15:0); - s(EmcAutoCalVrefSel1, 15:0, scratch187, 31:16); - s(EmcXm2CompPadCtrl, 1:0, scratch188, 1:0); - s(EmcXm2CompPadCtrl, 6:3, scratch188, 5:2); - s(EmcXm2CompPadCtrl, 9:9, scratch188, 6:6); - s(EmcXm2CompPadCtrl, 19:11, scratch188, 15:7); - s(EmcCfgDigDllPeriod, 15:0, scratch188, 31:16); - s(EmcCfgDigDll_1, 15:0, scratch189, 15:0); - s(EmcPreRefreshReqCnt, 15:0, scratch189, 31:16); - s(EmcPmacroCmdPadTxCtrl, 27:24, scratch190, 19:16); - s(EmcPmacroDataPadTxCtrl, 1:0, scratch190, 21:20); - s(EmcPmacroDataPadTxCtrl, 5:4, scratch190, 23:22); - s(EmcPmacroDataPadTxCtrl, 9:8, scratch190, 25:24); - s(EmcPmacroDataPadTxCtrl, 13:12, scratch190, 27:26); - s(EmcPmacroDataPadTxCtrl, 16:16, scratch190, 28:28); - s(EmcPmacroDataPadTxCtrl, 21:20, scratch190, 30:29); - s(EmcPmacroDataPadTxCtrl, 24:24, scratch190, 31:31); - s(EmcPmacroDataPadTxCtrl, 27:25, scratch191, 2:0); - - s(EmcPinGpio, 1:0, scratch8, 31:30); - s(EmcPinGpioEn, 1:0, scratch9, 31:30); - s(EmcDevSelect, 1:0, scratch10, 31:30); - s(EmcZcalWarmColdBootEnables, 1:0, scratch11, 31:30); - s(EmcCfgDigDllPeriodWarmBoot, 1:0, scratch12, 31:30); - s32(EmcBctSpare13, scratch31); - s32(EmcBctSpare12, scratch32); - s32(EmcBctSpare7, scratch33); - s32(EmcBctSpare6, scratch40); - s32(EmcBctSpare5, scratch42); - s32(EmcBctSpare4, scratch44); - s32(EmcBctSpare3, scratch45); - s32(EmcBctSpare2, scratch46); - s32(EmcBctSpare1, scratch47); - s32(EmcBctSpare0, scratch48); - s32(EmcBctSpare9, scratch50); - s32(EmcBctSpare8, scratch51); - s32(BootRomPatchData, scratch56); - s32(BootRomPatchControl, scratch57); - s(McClkenOverrideAllWarmBoot, 0:0, scratch58, 31:31); - s(EmcClkenOverrideAllWarmBoot, 0:0, scratch59, 30:30); - s(EmcMrsWarmBootEnable, 0:0, scratch59, 31:31); - s(ClearClk2Mc1, 0:0, scratch60, 30:30); - s(EmcWarmBootExtraModeRegWriteEnable, 0:0, scratch60, 31:31); - s(ClkRstControllerPllmMisc2OverrideEnable, 0:0, scratch61, 30:30); - s(EmcDbgWriteMux, 0:0, scratch61, 31:31); - s(EmcExtraRefreshNum, 2:0, scratch62, 31:29); - s(PmcIoDpd3ReqWait, 2:0, scratch68, 30:28); - s(AhbArbitrationXbarCtrlMemInitDone, 0:0, scratch68, 31:31); - s(MemoryType, 2:0, scratch69, 30:28); - s(PmcIoDpd4ReqWait, 2:0, scratch70, 30:28); - s(EmcTimingControlWait, 7:0, scratch86, 31:24); - s(EmcZcalWarmBootWait, 7:0, scratch87, 31:24); - s(WarmBootWait, 7:0, scratch88, 31:24); - s(EmcPinProgramWait, 7:0, scratch89, 31:24); - s(EmcAutoCalWait, 9:0, scratch101, 31:22); - s(SwizzleRankByteEncode, 15:0, scratch190, 15:0); - - switch (sdram->MemoryType) - { - case NvBootMemoryType_LpDdr2: - case NvBootMemoryType_LpDdr4: - s(EmcMrwLpddr2ZcalWarmBoot, 23:16, scratch5, 7:0); - s(EmcMrwLpddr2ZcalWarmBoot, 7:0, scratch5, 15:8); - s(EmcWarmBootMrwExtra, 23:16, scratch5, 23:16); - s(EmcWarmBootMrwExtra, 7:0, scratch5, 31:24); - s(EmcMrwLpddr2ZcalWarmBoot, 31:30, scratch6, 1:0); - s(EmcWarmBootMrwExtra, 31:30, scratch6, 3:2); - s(EmcMrwLpddr2ZcalWarmBoot, 27:26, scratch6, 5:4); - s(EmcWarmBootMrwExtra, 27:26, scratch6, 7:6); - s(EmcMrw6, 27:0, scratch8, 27:0); - s(EmcMrw6, 31:30, scratch8, 29:28); - s(EmcMrw8, 27:0, scratch9, 27:0); - s(EmcMrw8, 31:30, scratch9, 29:28); - s(EmcMrw9, 27:0, scratch10, 27:0); - s(EmcMrw9, 31:30, scratch10, 29:28); - s(EmcMrw10, 27:0, scratch11, 27:0); - s(EmcMrw10, 31:30, scratch11, 29:28); - s(EmcMrw12, 27:0, scratch12, 27:0); - s(EmcMrw12, 31:30, scratch12, 29:28); - s(EmcMrw13, 27:0, scratch13, 27:0); - s(EmcMrw13, 31:30, scratch13, 29:28); - s(EmcMrw14, 27:0, scratch14, 27:0); - s(EmcMrw14, 31:30, scratch14, 29:28); - s(EmcMrw1, 7:0, scratch15, 7:0); - s(EmcMrw1, 23:16, scratch15, 15:8); - s(EmcMrw1, 27:26, scratch15, 17:16); - s(EmcMrw1, 31:30, scratch15, 19:18); - s(EmcWarmBootMrwExtra, 7:0, scratch16, 7:0); - s(EmcWarmBootMrwExtra, 23:16, scratch16, 15:8); - s(EmcWarmBootMrwExtra, 27:26, scratch16, 17:16); - s(EmcWarmBootMrwExtra, 31:30, scratch16, 19:18); - s(EmcMrw2, 7:0, scratch17, 7:0); - s(EmcMrw2, 23:16, scratch17, 15:8); - s(EmcMrw2, 27:26, scratch17, 17:16); - s(EmcMrw2, 31:30, scratch17, 19:18); - s(EmcMrw3, 7:0, scratch18, 7:0); - s(EmcMrw3, 23:16, scratch18, 15:8); - s(EmcMrw3, 27:26, scratch18, 17:16); - s(EmcMrw3, 31:30, scratch18, 19:18); - s(EmcMrw4, 7:0, scratch19, 7:0); - s(EmcMrw4, 23:16, scratch19, 15:8); - s(EmcMrw4, 27:26, scratch19, 17:16); - s(EmcMrw4, 31:30, scratch19, 19:18); - break; - case NvBootMemoryType_Ddr3: - s(EmcMrs, 13:0, scratch5, 13:0); - s(EmcEmrs, 13:0, scratch5, 27:14); - s(EmcMrs, 21:20, scratch5, 29:28); - s(EmcMrs, 31:30, scratch5, 31:30); - s(EmcEmrs2, 13:0, scratch8, 13:0); - s(EmcEmrs3, 13:0, scratch8, 27:14); - s(EmcEmrs, 21:20, scratch8, 29:28); - s(EmcWarmBootMrsExtra, 13:0, scratch9, 13:0); - s(EmcEmrs, 31:30, scratch9, 15:14); - s(EmcEmrs2, 21:20, scratch9, 17:16); - s(EmcEmrs2, 31:30, scratch9, 19:18); - s(EmcEmrs3, 21:20, scratch9, 21:20); - s(EmcEmrs3, 31:30, scratch9, 23:22); - s(EmcWarmBootMrsExtra, 31:30, scratch9, 25:24); - s(EmcWarmBootMrsExtra, 21:20, scratch9, 27:26); - s(EmcZqCalDdr3WarmBoot, 31:30, scratch9, 29:28); - s(EmcMrs, 27:26, scratch10, 1:0); - s(EmcEmrs, 27:26, scratch10, 3:2); - s(EmcEmrs2, 27:26, scratch10, 5:4); - s(EmcEmrs3, 27:26, scratch10, 7:6); - s(EmcWarmBootMrsExtra, 27:27, scratch10, 8:8); - s(EmcWarmBootMrsExtra, 26:26, scratch10, 9:9); - s(EmcZqCalDdr3WarmBoot, 0:0, scratch10, 10:10); - s(EmcZqCalDdr3WarmBoot, 4:4, scratch10, 11:11); - break; - } - - s32(EmcCmdMappingByte, secure_scratch8); - s32(EmcPmacroBrickMapping0, secure_scratch9); - s32(EmcPmacroBrickMapping1, secure_scratch10); - s32(EmcPmacroBrickMapping2, secure_scratch11); - s32(McVideoProtectGpuOverride0, secure_scratch12); - s(EmcCmdMappingCmd0_0, 6:0, secure_scratch13, 6:0); - s(EmcCmdMappingCmd0_0, 14:8, secure_scratch13, 13:7); - s(EmcCmdMappingCmd0_0, 22:16, secure_scratch13, 20:14); - s(EmcCmdMappingCmd0_0, 30:24, secure_scratch13, 27:21); - s(McVideoProtectBomAdrHi, 1:0, secure_scratch13, 29:28); - s(McVideoProtectWriteAccess, 1:0, secure_scratch13, 31:30); - s(EmcCmdMappingCmd0_1, 6:0, secure_scratch14, 6:0); - s(EmcCmdMappingCmd0_1, 14:8, secure_scratch14, 13:7); - s(EmcCmdMappingCmd0_1, 22:16, secure_scratch14, 20:14); - s(EmcCmdMappingCmd0_1, 30:24, secure_scratch14, 27:21); - s(McSecCarveoutAdrHi, 1:0, secure_scratch14, 29:28); - s(McMtsCarveoutAdrHi, 1:0, secure_scratch14, 31:30); - s(EmcCmdMappingCmd1_0, 6:0, secure_scratch15, 6:0); - s(EmcCmdMappingCmd1_0, 14:8, secure_scratch15, 13:7); - s(EmcCmdMappingCmd1_0, 22:16, secure_scratch15, 20:14); - s(EmcCmdMappingCmd1_0, 30:24, secure_scratch15, 27:21); - s(McGeneralizedCarveout5BomHi, 1:0, secure_scratch15, 29:28); - s(McGeneralizedCarveout3BomHi, 1:0, secure_scratch15, 31:30); - s(EmcCmdMappingCmd1_1, 6:0, secure_scratch16, 6:0); - s(EmcCmdMappingCmd1_1, 14:8, secure_scratch16, 13:7); - s(EmcCmdMappingCmd1_1, 22:16, secure_scratch16, 20:14); - s(EmcCmdMappingCmd1_1, 30:24, secure_scratch16, 27:21); - s(McGeneralizedCarveout2BomHi, 1:0, secure_scratch16, 29:28); - s(McGeneralizedCarveout4BomHi, 1:0, secure_scratch16, 31:30); - s(EmcCmdMappingCmd2_0, 6:0, secure_scratch17, 6:0); - s(EmcCmdMappingCmd2_0, 14:8, secure_scratch17, 13:7); - s(EmcCmdMappingCmd2_0, 22:16, secure_scratch17, 20:14); - s(EmcCmdMappingCmd2_0, 30:24, secure_scratch17, 27:21); - s(McGeneralizedCarveout1BomHi, 1:0, secure_scratch17, 29:28); - s(EmcAdrCfg, 0:0, secure_scratch17, 30:30); - s(EmcFbioSpare, 1:1, secure_scratch17, 31:31); - s(EmcCmdMappingCmd2_1, 6:0, secure_scratch18, 6:0); - s(EmcCmdMappingCmd2_1, 14:8, secure_scratch18, 13:7); - s(EmcCmdMappingCmd2_1, 22:16, secure_scratch18, 20:14); - s(EmcCmdMappingCmd2_1, 30:24, secure_scratch18, 27:21); - s(EmcFbioCfg8, 15:15, secure_scratch18, 28:28); - s(McEmemAdrCfg, 0:0, secure_scratch18, 29:29); - s(McSecCarveoutProtectWriteAccess, 0:0, secure_scratch18, 30:30); - s(McMtsCarveoutRegCtrl, 0:0, secure_scratch18, 31:31); - s(EmcCmdMappingCmd3_0, 6:0, secure_scratch19, 6:0); - s(EmcCmdMappingCmd3_0, 14:8, secure_scratch19, 13:7); - s(EmcCmdMappingCmd3_0, 22:16, secure_scratch19, 20:14); - s(EmcCmdMappingCmd3_0, 30:24, secure_scratch19, 27:21); - s(McGeneralizedCarveout2Cfg0, 6:3, secure_scratch19, 31:28); - s(EmcCmdMappingCmd3_1, 6:0, secure_scratch20, 6:0); - s(EmcCmdMappingCmd3_1, 14:8, secure_scratch20, 13:7); - s(EmcCmdMappingCmd3_1, 22:16, secure_scratch20, 20:14); - s(EmcCmdMappingCmd3_1, 30:24, secure_scratch20, 27:21); - s(McGeneralizedCarveout2Cfg0, 10:7, secure_scratch20, 31:28); - s(McGeneralizedCarveout4Cfg0, 26:0, secure_scratch39, 26:0); - s(McGeneralizedCarveout2Cfg0, 17:14, secure_scratch39, 30:27); - s(McVideoProtectVprOverride, 0:0, secure_scratch39, 31:31); - s(McGeneralizedCarveout5Cfg0, 26:0, secure_scratch40, 26:0); - s(McGeneralizedCarveout2Cfg0, 21:18, secure_scratch40, 30:27); - s(McVideoProtectVprOverride, 1:1, secure_scratch40, 31:31); - s(EmcCmdMappingCmd0_2, 6:0, secure_scratch41, 6:0); - s(EmcCmdMappingCmd0_2, 14:8, secure_scratch41, 13:7); - s(EmcCmdMappingCmd0_2, 22:16, secure_scratch41, 20:14); - s(EmcCmdMappingCmd0_2, 27:24, secure_scratch41, 24:21); - s(McGeneralizedCarveout1Cfg0, 6:3, secure_scratch41, 28:25); - s(McGeneralizedCarveout2Cfg0, 13:11, secure_scratch41, 31:29); - s(EmcCmdMappingCmd1_2, 6:0, secure_scratch42, 6:0); - s(EmcCmdMappingCmd1_2, 14:8, secure_scratch42, 13:7); - s(EmcCmdMappingCmd1_2, 22:16, secure_scratch42, 20:14); - s(EmcCmdMappingCmd1_2, 27:24, secure_scratch42, 24:21); - s(McGeneralizedCarveout1Cfg0, 13:7, secure_scratch42, 31:25); - s(EmcCmdMappingCmd2_2, 6:0, secure_scratch43, 6:0); - s(EmcCmdMappingCmd2_2, 14:8, secure_scratch43, 13:7); - s(EmcCmdMappingCmd2_2, 22:16, secure_scratch43, 20:14); - s(EmcCmdMappingCmd2_2, 27:24, secure_scratch43, 24:21); - s(McGeneralizedCarveout1Cfg0, 17:14, secure_scratch43, 28:25); - s(McGeneralizedCarveout3Cfg0, 13:11, secure_scratch43, 31:29); - s(EmcCmdMappingCmd3_2, 6:0, secure_scratch44, 6:0); - s(EmcCmdMappingCmd3_2, 14:8, secure_scratch44, 13:7); - s(EmcCmdMappingCmd3_2, 22:16, secure_scratch44, 20:14); - s(EmcCmdMappingCmd3_2, 27:24, secure_scratch44, 24:21); - s(McGeneralizedCarveout1Cfg0, 21:18, secure_scratch44, 28:25); - s(McVideoProtectVprOverride, 3:2, secure_scratch44, 30:29); - s(McVideoProtectVprOverride, 6:6, secure_scratch44, 31:31); - s(McEmemAdrCfgChannelMask, 31:9, secure_scratch45, 22:0); - s(McEmemAdrCfgDev0, 2:0, secure_scratch45, 25:23); - s(McEmemAdrCfgDev0, 9:8, secure_scratch45, 27:26); - s(McEmemAdrCfgDev0, 19:16, secure_scratch45, 31:28); - s(McEmemAdrCfgBankMask0, 31:10, secure_scratch46, 21:0); - s(McEmemAdrCfgDev1, 2:0, secure_scratch46, 24:22); - s(McEmemAdrCfgDev1, 9:8, secure_scratch46, 26:25); - s(McEmemAdrCfgDev1, 19:16, secure_scratch46, 30:27); - s(McVideoProtectVprOverride, 7:7, secure_scratch46, 31:31); - s(McEmemAdrCfgBankMask1, 31:10, secure_scratch47, 21:0); - s(McGeneralizedCarveout3Cfg0, 10:3, secure_scratch47, 29:22); - s(McVideoProtectVprOverride, 9:8, secure_scratch47, 31:30); - s(McEmemAdrCfgBankMask2, 31:10, secure_scratch48, 21:0); - s(McGeneralizedCarveout3Cfg0, 21:14, secure_scratch48, 29:22); - s(McVideoProtectVprOverride, 11:11, secure_scratch48, 30:30); - s(McVideoProtectVprOverride, 14:14, secure_scratch48, 31:31); - s(McVideoProtectGpuOverride1, 15:0, secure_scratch49, 15:0); - s(McEmemCfg, 13:0, secure_scratch49, 29:16); - s(McEmemCfg, 31:31, secure_scratch49, 30:30); - s(McVideoProtectVprOverride, 15:15, secure_scratch49, 31:31); - s(McGeneralizedCarveout3Bom, 31:17, secure_scratch50, 14:0); - s(McGeneralizedCarveout1Bom, 31:17, secure_scratch50, 29:15); - s(McVideoProtectVprOverride, 18:17, secure_scratch50, 31:30); - s(McGeneralizedCarveout4Bom, 31:17, secure_scratch51, 14:0); - s(McGeneralizedCarveout2Bom, 31:17, secure_scratch51, 29:15); - s(McVideoProtectVprOverride, 20:19, secure_scratch51, 31:30); - s(McGeneralizedCarveout5Bom, 31:17, secure_scratch52, 14:0); - s(McVideoProtectBom, 31:20, secure_scratch52, 26:15); - s(McVideoProtectVprOverride, 23:21, secure_scratch52, 29:27); - s(McVideoProtectVprOverride, 26:26, secure_scratch52, 30:30); - s(McVideoProtectVprOverride, 29:29, secure_scratch52, 31:31); - s(McVideoProtectSizeMb, 11:0, secure_scratch53, 11:0); - s(McSecCarveoutBom, 31:20, secure_scratch53, 23:12); - s(McVideoProtectVprOverride, 31:30, secure_scratch53, 25:24); - s(McVideoProtectVprOverride1, 1:0, secure_scratch53, 27:26); - s(McVideoProtectVprOverride1, 7:4, secure_scratch53, 31:28); - s(McSecCarveoutSizeMb, 11:0, secure_scratch54, 11:0); - s(McMtsCarveoutBom, 31:20, secure_scratch54, 23:12); - s(McVideoProtectVprOverride1, 15:8, secure_scratch54, 31:24); - s(McMtsCarveoutSizeMb, 11:0, secure_scratch55, 11:0); - s(McGeneralizedCarveout4Size128kb, 11:0, secure_scratch55, 23:12); - s(McVideoProtectVprOverride1, 16:16, secure_scratch55, 24:24); - s(McGeneralizedCarveout2Cfg0, 2:0, secure_scratch55, 27:25); - s(McGeneralizedCarveout2Cfg0, 25:22, secure_scratch55, 31:28); - s(McGeneralizedCarveout3Size128kb, 11:0, secure_scratch56, 11:0); - s(McGeneralizedCarveout2Size128kb, 11:0, secure_scratch56, 23:12); - s(McGeneralizedCarveout2Cfg0, 26:26, secure_scratch56, 24:24); - s(McGeneralizedCarveout1Cfg0, 2:0, secure_scratch56, 27:25); - s(McGeneralizedCarveout1Cfg0, 25:22, secure_scratch56, 31:28); - s(McGeneralizedCarveout1Size128kb, 11:0, secure_scratch57, 11:0); - s(McGeneralizedCarveout5Size128kb, 11:0, secure_scratch57, 23:12); - s(McGeneralizedCarveout1Cfg0, 26:26, secure_scratch57, 24:24); - s(McGeneralizedCarveout3Cfg0, 2:0, secure_scratch57, 27:25); - s(McGeneralizedCarveout3Cfg0, 25:22, secure_scratch57, 31:28); - s(McGeneralizedCarveout3Cfg0, 26:26, secure_scratch58, 0:0); - - s32(McGeneralizedCarveout1Access0, secure_scratch59); - s32(McGeneralizedCarveout1Access1, secure_scratch60); - s32(McGeneralizedCarveout1Access2, secure_scratch61); - s32(McGeneralizedCarveout1Access3, secure_scratch62); - s32(McGeneralizedCarveout1Access4, secure_scratch63); - s32(McGeneralizedCarveout2Access0, secure_scratch64); - s32(McGeneralizedCarveout2Access1, secure_scratch65); - s32(McGeneralizedCarveout2Access2, secure_scratch66); - s32(McGeneralizedCarveout2Access3, secure_scratch67); - s32(McGeneralizedCarveout2Access4, secure_scratch68); - s32(McGeneralizedCarveout3Access0, secure_scratch69); - s32(McGeneralizedCarveout3Access1, secure_scratch70); - s32(McGeneralizedCarveout3Access2, secure_scratch71); - s32(McGeneralizedCarveout3Access3, secure_scratch72); - s32(McGeneralizedCarveout3Access4, secure_scratch73); - s32(McGeneralizedCarveout4Access0, secure_scratch74); - s32(McGeneralizedCarveout4Access1, secure_scratch75); - s32(McGeneralizedCarveout4Access2, secure_scratch76); - s32(McGeneralizedCarveout4Access3, secure_scratch77); - s32(McGeneralizedCarveout4Access4, secure_scratch78); - s32(McGeneralizedCarveout5Access0, secure_scratch79); - s32(McGeneralizedCarveout5Access1, secure_scratch80); - s32(McGeneralizedCarveout5Access2, secure_scratch81); - s32(McGeneralizedCarveout5Access3, secure_scratch82); - s32(McGeneralizedCarveout1ForceInternalAccess0, secure_scratch84); - s32(McGeneralizedCarveout1ForceInternalAccess1, secure_scratch85); - s32(McGeneralizedCarveout1ForceInternalAccess2, secure_scratch86); - s32(McGeneralizedCarveout1ForceInternalAccess3, secure_scratch87); - s32(McGeneralizedCarveout1ForceInternalAccess4, secure_scratch88); - s32(McGeneralizedCarveout2ForceInternalAccess0, secure_scratch89); - s32(McGeneralizedCarveout2ForceInternalAccess1, secure_scratch90); - s32(McGeneralizedCarveout2ForceInternalAccess2, secure_scratch91); - s32(McGeneralizedCarveout2ForceInternalAccess3, secure_scratch92); - s32(McGeneralizedCarveout2ForceInternalAccess4, secure_scratch93); - s32(McGeneralizedCarveout3ForceInternalAccess0, secure_scratch94); - s32(McGeneralizedCarveout3ForceInternalAccess1, secure_scratch95); - s32(McGeneralizedCarveout3ForceInternalAccess2, secure_scratch96); - s32(McGeneralizedCarveout3ForceInternalAccess3, secure_scratch97); - s32(McGeneralizedCarveout3ForceInternalAccess4, secure_scratch98); - s32(McGeneralizedCarveout4ForceInternalAccess0, secure_scratch99); - s32(McGeneralizedCarveout4ForceInternalAccess1, secure_scratch100); - s32(McGeneralizedCarveout4ForceInternalAccess2, secure_scratch101); - s32(McGeneralizedCarveout4ForceInternalAccess3, secure_scratch102); - s32(McGeneralizedCarveout4ForceInternalAccess4, secure_scratch103); - s32(McGeneralizedCarveout5ForceInternalAccess0, secure_scratch104); - s32(McGeneralizedCarveout5ForceInternalAccess1, secure_scratch105); - s32(McGeneralizedCarveout5ForceInternalAccess2, secure_scratch106); - s32(McGeneralizedCarveout5ForceInternalAccess3, secure_scratch107); - - c32(0, scratch2); - s(PllMInputDivider, 7:0, scratch2, 7:0); - s(PllMFeedbackDivider, 7:0, scratch2, 15:8); - s(PllMPostDivider, 4:0, scratch2, 20:16); - s(PllMKVCO, 0:0, scratch2, 21:21); - s(PllMKCP, 1:0, scratch2, 23:22); - - c32(0, scratch35); - s(PllMSetupControl, 15:0, scratch35, 15:0); - - c32(0, scratch3); - s(PllMInputDivider, 7:0, scratch3, 7:0); - c(0x3e, scratch3, 15:8); - c(0, scratch3, 20:16); - s(PllMKVCO, 0:0, scratch3, 21:21); - s(PllMKCP, 1:0, scratch3, 23:22); - - c32(0, scratch36); - s(PllMSetupControl, 23:0, scratch36, 23:0); - - c32(0, scratch4); - s(PllMStableTime, 9:0, scratch4, 9:0); -} diff --git a/sept/sept-secondary/src/sdram_lz.inl b/sept/sept-secondary/src/sdram_lz.inl index f8f46fbd4..b202ad092 100644 --- a/sept/sept-secondary/src/sdram_lz.inl +++ b/sept/sept-secondary/src/sdram_lz.inl @@ -1,5 +1,6 @@ /* * Copyright (c) 2018 naehrwert + * Copyright (c) 2018-2020 Atmosphère-NX * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -14,7 +15,7 @@ * along with this program. If not, see . */ -static const uint8_t _dram_cfg_lz[1262] = { +static const uint8_t sdram_params_erista_lz[1262] = { 0x17, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x2C, 0x17, 0x04, 0x09, 0x00, 0x17, 0x04, 0x04, 0x17, 0x08, 0x08, 0x17, 0x10, 0x10, 0x00, 0x00, 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, @@ -122,3 +123,212 @@ static const uint8_t _dram_cfg_lz[1262] = { 0xAC, 0x38, 0x07, 0x17, 0x0D, 0x8E, 0x68, 0xA3, 0x72, 0x17, 0x83, 0x10, 0x8E, 0x68 }; + +static const uint8_t sdram_params_mariko_lz[1727] = { + 0x19, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, + 0x00, 0x2C, 0x19, 0x04, 0x09, 0x00, 0x19, 0x04, 0x04, 0x19, 0x08, 0x08, + 0x19, 0x10, 0x10, 0x19, 0x20, 0x20, 0x19, 0x40, 0x40, 0x19, 0x2A, 0x2A, + 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x19, 0x04, 0x04, 0x19, 0x09, + 0x14, 0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x19, 0x06, 0x0E, + 0x88, 0x19, 0x04, 0x04, 0x00, 0x20, 0x12, 0x19, 0x0A, 0x0C, 0x19, 0x06, + 0x08, 0x00, 0x00, 0xBC, 0xBC, 0xC5, 0xB3, 0x3C, 0x9E, 0x00, 0x00, 0x02, + 0x03, 0xE0, 0xC1, 0x04, 0x04, 0x04, 0x04, 0x19, 0x04, 0x04, 0x19, 0x04, + 0x04, 0x3F, 0x3F, 0x3F, 0x3F, 0x19, 0x04, 0x04, 0x19, 0x04, 0x04, 0x19, + 0x04, 0x38, 0x04, 0x08, 0x00, 0x00, 0x50, 0x50, 0x50, 0x00, 0xA1, 0x01, + 0x00, 0x00, 0x30, 0x19, 0x04, 0x39, 0x10, 0x00, 0x16, 0x00, 0x10, 0x90, + 0x19, 0x06, 0x81, 0x00, 0x19, 0x07, 0x74, 0x03, 0x19, 0x04, 0x04, 0x00, + 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x3A, 0x00, + 0x00, 0x00, 0x1D, 0x19, 0x0B, 0x81, 0x14, 0x09, 0x00, 0x00, 0x00, 0x04, + 0x19, 0x0B, 0x10, 0x0B, 0x19, 0x07, 0x28, 0x08, 0x19, 0x07, 0x0C, 0x19, + 0x04, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x15, 0x19, 0x07, 0x08, 0x1B, 0x19, + 0x07, 0x28, 0x20, 0x00, 0x00, 0x00, 0x06, 0x19, 0x04, 0x04, 0x19, 0x07, + 0x08, 0x19, 0x04, 0x64, 0x19, 0x04, 0x18, 0x19, 0x04, 0x30, 0x19, 0x04, + 0x10, 0x19, 0x08, 0x81, 0x00, 0x19, 0x04, 0x10, 0x19, 0x04, 0x4C, 0x0E, + 0x00, 0x00, 0x00, 0x05, 0x19, 0x07, 0x1C, 0x19, 0x09, 0x82, 0x24, 0x19, + 0x07, 0x6C, 0x19, 0x07, 0x83, 0x57, 0x80, 0x19, 0x04, 0x0A, 0x12, 0x00, + 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x1A, 0x00, 0x00, 0x00, 0x16, 0x19, + 0x07, 0x0C, 0x0A, 0x19, 0x04, 0x48, 0x19, 0x07, 0x61, 0xC1, 0x19, 0x07, + 0x50, 0x19, 0x04, 0x04, 0x19, 0x04, 0x13, 0x19, 0x04, 0x1C, 0x19, 0x04, + 0x08, 0x14, 0x19, 0x07, 0x60, 0x19, 0x08, 0x54, 0x3B, 0x19, 0x04, 0x04, + 0x19, 0x07, 0x14, 0x19, 0x04, 0x04, 0x04, 0x19, 0x07, 0x81, 0x6C, 0x19, + 0x0C, 0x0C, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91, 0x3F, 0x3A, + 0x19, 0x04, 0x5A, 0xF3, 0x0C, 0x04, 0x05, 0x1B, 0x06, 0x02, 0x03, 0x07, + 0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A, 0x24, 0x0B, 0x1E, + 0x0D, 0x0C, 0x26, 0x26, 0x03, 0x02, 0x1B, 0x1C, 0x23, 0x03, 0x04, 0x07, + 0x05, 0x06, 0x25, 0x25, 0x02, 0x0A, 0x0B, 0x1D, 0x0D, 0x08, 0x0C, 0x09, + 0x1E, 0x24, 0x26, 0x26, 0x08, 0x24, 0x06, 0x07, 0x9A, 0x19, 0x05, 0x83, + 0x3F, 0xFF, 0x00, 0xFF, 0x19, 0x10, 0x84, 0x00, 0x04, 0x00, 0x01, 0x88, + 0x00, 0x00, 0x02, 0x88, 0x00, 0x00, 0x0D, 0x88, 0x00, 0x00, 0x00, 0xC0, + 0x31, 0x31, 0x03, 0x88, 0x00, 0x00, 0x0B, 0x88, 0x5D, 0x5D, 0x0E, 0x8C, + 0x5D, 0x5D, 0x0C, 0x88, 0x08, 0x08, 0x0D, 0x8C, 0x00, 0x00, 0x0D, 0x8C, + 0x16, 0x16, 0x16, 0x88, 0x19, 0x06, 0x2C, 0x11, 0x08, 0x19, 0x10, 0x85, + 0x5F, 0x10, 0x00, 0xCC, 0x00, 0x0A, 0x00, 0x33, 0x00, 0x00, 0x00, 0x20, + 0xF3, 0x25, 0x08, 0x11, 0x19, 0x04, 0x69, 0x0F, 0x19, 0x04, 0x18, 0x19, + 0x04, 0x28, 0x01, 0x03, 0x00, 0x70, 0x00, 0x0C, 0x00, 0x01, 0x19, 0x04, + 0x0C, 0x08, 0x44, 0x00, 0x10, 0x04, 0x04, 0x00, 0x06, 0x13, 0x07, 0x19, + 0x06, 0x1C, 0xA0, 0x00, 0x2C, 0x00, 0x01, 0x37, 0x0F, 0x19, 0x05, 0x82, + 0x52, 0x02, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x04, 0x00, 0x1F, 0x22, 0x20, + 0x80, 0x0F, 0xF4, 0x20, 0x02, 0x29, 0x29, 0x29, 0x29, 0x19, 0x04, 0x04, + 0x19, 0x08, 0x08, 0x78, 0x19, 0x06, 0x85, 0x1A, 0x19, 0x05, 0x58, 0x19, + 0x40, 0x85, 0x74, 0x22, 0x00, 0x0E, 0x00, 0x10, 0x19, 0x09, 0x84, 0x22, + 0x19, 0x12, 0x18, 0x43, 0x00, 0x49, 0x00, 0x45, 0x00, 0x42, 0x00, 0x47, + 0x00, 0x49, 0x00, 0x47, 0x00, 0x46, 0x19, 0x05, 0x83, 0x60, 0x00, 0x00, + 0x10, 0x19, 0x18, 0x18, 0x00, 0x28, 0x00, 0x28, 0x19, 0x04, 0x04, 0x19, + 0x08, 0x08, 0x19, 0x10, 0x10, 0x00, 0x22, 0x19, 0x05, 0x5A, 0x19, 0x04, + 0x5C, 0x19, 0x04, 0x5E, 0x1B, 0x19, 0x05, 0x88, 0x24, 0x19, 0x10, 0x7C, + 0x19, 0x09, 0x82, 0x54, 0x40, 0x06, 0x00, 0xCC, 0x00, 0x09, 0x00, 0x4F, + 0x00, 0x51, 0x80, 0x19, 0x07, 0x18, 0x19, 0x08, 0x08, 0x19, 0x05, 0x84, + 0x40, 0xAB, 0x00, 0x0A, 0x04, 0x11, 0x19, 0x08, 0x82, 0x5C, 0x19, 0x0C, + 0x38, 0x19, 0x1C, 0x87, 0x64, 0x19, 0x0B, 0x0C, 0x19, 0x08, 0x89, 0x28, + 0x19, 0x05, 0x14, 0x01, 0x22, 0x04, 0xFF, 0x9F, 0xAF, 0x4F, 0x19, 0x09, + 0x10, 0x19, 0x0B, 0x28, 0x9F, 0xFF, 0x37, 0x19, 0x06, 0x81, 0x18, 0x32, + 0x54, 0x76, 0x10, 0x47, 0x32, 0x65, 0x10, 0x34, 0x76, 0x25, 0x01, 0x34, + 0x67, 0x25, 0x01, 0x75, 0x64, 0x32, 0x01, 0x72, 0x56, 0x34, 0x10, 0x23, + 0x74, 0x56, 0x01, 0x45, 0x32, 0x67, 0x19, 0x04, 0x24, 0x49, 0x92, 0x24, + 0x19, 0x04, 0x04, 0x19, 0x11, 0x78, 0x12, 0x19, 0x04, 0x04, 0x19, 0x13, + 0x81, 0x10, 0x20, 0x41, 0x13, 0x1F, 0x14, 0x00, 0x01, 0x00, 0x19, 0x04, + 0x7C, 0xFF, 0xFF, 0xFF, 0x7F, 0x1F, 0xD7, 0x36, 0x19, 0x07, 0x89, 0x00, + 0x09, 0x00, 0x00, 0x34, 0x10, 0x19, 0x09, 0x87, 0x70, 0x19, 0x14, 0x81, + 0x4C, 0x03, 0x00, 0x05, 0x19, 0x05, 0x86, 0x2B, 0x10, 0x02, 0x19, 0x06, + 0x87, 0x5D, 0x21, 0x19, 0x07, 0x88, 0x15, 0x19, 0x07, 0x41, 0x19, 0x06, + 0x3D, 0x19, 0x07, 0x2C, 0x80, 0x00, 0x40, 0x00, 0x04, 0x10, 0x80, 0x19, + 0x05, 0x88, 0x04, 0x81, 0x10, 0x09, 0x28, 0x93, 0x32, 0xA5, 0x44, 0x5B, + 0x8A, 0x67, 0x76, 0x19, 0x60, 0x8A, 0x54, 0x10, 0x10, 0x19, 0x04, 0x04, + 0x00, 0x00, 0x00, 0xEF, 0x00, 0xEF, 0x19, 0x08, 0x14, 0x1C, 0x1C, 0x1C, + 0x1C, 0x19, 0x11, 0x83, 0x18, 0x03, 0x08, 0x19, 0x04, 0x04, 0x00, 0x00, + 0x24, 0xFF, 0xFF, 0x00, 0x44, 0x57, 0x6E, 0x00, 0x28, 0x72, 0x39, 0x00, + 0x10, 0x9C, 0x4B, 0x00, 0x10, 0x19, 0x05, 0x83, 0x24, 0x08, 0x4C, 0x00, + 0x00, 0x80, 0x20, 0x10, 0x0A, 0x00, 0x28, 0x10, 0x00, 0x80, 0x19, 0x08, + 0x83, 0x68, 0x19, 0x0C, 0x83, 0x40, 0x19, 0x08, 0x08, 0x05, 0x19, 0x0B, + 0x84, 0x0C, 0x04, 0x19, 0x07, 0x10, 0x07, 0x19, 0x06, 0x62, 0x02, 0x01, + 0x02, 0x03, 0x00, 0x04, 0x05, 0xA3, 0x72, 0x0F, 0x0F, 0x00, 0x70, 0x19, + 0x06, 0x42, 0x1F, 0x19, 0x0A, 0x82, 0x28, 0xFF, 0x00, 0xFF, 0x19, 0x05, + 0x87, 0x18, 0x19, 0x07, 0x89, 0x56, 0x19, 0x06, 0x20, 0xF0, 0x19, 0x09, + 0x88, 0x24, 0x43, 0xC3, 0xBA, 0xE4, 0xD3, 0x1E, 0x19, 0x0C, 0x8A, 0x0B, + 0x19, 0x0A, 0x1C, 0x19, 0x10, 0x81, 0x4C, 0x19, 0x05, 0x44, 0x19, 0x09, + 0x0E, 0x19, 0x05, 0x8B, 0x66, 0x19, 0x08, 0x8A, 0x6B, 0x19, 0x11, 0x2C, + 0x76, 0x0C, 0x19, 0x0A, 0x8B, 0x4B, 0x19, 0x0F, 0x84, 0x78, 0x19, 0x06, + 0x34, 0x19, 0x17, 0x3A, 0x7E, 0x16, 0x40, 0x19, 0x0C, 0x8C, 0x03, 0x19, + 0x2A, 0x38, 0x1E, 0x19, 0x0A, 0x38, 0x19, 0x13, 0x81, 0x28, 0x00, 0xC0, + 0x19, 0x17, 0x55, 0x46, 0x24, 0x19, 0x0A, 0x81, 0x28, 0x19, 0x14, 0x38, + 0x19, 0x18, 0x81, 0x60, 0x46, 0x2C, 0x19, 0x06, 0x38, 0xEC, 0x19, 0x0D, + 0x16, 0x19, 0x16, 0x82, 0x3C, 0x19, 0x87, 0x2C, 0x90, 0x38, 0x16, 0x00, + 0x0D, 0x00, 0x0B, 0x19, 0x05, 0x84, 0x26, 0x19, 0x16, 0x18, 0x43, 0x00, + 0x45, 0x00, 0x45, 0x00, 0x43, 0x00, 0x46, 0x00, 0x47, 0x00, 0x41, 0x00, + 0x46, 0x00, 0x0C, 0x19, 0x05, 0x83, 0x3A, 0x0D, 0x19, 0x18, 0x18, 0x19, + 0x21, 0x90, 0x38, 0x16, 0x19, 0x05, 0x5A, 0x19, 0x04, 0x5C, 0x19, 0x04, + 0x5E, 0x17, 0x19, 0x07, 0x90, 0x70, 0x19, 0x89, 0x5C, 0x90, 0x38, 0x50, + 0x05, 0x19, 0x1E, 0x90, 0x38, 0xAF, 0xC9, 0x19, 0x3C, 0x90, 0x38, 0x19, + 0x0C, 0x89, 0x30, 0x19, 0x81, 0x0C, 0x90, 0x38, 0x19, 0x04, 0x18, 0x05, + 0x19, 0x0F, 0x83, 0x5C, 0x0C, 0x19, 0x81, 0x5A, 0x90, 0x38, 0x08, 0x00, + 0x00, 0x02, 0x08, 0x00, 0x00, 0x0D, 0x08, 0x19, 0x07, 0x90, 0x38, 0x08, + 0x00, 0x00, 0x0B, 0x08, 0x5D, 0x5D, 0x0E, 0x0C, 0x5D, 0x5D, 0x0C, 0x08, + 0x08, 0x08, 0x0D, 0x0C, 0x00, 0x00, 0x0D, 0x0C, 0x14, 0x14, 0x16, 0x08, + 0x19, 0x06, 0x2C, 0x19, 0x56, 0x90, 0x38, 0x19, 0x04, 0x30, 0x19, 0x0C, + 0x90, 0x38, 0x35, 0x35, 0x35, 0x35, 0x19, 0x04, 0x04, 0x19, 0x81, 0x24, + 0x90, 0x38, 0x10, 0x19, 0x05, 0xA0, 0x4A, 0x19, 0x06, 0x06, 0x19, 0x0C, + 0x0C, 0x19, 0x08, 0x08, 0x19, 0x37, 0x90, 0x38, 0x19, 0x08, 0x18, 0x80, + 0x01, 0x00, 0x00, 0x40, 0x19, 0x82, 0x34, 0x90, 0x38, 0x19, 0x08, 0x12, + 0x19, 0x81, 0x14, 0x90, 0x38, 0x19, 0x05, 0x82, 0x74, 0x19, 0x18, 0x90, + 0x38, 0x20, 0x19, 0x32, 0x90, 0x38, 0x19, 0x08, 0x10, 0x19, 0x0C, 0x90, + 0x38, 0x01, 0x19, 0x49, 0x90, 0x38, 0x80, 0x2A, 0x19, 0x06, 0x84, 0x20, + 0x19, 0x95, 0x3E, 0xA0, 0x70, 0x19, 0x83, 0x2C, 0x90, 0x38, 0x14, 0x14, + 0x19, 0x4D, 0x90, 0x38, 0x19, 0x05, 0x8A, 0x08, 0x19, 0x87, 0x2A, 0x90, + 0x38, 0x19, 0x84, 0x30, 0xA0, 0x70, 0x19, 0x84, 0x7A, 0x90, 0x38, 0x32, + 0x32, 0x32, 0x32, 0x19, 0x04, 0x04, 0x19, 0x54, 0x90, 0x38, 0x18, 0x00, + 0x0F, 0x19, 0x15, 0x90, 0x38, 0x19, 0x08, 0x18, 0x48, 0x00, 0x44, 0x00, + 0x45, 0x00, 0x44, 0x00, 0x47, 0x19, 0x07, 0x90, 0x20, 0x0D, 0x19, 0x05, + 0x83, 0x0E, 0x0D, 0x19, 0x18, 0x18, 0x00, 0x78, 0x00, 0x78, 0x19, 0x04, + 0x04, 0x19, 0x08, 0x08, 0x19, 0x10, 0x10, 0x00, 0x18, 0x19, 0x05, 0x5A, + 0x19, 0x04, 0x5C, 0x19, 0x06, 0x90, 0x38, 0x18, 0x19, 0x8B, 0x57, 0x90, + 0x38, 0x19, 0x81, 0x6F, 0xC1, 0x60, 0x19, 0x8D, 0x31, 0xA0, 0x70, 0x19, + 0x82, 0x18, 0xD2, 0x18, 0x19, 0x04, 0x34, 0x19, 0x82, 0x00, 0xD2, 0x18, + 0x19, 0x82, 0x03, 0x90, 0x38, 0x19, 0x84, 0x1D, 0xD2, 0x18, 0x19, 0x08, + 0x83, 0x7C, 0x19, 0x85, 0x16, 0xD2, 0x18, 0x19, 0x82, 0x76, 0xB1, 0x28, + 0x19, 0x6F, 0x90, 0x38, 0x19, 0x81, 0x71, 0xA0, 0x70, 0x19, 0x50, 0xB1, + 0x28, 0x19, 0x20, 0x90, 0x38, 0x19, 0x84, 0x54, 0xB1, 0x28, 0x19, 0x10, + 0x90, 0x38, 0x19, 0x87, 0x04, 0xA0, 0x70, 0x19, 0x81, 0x6F, 0x90, 0x38, + 0x19, 0x81, 0x15, 0xA0, 0x70, 0x19, 0x81, 0x2C, 0xC1, 0x60, 0x19, 0x57, + 0x90, 0x38, 0x19, 0x8C, 0x51, 0xA0, 0x70, 0x06, 0x1B, 0x04, 0x1C, 0x07, + 0x03, 0x05, 0x02, 0x00, 0x25, 0x25, 0x03, 0x00, 0x1E, 0x1D, 0x08, 0x0D, + 0x0A, 0x0C, 0x09, 0x0B, 0x26, 0x26, 0x05, 0x02, 0x04, 0x03, 0x05, 0x00, + 0x06, 0x1C, 0x1B, 0x07, 0x25, 0x25, 0x07, 0x0A, 0x0B, 0x1D, 0x0C, 0x0D, + 0x09, 0x00, 0x08, 0x1E, 0x26, 0x26, 0x09, 0x24, 0x06, 0x08, 0x2A, 0x19, + 0x82, 0x0C, 0xA0, 0x70, 0x10, 0x00, 0x14, 0x00, 0x0B, 0x00, 0x13, 0x19, + 0x18, 0x18, 0x00, 0x47, 0x00, 0x45, 0x00, 0x4F, 0x00, 0x4D, 0x00, 0x46, + 0x00, 0x46, 0x00, 0x48, 0x00, 0x48, 0x00, 0x08, 0x00, 0x0C, 0x00, 0x0C, + 0x00, 0x0B, 0x19, 0x18, 0x18, 0x19, 0x21, 0x90, 0x38, 0x10, 0x19, 0x05, + 0x5A, 0x19, 0x04, 0x5C, 0x19, 0x04, 0x5E, 0x13, 0x19, 0x13, 0x8D, 0x5D, + 0x19, 0x78, 0xA0, 0x70, 0x28, 0x40, 0xFF, 0x9F, 0x9F, 0x19, 0x1D, 0x90, + 0x38, 0x57, 0x21, 0x03, 0x64, 0x67, 0x04, 0x32, 0x51, 0x21, 0x56, 0x73, + 0x04, 0x12, 0x60, 0x35, 0x47, 0x73, 0x56, 0x04, 0x12, 0x10, 0x72, 0x65, + 0x43, 0x37, 0x21, 0x40, 0x65, 0x64, 0x21, 0x30, 0x57, 0x19, 0x3E, 0x90, + 0x38, 0x9F, 0x19, 0x06, 0x90, 0x38, 0xCF, 0x33, 0x19, 0x54, 0x90, 0x38, + 0x10, 0x08, 0x01, 0x03, 0x00, 0x50, 0x00, 0x40, 0x01, 0x19, 0x06, 0x90, + 0x38, 0x08, 0x29, 0x32, 0x93, 0xA5, 0x54, 0x4A, 0x6B, 0x76, 0x87, 0x19, + 0x82, 0x29, 0xA0, 0x70, 0xCB, 0xFA, 0xE4, 0xD3, 0xFE, 0x19, 0x82, 0x3A, + 0x90, 0x38, 0x9C, 0x19, 0x84, 0x6F, 0xD2, 0x18, 0x19, 0x82, 0x60, 0xB1, + 0x28, 0x19, 0x85, 0x44, 0xD2, 0x18, 0x19, 0x83, 0x48, 0xB1, 0x28 +}; + +static const uint32_t sdram_params_index_table_erista[28] = { + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, +}; + +static const uint32_t sdram_params_index_table_mariko[28] = { + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0, + 1, + 2, + 3, + 4, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 6, + 8, + 9, + 0xA, + 7, + 6, + 0xB, + 0xB, + 0xB, +}; diff --git a/sept/sept-secondary/src/sdram_param_t210.h b/sept/sept-secondary/src/sdram_param_t210.h deleted file mode 100644 index 328ee5109..000000000 --- a/sept/sept-secondary/src/sdram_param_t210.h +++ /dev/null @@ -1,933 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - * See file CREDITS for list of people who contributed to this - * project. - */ - -/** - * Defines the SDRAM parameter structure. - * - * Note that PLLM is used by EMC. - */ - -#ifndef _SDRAM_PARAM_T210_H_ -#define _SDRAM_PARAM_T210_H_ - -#include - -#define MEMORY_TYPE_NONE 0 -#define MEMORY_TYPE_DDR 0 -#define MEMORY_TYPE_LPDDR 0 -#define MEMORY_TYPE_DDR2 0 -#define MEMORY_TYPE_LPDDR2 1 -#define MEMORY_TYPE_DDR3 2 -#define MEMORY_TYPE_LPDDR4 3 - -/** - * Defines the SDRAM parameter structure - */ -typedef struct _sdram_params -{ - /* Specifies the type of memory device */ - uint32_t memory_type; - - /* MC/EMC clock source configuration */ - - /* Specifies the M value for PllM */ - uint32_t pllm_input_divider; - /* Specifies the N value for PllM */ - uint32_t pllm_feedback_divider; - /* Specifies the time to wait for PLLM to lock (in microseconds) */ - uint32_t pllm_stable_time; - /* Specifies misc. control bits */ - uint32_t pllm_setup_control; - /* Specifies the P value for PLLM */ - uint32_t pllm_post_divider; - /* Specifies value for Charge Pump Gain Control */ - uint32_t pllm_kcp; - /* Specifies VCO gain */ - uint32_t pllm_kvco; - /* Spare BCT param */ - uint32_t emc_bct_spare0; - /* Spare BCT param */ - uint32_t emc_bct_spare1; - /* Spare BCT param */ - uint32_t emc_bct_spare2; - /* Spare BCT param */ - uint32_t emc_bct_spare3; - /* Spare BCT param */ - uint32_t emc_bct_spare4; - /* Spare BCT param */ - uint32_t emc_bct_spare5; - /* Spare BCT param */ - uint32_t emc_bct_spare6; - /* Spare BCT param */ - uint32_t emc_bct_spare7; - /* Spare BCT param */ - uint32_t emc_bct_spare8; - /* Spare BCT param */ - uint32_t emc_bct_spare9; - /* Spare BCT param */ - uint32_t emc_bct_spare10; - /* Spare BCT param */ - uint32_t emc_bct_spare11; - /* Spare BCT param */ - uint32_t emc_bct_spare12; - /* Spare BCT param */ - uint32_t emc_bct_spare13; - - /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ - uint32_t emc_clock_source; - uint32_t emc_clock_source_dll; - - /* Defines possible override for PLLLM_MISC2 */ - uint32_t clk_rst_pllm_misc20_override; - /* enables override for PLLLM_MISC2 */ - uint32_t clk_rst_pllm_misc20_override_enable; - /* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */ - uint32_t clear_clock2_mc1; - - /* Auto-calibration of EMC pads */ - - /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ - uint32_t emc_auto_cal_interval; - /* - * Specifies the value for EMC_AUTO_CAL_CONFIG - * Note: Trigger bits are set by the SDRAM code. - */ - uint32_t emc_auto_cal_config; - - /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ - uint32_t emc_auto_cal_config2; - - /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ - uint32_t emc_auto_cal_config3; - - uint32_t emc_auto_cal_config4; - uint32_t emc_auto_cal_config5; - uint32_t emc_auto_cal_config6; - uint32_t emc_auto_cal_config7; - uint32_t emc_auto_cal_config8; - /* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */ - uint32_t emc_auto_cal_vref_sel0; - uint32_t emc_auto_cal_vref_sel1; - - /* Specifies the value for EMC_AUTO_CAL_CHANNEL */ - uint32_t emc_auto_cal_channel; - - /* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */ - uint32_t emc_pmacro_auto_cal_cfg0; - uint32_t emc_pmacro_auto_cal_cfg1; - uint32_t emc_pmacro_auto_cal_cfg2; - - uint32_t emc_pmacro_rx_term; - uint32_t emc_pmacro_dq_tx_drive; - uint32_t emc_pmacro_ca_tx_drive; - uint32_t emc_pmacro_cmd_tx_drive; - uint32_t emc_pmacro_auto_cal_common; - uint32_t emc_pmacro_zcrtl; - - /* - * Specifies the time for the calibration - * to stabilize (in microseconds) - */ - uint32_t emc_auto_cal_wait; - - uint32_t emc_xm2_comp_pad_ctrl; - uint32_t emc_xm2_comp_pad_ctrl2; - uint32_t emc_xm2_comp_pad_ctrl3; - - /* - * DRAM size information - * Specifies the value for EMC_ADR_CFG - */ - uint32_t emc_adr_cfg; - - /* - * Specifies the time to wait after asserting pin - * CKE (in microseconds) - */ - uint32_t emc_pin_program_wait; - /* Specifies the extra delay before/after pin RESET/CKE command */ - uint32_t emc_pin_extra_wait; - - uint32_t emc_pin_gpio_enable; - uint32_t emc_pin_gpio; - - /* - * Specifies the extra delay after the first writing - * of EMC_TIMING_CONTROL - */ - uint32_t emc_timing_control_wait; - - /* Timing parameters required for the SDRAM */ - - /* Specifies the value for EMC_RC */ - uint32_t emc_rc; - /* Specifies the value for EMC_RFC */ - uint32_t emc_rfc; - - uint32_t emc_rfc_pb; - uint32_t emc_ref_ctrl2; - - /* Specifies the value for EMC_RFC_SLR */ - uint32_t emc_rfc_slr; - /* Specifies the value for EMC_RAS */ - uint32_t emc_ras; - /* Specifies the value for EMC_RP */ - uint32_t emc_rp; - /* Specifies the value for EMC_R2R */ - uint32_t emc_r2r; - /* Specifies the value for EMC_W2W */ - uint32_t emc_w2w; - /* Specifies the value for EMC_R2W */ - uint32_t emc_r2w; - /* Specifies the value for EMC_W2R */ - uint32_t emc_w2r; - /* Specifies the value for EMC_R2P */ - uint32_t emc_r2p; - /* Specifies the value for EMC_W2P */ - uint32_t emc_w2p; - /* Specifies the value for EMC_RD_RCD */ - - uint32_t emc_tppd; - uint32_t emc_ccdmw; - - uint32_t emc_rd_rcd; - /* Specifies the value for EMC_WR_RCD */ - uint32_t emc_wr_rcd; - /* Specifies the value for EMC_RRD */ - uint32_t emc_rrd; - /* Specifies the value for EMC_REXT */ - uint32_t emc_rext; - /* Specifies the value for EMC_WEXT */ - uint32_t emc_wext; - /* Specifies the value for EMC_WDV */ - uint32_t emc_wdv; - - uint32_t emc_wdv_chk; - uint32_t emc_wsv; - uint32_t emc_wev; - - /* Specifies the value for EMC_WDV_MASK */ - uint32_t emc_wdv_mask; - - uint32_t emc_ws_duration; - uint32_t emc_we_duration; - - /* Specifies the value for EMC_QUSE */ - uint32_t emc_quse; - /* Specifies the value for EMC_QUSE_WIDTH */ - uint32_t emc_quse_width; - /* Specifies the value for EMC_IBDLY */ - uint32_t emc_ibdly; - - uint32_t emc_obdly; - - /* Specifies the value for EMC_EINPUT */ - uint32_t emc_einput; - /* Specifies the value for EMC_EINPUT_DURATION */ - uint32_t emc_einput_duration; - /* Specifies the value for EMC_PUTERM_EXTRA */ - uint32_t emc_puterm_extra; - /* Specifies the value for EMC_PUTERM_WIDTH */ - uint32_t emc_puterm_width; - - uint32_t emc_qrst; - uint32_t emc_qsafe; - uint32_t emc_rdv; - uint32_t emc_rdv_mask; - - uint32_t emc_rdv_early; - uint32_t emc_rdv_early_mask; - - /* Specifies the value for EMC_QPOP */ - uint32_t emc_qpop; - - /* Specifies the value for EMC_REFRESH */ - uint32_t emc_refresh; - /* Specifies the value for EMC_BURST_REFRESH_NUM */ - uint32_t emc_burst_refresh_num; - /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ - uint32_t emc_prerefresh_req_cnt; - /* Specifies the value for EMC_PDEX2WR */ - uint32_t emc_pdex2wr; - /* Specifies the value for EMC_PDEX2RD */ - uint32_t emc_pdex2rd; - /* Specifies the value for EMC_PCHG2PDEN */ - uint32_t emc_pchg2pden; - /* Specifies the value for EMC_ACT2PDEN */ - uint32_t emc_act2pden; - /* Specifies the value for EMC_AR2PDEN */ - uint32_t emc_ar2pden; - /* Specifies the value for EMC_RW2PDEN */ - uint32_t emc_rw2pden; - - uint32_t emc_cke2pden; - uint32_t emc_pdex2che; - uint32_t emc_pdex2mrr; - - /* Specifies the value for EMC_TXSR */ - uint32_t emc_txsr; - /* Specifies the value for EMC_TXSRDLL */ - uint32_t emc_txsr_dll; - /* Specifies the value for EMC_TCKE */ - uint32_t emc_tcke; - /* Specifies the value for EMC_TCKESR */ - uint32_t emc_tckesr; - /* Specifies the value for EMC_TPD */ - uint32_t emc_tpd; - /* Specifies the value for EMC_TFAW */ - uint32_t emc_tfaw; - /* Specifies the value for EMC_TRPAB */ - uint32_t emc_trpab; - /* Specifies the value for EMC_TCLKSTABLE */ - uint32_t emc_tclkstable; - /* Specifies the value for EMC_TCLKSTOP */ - uint32_t emc_tclkstop; - /* Specifies the value for EMC_TREFBW */ - uint32_t emc_trefbw; - - /* FBIO configuration values */ - - /* Specifies the value for EMC_FBIO_CFG5 */ - uint32_t emc_fbio_cfg5; - /* Specifies the value for EMC_FBIO_CFG7 */ - uint32_t emc_fbio_cfg7; - uint32_t emc_fbio_cfg8; - - /* Command mapping for CMD brick 0 */ - uint32_t emc_cmd_mapping_cmd0_0; - uint32_t emc_cmd_mapping_cmd0_1; - uint32_t emc_cmd_mapping_cmd0_2; - uint32_t emc_cmd_mapping_cmd1_0; - uint32_t emc_cmd_mapping_cmd1_1; - uint32_t emc_cmd_mapping_cmd1_2; - uint32_t emc_cmd_mapping_cmd2_0; - uint32_t emc_cmd_mapping_cmd2_1; - uint32_t emc_cmd_mapping_cmd2_2; - uint32_t emc_cmd_mapping_cmd3_0; - uint32_t emc_cmd_mapping_cmd3_1; - uint32_t emc_cmd_mapping_cmd3_2; - uint32_t emc_cmd_mapping_byte; - - /* Specifies the value for EMC_FBIO_SPARE */ - uint32_t emc_fbio_spare; - - /* Specifies the value for EMC_CFG_RSV */ - uint32_t emc_cfg_rsv; - - /* MRS command values */ - - /* Specifies the value for EMC_MRS */ - uint32_t emc_mrs; - /* Specifies the MP0 command to initialize mode registers */ - uint32_t emc_emrs; - /* Specifies the MP2 command to initialize mode registers */ - uint32_t emc_emrs2; - /* Specifies the MP3 command to initialize mode registers */ - uint32_t emc_emrs3; - /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ - uint32_t emc_mrw1; - /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ - uint32_t emc_mrw2; - /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ - uint32_t emc_mrw3; - /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ - uint32_t emc_mrw4; - - /* Specifies the programming to LPDDR4 Mode Register 3 at cold boot */ - uint32_t emc_mrw6; - /* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */ - uint32_t emc_mrw8; - /* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */ - uint32_t emc_mrw9; - /* Specifies the programming to LPDDR4 Mode Register 12 at cold boot */ - uint32_t emc_mrw10; - /* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */ - uint32_t emc_mrw12; - /* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */ - uint32_t emc_mrw13; - /* Specifies the programming to LPDDR4 Mode Register 22 at cold boot */ - uint32_t emc_mrw14; - - /* - * Specifies the programming to extra LPDDR2 Mode Register - * at cold boot - */ - uint32_t emc_mrw_extra; - /* - * Specifies the programming to extra LPDDR2 Mode Register - * at warm boot - */ - uint32_t emc_warm_boot_mrw_extra; - /* - * Specify the enable of extra Mode Register programming at - * warm boot - */ - uint32_t emc_warm_boot_extramode_reg_write_enable; - /* - * Specify the enable of extra Mode Register programming at - * cold boot - */ - uint32_t emc_extramode_reg_write_enable; - - /* Specifies the EMC_MRW reset command value */ - uint32_t emc_mrw_reset_command; - /* Specifies the EMC Reset wait time (in microseconds) */ - uint32_t emc_mrw_reset_ninit_wait; - /* Specifies the value for EMC_MRS_WAIT_CNT */ - uint32_t emc_mrs_wait_cnt; - /* Specifies the value for EMC_MRS_WAIT_CNT2 */ - uint32_t emc_mrs_wait_cnt2; - - /* EMC miscellaneous configurations */ - - /* Specifies the value for EMC_CFG */ - uint32_t emc_cfg; - /* Specifies the value for EMC_CFG_2 */ - uint32_t emc_cfg2; - /* Specifies the pipe bypass controls */ - uint32_t emc_cfg_pipe; - - uint32_t emc_cfg_pipe_clk; - uint32_t emc_fdpd_ctrl_cmd_no_ramp; - uint32_t emc_cfg_update; - - /* Specifies the value for EMC_DBG */ - uint32_t emc_dbg; - - uint32_t emc_dbg_write_mux; - - /* Specifies the value for EMC_CMDQ */ - uint32_t emc_cmd_q; - /* Specifies the value for EMC_MC2EMCQ */ - uint32_t emc_mc2emc_q; - /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ - uint32_t emc_dyn_self_ref_control; - - /* Specifies the value for MEM_INIT_DONE */ - uint32_t ahb_arbitration_xbar_ctrl_meminit_done; - - /* Specifies the value for EMC_CFG_DIG_DLL */ - uint32_t emc_cfg_dig_dll; - uint32_t emc_cfg_dig_dll_1; - - /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ - uint32_t emc_cfg_dig_dll_period; - /* Specifies the value of *DEV_SELECTN of various EMC registers */ - uint32_t emc_dev_select; - - /* Specifies the value for EMC_SEL_DPD_CTRL */ - uint32_t emc_sel_dpd_ctrl; - - /* Pads trimmer delays */ - uint32_t emc_fdpd_ctrl_dq; - uint32_t emc_fdpd_ctrl_cmd; - uint32_t emc_pmacro_ib_vref_dq_0; - uint32_t emc_pmacro_ib_vref_dq_1; - uint32_t emc_pmacro_ib_vref_dqs_0; - uint32_t emc_pmacro_ib_vref_dqs_1; - uint32_t emc_pmacro_ib_rxrt; - uint32_t emc_cfg_pipe1; - uint32_t emc_cfg_pipe2; - - /* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */ - uint32_t emc_pmacro_quse_ddll_rank0_0; - uint32_t emc_pmacro_quse_ddll_rank0_1; - uint32_t emc_pmacro_quse_ddll_rank0_2; - uint32_t emc_pmacro_quse_ddll_rank0_3; - uint32_t emc_pmacro_quse_ddll_rank0_4; - uint32_t emc_pmacro_quse_ddll_rank0_5; - uint32_t emc_pmacro_quse_ddll_rank1_0; - uint32_t emc_pmacro_quse_ddll_rank1_1; - uint32_t emc_pmacro_quse_ddll_rank1_2; - uint32_t emc_pmacro_quse_ddll_rank1_3; - uint32_t emc_pmacro_quse_ddll_rank1_4; - uint32_t emc_pmacro_quse_ddll_rank1_5; - - uint32_t emc_pmacro_ob_ddll_long_dq_rank0_0; - uint32_t emc_pmacro_ob_ddll_long_dq_rank0_1; - uint32_t emc_pmacro_ob_ddll_long_dq_rank0_2; - uint32_t emc_pmacro_ob_ddll_long_dq_rank0_3; - uint32_t emc_pmacro_ob_ddll_long_dq_rank0_4; - uint32_t emc_pmacro_ob_ddll_long_dq_rank0_5; - uint32_t emc_pmacro_ob_ddll_long_dq_rank1_0; - uint32_t emc_pmacro_ob_ddll_long_dq_rank1_1; - uint32_t emc_pmacro_ob_ddll_long_dq_rank1_2; - uint32_t emc_pmacro_ob_ddll_long_dq_rank1_3; - uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4; - uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5; - - uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4; - uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5; - - uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_0; - uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_1; - uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_2; - uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_3; - uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_0; - uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_1; - uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_2; - uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_3; - - uint32_t emc_pmacro_ddll_long_cmd_0; - uint32_t emc_pmacro_ddll_long_cmd_1; - uint32_t emc_pmacro_ddll_long_cmd_2; - uint32_t emc_pmacro_ddll_long_cmd_3; - uint32_t emc_pmacro_ddll_long_cmd_4; - uint32_t emc_pmacro_ddll_short_cmd_0; - uint32_t emc_pmacro_ddll_short_cmd_1; - uint32_t emc_pmacro_ddll_short_cmd_2; - - /* - * Specifies the delay after asserting CKE pin during a WarmBoot0 - * sequence (in microseconds) - */ - uint32_t warm_boot_wait; - - /* Specifies the value for EMC_ODT_WRITE */ - uint32_t emc_odt_write; - - /* Periodic ZQ calibration */ - - /* - * Specifies the value for EMC_ZCAL_INTERVAL - * Value 0 disables ZQ calibration - */ - uint32_t emc_zcal_interval; - /* Specifies the value for EMC_ZCAL_WAIT_CNT */ - uint32_t emc_zcal_wait_cnt; - /* Specifies the value for EMC_ZCAL_MRW_CMD */ - uint32_t emc_zcal_mrw_cmd; - - /* DRAM initialization sequence flow control */ - - /* Specifies the MRS command value for resetting DLL */ - uint32_t emc_mrs_reset_dll; - /* Specifies the command for ZQ initialization of device 0 */ - uint32_t emc_zcal_init_dev0; - /* Specifies the command for ZQ initialization of device 1 */ - uint32_t emc_zcal_init_dev1; - /* - * Specifies the wait time after programming a ZQ initialization - * command (in microseconds) - */ - uint32_t emc_zcal_init_wait; - /* - * Specifies the enable for ZQ calibration at cold boot [bit 0] - * and warm boot [bit 1] - */ - uint32_t emc_zcal_warm_cold_boot_enables; - - /* - * Specifies the MRW command to LPDDR2 for ZQ calibration - * on warmboot - */ - /* Is issued to both devices separately */ - uint32_t emc_mrw_lpddr2zcal_warm_boot; - /* - * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot - * Is issued to both devices separately - */ - uint32_t emc_zqcal_ddr3_warm_boot; - - uint32_t emc_zqcal_lpddr4_warm_boot; - - /* - * Specifies the wait time for ZQ calibration on warmboot - * (in microseconds) - */ - uint32_t emc_zcal_warm_boot_wait; - /* - * Specifies the enable for DRAM Mode Register programming - * at warm boot - */ - uint32_t emc_mrs_warm_boot_enable; - /* - * Specifies the wait time after sending an MRS DLL reset command - * in microseconds) - */ - uint32_t emc_mrs_reset_dll_wait; - /* Specifies the extra MRS command to initialize mode registers */ - uint32_t emc_mrs_extra; - /* Specifies the extra MRS command at warm boot */ - uint32_t emc_warm_boot_mrs_extra; - /* Specifies the EMRS command to enable the DDR2 DLL */ - uint32_t emc_emrs_ddr2_dll_enable; - /* Specifies the MRS command to reset the DDR2 DLL */ - uint32_t emc_mrs_ddr2_dll_reset; - /* Specifies the EMRS command to set OCD calibration */ - uint32_t emc_emrs_ddr2_ocd_calib; - /* - * Specifies the wait between initializing DDR and setting OCD - * calibration (in microseconds) - */ - uint32_t emc_ddr2_wait; - /* Specifies the value for EMC_CLKEN_OVERRIDE */ - uint32_t emc_clken_override; - /* - * Specifies LOG2 of the extra refresh numbers after booting - * Program 0 to disable - */ - uint32_t emc_extra_refresh_num; - /* Specifies the master override for all EMC clocks */ - uint32_t emc_clken_override_allwarm_boot; - /* Specifies the master override for all MC clocks */ - uint32_t mc_clken_override_allwarm_boot; - /* Specifies digital dll period, choosing between 4 to 64 ms */ - uint32_t emc_cfg_dig_dll_period_warm_boot; - - /* Pad controls */ - - /* Specifies the value for PMC_VDDP_SEL */ - uint32_t pmc_vddp_sel; - /* Specifies the wait time after programming PMC_VDDP_SEL */ - uint32_t pmc_vddp_sel_wait; - /* Specifies the value for PMC_DDR_PWR */ - uint32_t pmc_ddr_pwr; - /* Specifies the value for PMC_DDR_CFG */ - uint32_t pmc_ddr_cfg; - /* Specifies the value for PMC_IO_DPD3_REQ */ - uint32_t pmc_io_dpd3_req; - /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ - uint32_t pmc_io_dpd3_req_wait; - - uint32_t pmc_io_dpd4_req_wait; - - /* Specifies the value for PMC_REG_SHORT */ - uint32_t pmc_reg_short; - /* Specifies the value for PMC_NO_IOPOWER */ - uint32_t pmc_no_io_power; - - uint32_t pmc_ddr_ctrl_wait; - uint32_t pmc_ddr_ctrl; - - /* Specifies the value for EMC_ACPD_CONTROL */ - uint32_t emc_acpd_control; - - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ - uint32_t emc_swizzle_rank0_byte0; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ - uint32_t emc_swizzle_rank0_byte1; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ - uint32_t emc_swizzle_rank0_byte2; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ - uint32_t emc_swizzle_rank0_byte3; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ - uint32_t emc_swizzle_rank1_byte0; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ - uint32_t emc_swizzle_rank1_byte1; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ - uint32_t emc_swizzle_rank1_byte2; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ - uint32_t emc_swizzle_rank1_byte3; - - /* Specifies the value for EMC_TXDSRVTTGEN */ - uint32_t emc_txdsrvttgen; - - /* Specifies the value for EMC_DATA_BRLSHFT_0 */ - uint32_t emc_data_brlshft0; - uint32_t emc_data_brlshft1; - - uint32_t emc_dqs_brlshft0; - uint32_t emc_dqs_brlshft1; - - uint32_t emc_cmd_brlshft0; - uint32_t emc_cmd_brlshft1; - uint32_t emc_cmd_brlshft2; - uint32_t emc_cmd_brlshft3; - - uint32_t emc_quse_brlshft0; - uint32_t emc_quse_brlshft1; - uint32_t emc_quse_brlshft2; - uint32_t emc_quse_brlshft3; - - uint32_t emc_dll_cfg0; - uint32_t emc_dll_cfg1; - - uint32_t emc_pmc_scratch1; - uint32_t emc_pmc_scratch2; - uint32_t emc_pmc_scratch3; - - uint32_t emc_pmacro_pad_cfg_ctrl; - - uint32_t emc_pmacro_vttgen_ctrl0; - uint32_t emc_pmacro_vttgen_ctrl1; - uint32_t emc_pmacro_vttgen_ctrl2; - - uint32_t emc_pmacro_brick_ctrl_rfu1; - uint32_t emc_pmacro_cmd_brick_ctrl_fdpd; - uint32_t emc_pmacro_brick_ctrl_rfu2; - uint32_t emc_pmacro_data_brick_ctrl_fdpd; - uint32_t emc_pmacro_bg_bias_ctrl0; - uint32_t emc_pmacro_data_pad_rx_ctrl; - uint32_t emc_pmacro_cmd_pad_rx_ctrl; - uint32_t emc_pmacro_data_rx_term_mode; - uint32_t emc_pmacro_cmd_rx_term_mode; - uint32_t emc_pmacro_data_pad_tx_ctrl; - uint32_t emc_pmacro_common_pad_tx_ctrl; - uint32_t emc_pmacro_cmd_pad_tx_ctrl; - uint32_t emc_cfg3; - - uint32_t emc_pmacro_tx_pwrd0; - uint32_t emc_pmacro_tx_pwrd1; - uint32_t emc_pmacro_tx_pwrd2; - uint32_t emc_pmacro_tx_pwrd3; - uint32_t emc_pmacro_tx_pwrd4; - uint32_t emc_pmacro_tx_pwrd5; - - uint32_t emc_config_sample_delay; - - uint32_t emc_pmacro_brick_mapping0; - uint32_t emc_pmacro_brick_mapping1; - uint32_t emc_pmacro_brick_mapping2; - - uint32_t emc_pmacro_tx_sel_clk_src0; - uint32_t emc_pmacro_tx_sel_clk_src1; - uint32_t emc_pmacro_tx_sel_clk_src2; - uint32_t emc_pmacro_tx_sel_clk_src3; - uint32_t emc_pmacro_tx_sel_clk_src4; - uint32_t emc_pmacro_tx_sel_clk_src5; - - uint32_t emc_pmacro_ddll_bypass; - - uint32_t emc_pmacro_ddll_pwrd0; - uint32_t emc_pmacro_ddll_pwrd1; - uint32_t emc_pmacro_ddll_pwrd2; - - uint32_t emc_pmacro_cmd_ctrl0; - uint32_t emc_pmacro_cmd_ctrl1; - uint32_t emc_pmacro_cmd_ctrl2; - - /* DRAM size information */ - - /* Specifies the value for MC_EMEM_ADR_CFG */ - uint32_t mc_emem_adr_cfg; - /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ - uint32_t mc_emem_adr_cfg_dev0; - /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ - uint32_t mc_emem_adr_cfg_dev1; - - uint32_t mc_emem_adr_cfg_channel_mask; - - /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */ - uint32_t mc_emem_adr_cfg_bank_mask0; - /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ - uint32_t mc_emem_adr_cfg_bank_mask1; - /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ - uint32_t mc_emem_adr_cfg_bank_mask2; - - /* - * Specifies the value for MC_EMEM_CFG which holds the external memory - * size (in KBytes) - */ - uint32_t mc_emem_cfg; - - /* MC arbitration configuration */ - - /* Specifies the value for MC_EMEM_ARB_CFG */ - uint32_t mc_emem_arb_cfg; - /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ - uint32_t mc_emem_arb_outstanding_req; - - uint32_t emc_emem_arb_refpb_hp_ctrl; - uint32_t emc_emem_arb_refpb_bank_ctrl; - - /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ - uint32_t mc_emem_arb_timing_rcd; - /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ - uint32_t mc_emem_arb_timing_rp; - /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ - uint32_t mc_emem_arb_timing_rc; - /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ - uint32_t mc_emem_arb_timing_ras; - /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ - uint32_t mc_emem_arb_timing_faw; - /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ - uint32_t mc_emem_arb_timing_rrd; - /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ - uint32_t mc_emem_arb_timing_rap2pre; - /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ - uint32_t mc_emem_arb_timing_wap2pre; - /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ - uint32_t mc_emem_arb_timing_r2r; - /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ - uint32_t mc_emem_arb_timing_w2w; - /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ - uint32_t mc_emem_arb_timing_r2w; - /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ - uint32_t mc_emem_arb_timing_w2r; - - uint32_t mc_emem_arb_timing_rfcpb; - - /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ - uint32_t mc_emem_arb_da_turns; - /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ - uint32_t mc_emem_arb_da_covers; - /* Specifies the value for MC_EMEM_ARB_MISC0 */ - uint32_t mc_emem_arb_misc0; - /* Specifies the value for MC_EMEM_ARB_MISC1 */ - uint32_t mc_emem_arb_misc1; - uint32_t mc_emem_arb_misc2; - - /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ - uint32_t mc_emem_arb_ring1_throttle; - /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ - uint32_t mc_emem_arb_override; - /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ - uint32_t mc_emem_arb_override1; - /* Specifies the value for MC_EMEM_ARB_RSV */ - uint32_t mc_emem_arb_rsv; - - uint32_t mc_da_cfg0; - uint32_t mc_emem_arb_timing_ccdmw; - - /* Specifies the value for MC_CLKEN_OVERRIDE */ - uint32_t mc_clken_override; - - /* Specifies the value for MC_STAT_CONTROL */ - uint32_t mc_stat_control; - /* Specifies the value for MC_VIDEO_PROTECT_BOM */ - uint32_t mc_video_protect_bom; - /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ - uint32_t mc_video_protect_bom_adr_hi; - /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ - uint32_t mc_video_protect_size_mb; - /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ - uint32_t mc_video_protect_vpr_override; - /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ - uint32_t mc_video_protect_vpr_override1; - /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ - uint32_t mc_video_protect_gpu_override0; - /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ - uint32_t mc_video_protect_gpu_override1; - /* Specifies the value for MC_SEC_CARVEOUT_BOM */ - uint32_t mc_sec_carveout_bom; - /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ - uint32_t mc_sec_carveout_adr_hi; - /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ - uint32_t mc_sec_carveout_size_mb; - /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */ - uint32_t mc_video_protect_write_access; - /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */ - uint32_t mc_sec_carveout_protect_write_access; - - uint32_t mc_generalized_carveout1_bom; - uint32_t mc_generalized_carveout1_bom_hi; - uint32_t mc_generalized_carveout1_size_128kb; - uint32_t mc_generalized_carveout1_access0; - uint32_t mc_generalized_carveout1_access1; - uint32_t mc_generalized_carveout1_access2; - uint32_t mc_generalized_carveout1_access3; - uint32_t mc_generalized_carveout1_access4; - uint32_t mc_generalized_carveout1_force_internal_access0; - uint32_t mc_generalized_carveout1_force_internal_access1; - uint32_t mc_generalized_carveout1_force_internal_access2; - uint32_t mc_generalized_carveout1_force_internal_access3; - uint32_t mc_generalized_carveout1_force_internal_access4; - uint32_t mc_generalized_carveout1_cfg0; - - uint32_t mc_generalized_carveout2_bom; - uint32_t mc_generalized_carveout2_bom_hi; - uint32_t mc_generalized_carveout2_size_128kb; - uint32_t mc_generalized_carveout2_access0; - uint32_t mc_generalized_carveout2_access1; - uint32_t mc_generalized_carveout2_access2; - uint32_t mc_generalized_carveout2_access3; - uint32_t mc_generalized_carveout2_access4; - uint32_t mc_generalized_carveout2_force_internal_access0; - uint32_t mc_generalized_carveout2_force_internal_access1; - uint32_t mc_generalized_carveout2_force_internal_access2; - uint32_t mc_generalized_carveout2_force_internal_access3; - uint32_t mc_generalized_carveout2_force_internal_access4; - uint32_t mc_generalized_carveout2_cfg0; - - uint32_t mc_generalized_carveout3_bom; - uint32_t mc_generalized_carveout3_bom_hi; - uint32_t mc_generalized_carveout3_size_128kb; - uint32_t mc_generalized_carveout3_access0; - uint32_t mc_generalized_carveout3_access1; - uint32_t mc_generalized_carveout3_access2; - uint32_t mc_generalized_carveout3_access3; - uint32_t mc_generalized_carveout3_access4; - uint32_t mc_generalized_carveout3_force_internal_access0; - uint32_t mc_generalized_carveout3_force_internal_access1; - uint32_t mc_generalized_carveout3_force_internal_access2; - uint32_t mc_generalized_carveout3_force_internal_access3; - uint32_t mc_generalized_carveout3_force_internal_access4; - uint32_t mc_generalized_carveout3_cfg0; - - uint32_t mc_generalized_carveout4_bom; - uint32_t mc_generalized_carveout4_bom_hi; - uint32_t mc_generalized_carveout4_size_128kb; - uint32_t mc_generalized_carveout4_access0; - uint32_t mc_generalized_carveout4_access1; - uint32_t mc_generalized_carveout4_access2; - uint32_t mc_generalized_carveout4_access3; - uint32_t mc_generalized_carveout4_access4; - uint32_t mc_generalized_carveout4_force_internal_access0; - uint32_t mc_generalized_carveout4_force_internal_access1; - uint32_t mc_generalized_carveout4_force_internal_access2; - uint32_t mc_generalized_carveout4_force_internal_access3; - uint32_t mc_generalized_carveout4_force_internal_access4; - uint32_t mc_generalized_carveout4_cfg0; - - uint32_t mc_generalized_carveout5_bom; - uint32_t mc_generalized_carveout5_bom_hi; - uint32_t mc_generalized_carveout5_size_128kb; - uint32_t mc_generalized_carveout5_access0; - uint32_t mc_generalized_carveout5_access1; - uint32_t mc_generalized_carveout5_access2; - uint32_t mc_generalized_carveout5_access3; - uint32_t mc_generalized_carveout5_access4; - uint32_t mc_generalized_carveout5_force_internal_access0; - uint32_t mc_generalized_carveout5_force_internal_access1; - uint32_t mc_generalized_carveout5_force_internal_access2; - uint32_t mc_generalized_carveout5_force_internal_access3; - uint32_t mc_generalized_carveout5_force_internal_access4; - uint32_t mc_generalized_carveout5_cfg0; - - /* Specifies enable for CA training */ - uint32_t emc_ca_training_enable; - /* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */ - uint32_t swizzle_rank_byte_encode; - /* Specifies enable and offset for patched boot rom write */ - uint32_t boot_rom_patch_control; - /* Specifies data for patched boot rom write */ - uint32_t boot_rom_patch_data; - - /* Specifies the value for MC_MTS_CARVEOUT_BOM */ - uint32_t mc_mts_carveout_bom; - /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ - uint32_t mc_mts_carveout_adr_hi; - /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ - uint32_t mc_mts_carveout_size_mb; - /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ - uint32_t mc_mts_carveout_reg_ctrl; -} sdram_params_t; - -#endif diff --git a/sept/sept-secondary/src/sdram_param_t210_lp0.h b/sept/sept-secondary/src/sdram_param_t210_lp0.h deleted file mode 100644 index 0a1d41840..000000000 --- a/sept/sept-secondary/src/sdram_param_t210_lp0.h +++ /dev/null @@ -1,964 +0,0 @@ -/* - * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved. - * Copyright 2014 Google Inc. - * Copyright (c) 2018 CTCaer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -/** - * Defines the SDRAM parameter structure. - * - * Note that PLLM is used by EMC. The field names are in camel case to ease - * directly converting BCT config files (*.cfg) into C structure. - */ - -#ifndef __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ -#define __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ - -#include - -enum -{ - /* Specifies the memory type to be undefined */ - NvBootMemoryType_None = 0, - - /* Specifies the memory type to be DDR SDRAM */ - NvBootMemoryType_Ddr = 0, - - /* Specifies the memory type to be LPDDR SDRAM */ - NvBootMemoryType_LpDdr = 0, - - /* Specifies the memory type to be DDR2 SDRAM */ - NvBootMemoryType_Ddr2 = 0, - - /* Specifies the memory type to be LPDDR2 SDRAM */ - NvBootMemoryType_LpDdr2, - - /* Specifies the memory type to be DDR3 SDRAM */ - NvBootMemoryType_Ddr3, - - /* Specifies the memory type to be LPDDR4 SDRAM */ - NvBootMemoryType_LpDdr4, - - NvBootMemoryType_Num, - - /* Specifies an entry in the ram_code table that's not in use */ - NvBootMemoryType_Unused = 0X7FFFFFF, -}; - -/** - * Defines the SDRAM parameter structure - */ -struct sdram_params -{ - - /* Specifies the type of memory device */ - uint32_t MemoryType; - - /* MC/EMC clock source configuration */ - - /* Specifies the M value for PllM */ - uint32_t PllMInputDivider; - /* Specifies the N value for PllM */ - uint32_t PllMFeedbackDivider; - /* Specifies the time to wait for PLLM to lock (in microseconds) */ - uint32_t PllMStableTime; - /* Specifies misc. control bits */ - uint32_t PllMSetupControl; - /* Specifies the P value for PLLM */ - uint32_t PllMPostDivider; - /* Specifies value for Charge Pump Gain Control */ - uint32_t PllMKCP; - /* Specifies VCO gain */ - uint32_t PllMKVCO; - /* Spare BCT param */ - uint32_t EmcBctSpare0; - /* Spare BCT param */ - uint32_t EmcBctSpare1; - /* Spare BCT param */ - uint32_t EmcBctSpare2; - /* Spare BCT param */ - uint32_t EmcBctSpare3; - /* Spare BCT param */ - uint32_t EmcBctSpare4; - /* Spare BCT param */ - uint32_t EmcBctSpare5; - /* Spare BCT param */ - uint32_t EmcBctSpare6; - /* Spare BCT param */ - uint32_t EmcBctSpare7; - /* Spare BCT param */ - uint32_t EmcBctSpare8; - /* Spare BCT param */ - uint32_t EmcBctSpare9; - /* Spare BCT param */ - uint32_t EmcBctSpare10; - /* Spare BCT param */ - uint32_t EmcBctSpare11; - /* Spare BCT param */ - uint32_t EmcBctSpare12; - /* Spare BCT param */ - uint32_t EmcBctSpare13; - - /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ - uint32_t EmcClockSource; - uint32_t EmcClockSourceDll; - - /* Defines possible override for PLLLM_MISC2 */ - uint32_t ClkRstControllerPllmMisc2Override; - /* enables override for PLLLM_MISC2 */ - uint32_t ClkRstControllerPllmMisc2OverrideEnable; - /* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */ - uint32_t ClearClk2Mc1; - - /* Auto-calibration of EMC pads */ - - /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ - uint32_t EmcAutoCalInterval; - /* - * Specifies the value for EMC_AUTO_CAL_CONFIG - * Note: Trigger bits are set by the SDRAM code. - */ - uint32_t EmcAutoCalConfig; - - /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ - uint32_t EmcAutoCalConfig2; - - /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ - uint32_t EmcAutoCalConfig3; - - /* Specifies the values for EMC_AUTO_CAL_CONFIG4-8 */ - uint32_t EmcAutoCalConfig4; - uint32_t EmcAutoCalConfig5; - uint32_t EmcAutoCalConfig6; - uint32_t EmcAutoCalConfig7; - uint32_t EmcAutoCalConfig8; - - /* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */ - uint32_t EmcAutoCalVrefSel0; - uint32_t EmcAutoCalVrefSel1; - - /* Specifies the value for EMC_AUTO_CAL_CHANNEL */ - uint32_t EmcAutoCalChannel; - - /* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */ - uint32_t EmcPmacroAutocalCfg0; - uint32_t EmcPmacroAutocalCfg1; - uint32_t EmcPmacroAutocalCfg2; - uint32_t EmcPmacroRxTerm; - uint32_t EmcPmacroDqTxDrv; - uint32_t EmcPmacroCaTxDrv; - uint32_t EmcPmacroCmdTxDrv; - uint32_t EmcPmacroAutocalCfgCommon; - uint32_t EmcPmacroZctrl; - - /* - * Specifies the time for the calibration - * to stabilize (in microseconds) - */ - uint32_t EmcAutoCalWait; - - uint32_t EmcXm2CompPadCtrl; - uint32_t EmcXm2CompPadCtrl2; - uint32_t EmcXm2CompPadCtrl3; - - /* - * DRAM size information - * Specifies the value for EMC_ADR_CFG - */ - uint32_t EmcAdrCfg; - - /* - * Specifies the time to wait after asserting pin - * CKE (in microseconds) - */ - uint32_t EmcPinProgramWait; - /* Specifies the extra delay before/after pin RESET/CKE command */ - uint32_t EmcPinExtraWait; - - uint32_t EmcPinGpioEn; - uint32_t EmcPinGpio; - - /* - * Specifies the extra delay after the first writing - * of EMC_TIMING_CONTROL - */ - uint32_t EmcTimingControlWait; - - /* Timing parameters required for the SDRAM */ - - /* Specifies the value for EMC_RC */ - uint32_t EmcRc; - /* Specifies the value for EMC_RFC */ - uint32_t EmcRfc; - /* Specifies the value for EMC_RFC_PB */ - uint32_t EmcRfcPb; - /* Specifies the value for EMC_RFC_CTRL2 */ - uint32_t EmcRefctrl2; - /* Specifies the value for EMC_RFC_SLR */ - uint32_t EmcRfcSlr; - /* Specifies the value for EMC_RAS */ - uint32_t EmcRas; - /* Specifies the value for EMC_RP */ - uint32_t EmcRp; - /* Specifies the value for EMC_R2R */ - uint32_t EmcR2r; - /* Specifies the value for EMC_W2W */ - uint32_t EmcW2w; - /* Specifies the value for EMC_R2W */ - uint32_t EmcR2w; - /* Specifies the value for EMC_W2R */ - uint32_t EmcW2r; - /* Specifies the value for EMC_R2P */ - uint32_t EmcR2p; - /* Specifies the value for EMC_W2P */ - uint32_t EmcW2p; - - uint32_t EmcTppd; - uint32_t EmcCcdmw; - - /* Specifies the value for EMC_RD_RCD */ - uint32_t EmcRdRcd; - /* Specifies the value for EMC_WR_RCD */ - uint32_t EmcWrRcd; - /* Specifies the value for EMC_RRD */ - uint32_t EmcRrd; - /* Specifies the value for EMC_REXT */ - uint32_t EmcRext; - /* Specifies the value for EMC_WEXT */ - uint32_t EmcWext; - /* Specifies the value for EMC_WDV */ - uint32_t EmcWdv; - - uint32_t EmcWdvChk; - uint32_t EmcWsv; - uint32_t EmcWev; - - /* Specifies the value for EMC_WDV_MASK */ - uint32_t EmcWdvMask; - - uint32_t EmcWsDuration; - uint32_t EmcWeDuration; - - /* Specifies the value for EMC_QUSE */ - uint32_t EmcQUse; - /* Specifies the value for EMC_QUSE_WIDTH */ - uint32_t EmcQuseWidth; - /* Specifies the value for EMC_IBDLY */ - uint32_t EmcIbdly; - /* Specifies the value for EMC_OBDLY */ - uint32_t EmcObdly; - /* Specifies the value for EMC_EINPUT */ - uint32_t EmcEInput; - /* Specifies the value for EMC_EINPUT_DURATION */ - uint32_t EmcEInputDuration; - /* Specifies the value for EMC_PUTERM_EXTRA */ - uint32_t EmcPutermExtra; - /* Specifies the value for EMC_PUTERM_WIDTH */ - uint32_t EmcPutermWidth; - /* Specifies the value for EMC_PUTERM_ADJ */ - ////uint32_t EmcPutermAdj; - - /* Specifies the value for EMC_QRST */ - uint32_t EmcQRst; - /* Specifies the value for EMC_QSAFE */ - uint32_t EmcQSafe; - /* Specifies the value for EMC_RDV */ - uint32_t EmcRdv; - /* Specifies the value for EMC_RDV_MASK */ - uint32_t EmcRdvMask; - /* Specifies the value for EMC_RDV_EARLY */ - uint32_t EmcRdvEarly; - /* Specifies the value for EMC_RDV_EARLY_MASK */ - uint32_t EmcRdvEarlyMask; - /* Specifies the value for EMC_QPOP */ - uint32_t EmcQpop; - - /* Specifies the value for EMC_REFRESH */ - uint32_t EmcRefresh; - /* Specifies the value for EMC_BURST_REFRESH_NUM */ - uint32_t EmcBurstRefreshNum; - /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ - uint32_t EmcPreRefreshReqCnt; - /* Specifies the value for EMC_PDEX2WR */ - uint32_t EmcPdEx2Wr; - /* Specifies the value for EMC_PDEX2RD */ - uint32_t EmcPdEx2Rd; - /* Specifies the value for EMC_PCHG2PDEN */ - uint32_t EmcPChg2Pden; - /* Specifies the value for EMC_ACT2PDEN */ - uint32_t EmcAct2Pden; - /* Specifies the value for EMC_AR2PDEN */ - uint32_t EmcAr2Pden; - /* Specifies the value for EMC_RW2PDEN */ - uint32_t EmcRw2Pden; - /* Specifies the value for EMC_CKE2PDEN */ - uint32_t EmcCke2Pden; - /* Specifies the value for EMC_PDEX2CKE */ - uint32_t EmcPdex2Cke; - /* Specifies the value for EMC_PDEX2MRR */ - uint32_t EmcPdex2Mrr; - /* Specifies the value for EMC_TXSR */ - uint32_t EmcTxsr; - /* Specifies the value for EMC_TXSRDLL */ - uint32_t EmcTxsrDll; - /* Specifies the value for EMC_TCKE */ - uint32_t EmcTcke; - /* Specifies the value for EMC_TCKESR */ - uint32_t EmcTckesr; - /* Specifies the value for EMC_TPD */ - uint32_t EmcTpd; - /* Specifies the value for EMC_TFAW */ - uint32_t EmcTfaw; - /* Specifies the value for EMC_TRPAB */ - uint32_t EmcTrpab; - /* Specifies the value for EMC_TCLKSTABLE */ - uint32_t EmcTClkStable; - /* Specifies the value for EMC_TCLKSTOP */ - uint32_t EmcTClkStop; - /* Specifies the value for EMC_TREFBW */ - uint32_t EmcTRefBw; - - /* FBIO configuration values */ - - /* Specifies the value for EMC_FBIO_CFG5 */ - uint32_t EmcFbioCfg5; - /* Specifies the value for EMC_FBIO_CFG7 */ - uint32_t EmcFbioCfg7; - /* Specifies the value for EMC_FBIO_CFG8 */ - uint32_t EmcFbioCfg8; - - /* Command mapping for CMD brick 0 */ - uint32_t EmcCmdMappingCmd0_0; - uint32_t EmcCmdMappingCmd0_1; - uint32_t EmcCmdMappingCmd0_2; - uint32_t EmcCmdMappingCmd1_0; - uint32_t EmcCmdMappingCmd1_1; - uint32_t EmcCmdMappingCmd1_2; - uint32_t EmcCmdMappingCmd2_0; - uint32_t EmcCmdMappingCmd2_1; - uint32_t EmcCmdMappingCmd2_2; - uint32_t EmcCmdMappingCmd3_0; - uint32_t EmcCmdMappingCmd3_1; - uint32_t EmcCmdMappingCmd3_2; - uint32_t EmcCmdMappingByte; - - /* Specifies the value for EMC_FBIO_SPARE */ - uint32_t EmcFbioSpare; - - /* Specifies the value for EMC_CFG_RSV */ - uint32_t EmcCfgRsv; - - /* MRS command values */ - - /* Specifies the value for EMC_MRS */ - uint32_t EmcMrs; - /* Specifies the MP0 command to initialize mode registers */ - uint32_t EmcEmrs; - /* Specifies the MP2 command to initialize mode registers */ - uint32_t EmcEmrs2; - /* Specifies the MP3 command to initialize mode registers */ - uint32_t EmcEmrs3; - /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ - uint32_t EmcMrw1; - /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ - uint32_t EmcMrw2; - /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ - uint32_t EmcMrw3; - /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ - uint32_t EmcMrw4; - /* Specifies the programming to LPDDR2 Mode Register 3? at cold boot */ - uint32_t EmcMrw6; - /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ - uint32_t EmcMrw8; - /* Specifies the programming to LPDDR2 Mode Register 11? at cold boot */ - uint32_t EmcMrw9; - /* Specifies the programming to LPDDR2 Mode Register 12 at cold boot */ - uint32_t EmcMrw10; - /* Specifies the programming to LPDDR2 Mode Register 14 at cold boot */ - uint32_t EmcMrw12; - /* Specifies the programming to LPDDR2 Mode Register 14? at cold boot */ - uint32_t EmcMrw13; - /* Specifies the programming to LPDDR2 Mode Register 22 at cold boot */ - uint32_t EmcMrw14; - /* - * Specifies the programming to extra LPDDR2 Mode Register - * at cold boot - */ - uint32_t EmcMrwExtra; - /* - * Specifies the programming to extra LPDDR2 Mode Register - * at warm boot - */ - uint32_t EmcWarmBootMrwExtra; - /* - * Specify the enable of extra Mode Register programming at - * warm boot - */ - uint32_t EmcWarmBootExtraModeRegWriteEnable; - /* - * Specify the enable of extra Mode Register programming at - * cold boot - */ - uint32_t EmcExtraModeRegWriteEnable; - - /* Specifies the EMC_MRW reset command value */ - uint32_t EmcMrwResetCommand; - /* Specifies the EMC Reset wait time (in microseconds) */ - uint32_t EmcMrwResetNInitWait; - /* Specifies the value for EMC_MRS_WAIT_CNT */ - uint32_t EmcMrsWaitCnt; - /* Specifies the value for EMC_MRS_WAIT_CNT2 */ - uint32_t EmcMrsWaitCnt2; - - /* EMC miscellaneous configurations */ - - /* Specifies the value for EMC_CFG */ - uint32_t EmcCfg; - /* Specifies the value for EMC_CFG_2 */ - uint32_t EmcCfg2; - /* Specifies the pipe bypass controls */ - uint32_t EmcCfgPipe; - uint32_t EmcCfgPipeClk; - uint32_t EmcFdpdCtrlCmdNoRamp; - uint32_t EmcCfgUpdate; - - /* Specifies the value for EMC_DBG */ - uint32_t EmcDbg; - uint32_t EmcDbgWriteMux; - - /* Specifies the value for EMC_CMDQ */ - uint32_t EmcCmdQ; - /* Specifies the value for EMC_MC2EMCQ */ - uint32_t EmcMc2EmcQ; - /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ - uint32_t EmcDynSelfRefControl; - - /* Specifies the value for MEM_INIT_DONE */ - uint32_t AhbArbitrationXbarCtrlMemInitDone; - - /* Specifies the value for EMC_CFG_DIG_DLL */ - uint32_t EmcCfgDigDll; - uint32_t EmcCfgDigDll_1; - /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ - uint32_t EmcCfgDigDllPeriod; - /* Specifies the value of *DEV_SELECTN of various EMC registers */ - uint32_t EmcDevSelect; - - /* Specifies the value for EMC_SEL_DPD_CTRL */ - uint32_t EmcSelDpdCtrl; - - /* Pads trimmer delays */ - uint32_t EmcFdpdCtrlDq; - uint32_t EmcFdpdCtrlCmd; - uint32_t EmcPmacroIbVrefDq_0; - uint32_t EmcPmacroIbVrefDq_1; - uint32_t EmcPmacroIbVrefDqs_0; - uint32_t EmcPmacroIbVrefDqs_1; - uint32_t EmcPmacroIbRxrt; - uint32_t EmcCfgPipe1; - uint32_t EmcCfgPipe2; - - /* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */ - uint32_t EmcPmacroQuseDdllRank0_0; - uint32_t EmcPmacroQuseDdllRank0_1; - uint32_t EmcPmacroQuseDdllRank0_2; - uint32_t EmcPmacroQuseDdllRank0_3; - uint32_t EmcPmacroQuseDdllRank0_4; - uint32_t EmcPmacroQuseDdllRank0_5; - uint32_t EmcPmacroQuseDdllRank1_0; - uint32_t EmcPmacroQuseDdllRank1_1; - uint32_t EmcPmacroQuseDdllRank1_2; - uint32_t EmcPmacroQuseDdllRank1_3; - uint32_t EmcPmacroQuseDdllRank1_4; - uint32_t EmcPmacroQuseDdllRank1_5; - - uint32_t EmcPmacroObDdllLongDqRank0_0; - uint32_t EmcPmacroObDdllLongDqRank0_1; - uint32_t EmcPmacroObDdllLongDqRank0_2; - uint32_t EmcPmacroObDdllLongDqRank0_3; - uint32_t EmcPmacroObDdllLongDqRank0_4; - uint32_t EmcPmacroObDdllLongDqRank0_5; - uint32_t EmcPmacroObDdllLongDqRank1_0; - uint32_t EmcPmacroObDdllLongDqRank1_1; - uint32_t EmcPmacroObDdllLongDqRank1_2; - uint32_t EmcPmacroObDdllLongDqRank1_3; - uint32_t EmcPmacroObDdllLongDqRank1_4; - uint32_t EmcPmacroObDdllLongDqRank1_5; - - uint32_t EmcPmacroObDdllLongDqsRank0_0; - uint32_t EmcPmacroObDdllLongDqsRank0_1; - uint32_t EmcPmacroObDdllLongDqsRank0_2; - uint32_t EmcPmacroObDdllLongDqsRank0_3; - uint32_t EmcPmacroObDdllLongDqsRank0_4; - uint32_t EmcPmacroObDdllLongDqsRank0_5; - uint32_t EmcPmacroObDdllLongDqsRank1_0; - uint32_t EmcPmacroObDdllLongDqsRank1_1; - uint32_t EmcPmacroObDdllLongDqsRank1_2; - uint32_t EmcPmacroObDdllLongDqsRank1_3; - uint32_t EmcPmacroObDdllLongDqsRank1_4; - uint32_t EmcPmacroObDdllLongDqsRank1_5; - - uint32_t EmcPmacroIbDdllLongDqsRank0_0; - uint32_t EmcPmacroIbDdllLongDqsRank0_1; - uint32_t EmcPmacroIbDdllLongDqsRank0_2; - uint32_t EmcPmacroIbDdllLongDqsRank0_3; - uint32_t EmcPmacroIbDdllLongDqsRank1_0; - uint32_t EmcPmacroIbDdllLongDqsRank1_1; - uint32_t EmcPmacroIbDdllLongDqsRank1_2; - uint32_t EmcPmacroIbDdllLongDqsRank1_3; - - uint32_t EmcPmacroDdllLongCmd_0; - uint32_t EmcPmacroDdllLongCmd_1; - uint32_t EmcPmacroDdllLongCmd_2; - uint32_t EmcPmacroDdllLongCmd_3; - uint32_t EmcPmacroDdllLongCmd_4; - uint32_t EmcPmacroDdllShortCmd_0; - uint32_t EmcPmacroDdllShortCmd_1; - uint32_t EmcPmacroDdllShortCmd_2; - - /* - * Specifies the delay after asserting CKE pin during a WarmBoot0 - * sequence (in microseconds) - */ - uint32_t WarmBootWait; - - /* Specifies the value for EMC_ODT_WRITE */ - uint32_t EmcOdtWrite; - - /* Periodic ZQ calibration */ - - /* - * Specifies the value for EMC_ZCAL_INTERVAL - * Value 0 disables ZQ calibration - */ - uint32_t EmcZcalInterval; - /* Specifies the value for EMC_ZCAL_WAIT_CNT */ - uint32_t EmcZcalWaitCnt; - /* Specifies the value for EMC_ZCAL_MRW_CMD */ - uint32_t EmcZcalMrwCmd; - - /* DRAM initialization sequence flow control */ - - /* Specifies the MRS command value for resetting DLL */ - uint32_t EmcMrsResetDll; - /* Specifies the command for ZQ initialization of device 0 */ - uint32_t EmcZcalInitDev0; - /* Specifies the command for ZQ initialization of device 1 */ - uint32_t EmcZcalInitDev1; - /* - * Specifies the wait time after programming a ZQ initialization - * command (in microseconds) - */ - uint32_t EmcZcalInitWait; - /* - * Specifies the enable for ZQ calibration at cold boot [bit 0] - * and warm boot [bit 1] - */ - uint32_t EmcZcalWarmColdBootEnables; - - /* - * Specifies the MRW command to LPDDR2 for ZQ calibration - * on warmboot - */ - /* Is issued to both devices separately */ - uint32_t EmcMrwLpddr2ZcalWarmBoot; - /* - * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot - * Is issued to both devices separately - */ - uint32_t EmcZqCalDdr3WarmBoot; - uint32_t EmcZqCalLpDdr4WarmBoot; - /* - * Specifies the wait time for ZQ calibration on warmboot - * (in microseconds) - */ - uint32_t EmcZcalWarmBootWait; - /* - * Specifies the enable for DRAM Mode Register programming - * at warm boot - */ - uint32_t EmcMrsWarmBootEnable; - /* - * Specifies the wait time after sending an MRS DLL reset command - * in microseconds) - */ - uint32_t EmcMrsResetDllWait; - /* Specifies the extra MRS command to initialize mode registers */ - uint32_t EmcMrsExtra; - /* Specifies the extra MRS command at warm boot */ - uint32_t EmcWarmBootMrsExtra; - /* Specifies the EMRS command to enable the DDR2 DLL */ - uint32_t EmcEmrsDdr2DllEnable; - /* Specifies the MRS command to reset the DDR2 DLL */ - uint32_t EmcMrsDdr2DllReset; - /* Specifies the EMRS command to set OCD calibration */ - uint32_t EmcEmrsDdr2OcdCalib; - /* - * Specifies the wait between initializing DDR and setting OCD - * calibration (in microseconds) - */ - uint32_t EmcDdr2Wait; - /* Specifies the value for EMC_CLKEN_OVERRIDE */ - uint32_t EmcClkenOverride; - - /* - * Specifies LOG2 of the extra refresh numbers after booting - * Program 0 to disable - */ - uint32_t EmcExtraRefreshNum; - /* Specifies the master override for all EMC clocks */ - uint32_t EmcClkenOverrideAllWarmBoot; - /* Specifies the master override for all MC clocks */ - uint32_t McClkenOverrideAllWarmBoot; - /* Specifies digital dll period, choosing between 4 to 64 ms */ - uint32_t EmcCfgDigDllPeriodWarmBoot; - - /* Pad controls */ - - /* Specifies the value for PMC_VDDP_SEL */ - uint32_t PmcVddpSel; - /* Specifies the wait time after programming PMC_VDDP_SEL */ - uint32_t PmcVddpSelWait; - /* Specifies the value for PMC_DDR_PWR */ - uint32_t PmcDdrPwr; - /* Specifies the value for PMC_DDR_CFG */ - uint32_t PmcDdrCfg; - /* Specifies the value for PMC_IO_DPD3_REQ */ - uint32_t PmcIoDpd3Req; - /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ - uint32_t PmcIoDpd3ReqWait; - uint32_t PmcIoDpd4ReqWait; - - /* Specifies the value for PMC_REG_SHORT */ - uint32_t PmcRegShort; - /* Specifies the value for PMC_NO_IOPOWER */ - uint32_t PmcNoIoPower; - - uint32_t PmcDdrCntrlWait; - uint32_t PmcDdrCntrl; - - /* Specifies the value for EMC_ACPD_CONTROL */ - uint32_t EmcAcpdControl; - - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */ - ////uint32_t EmcSwizzleRank0ByteCfg; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ - uint32_t EmcSwizzleRank0Byte0; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ - uint32_t EmcSwizzleRank0Byte1; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ - uint32_t EmcSwizzleRank0Byte2; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ - uint32_t EmcSwizzleRank0Byte3; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */ - ////uint32_t EmcSwizzleRank1ByteCfg; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ - uint32_t EmcSwizzleRank1Byte0; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ - uint32_t EmcSwizzleRank1Byte1; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ - uint32_t EmcSwizzleRank1Byte2; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ - uint32_t EmcSwizzleRank1Byte3; - - /* Specifies the value for EMC_TXDSRVTTGEN */ - uint32_t EmcTxdsrvttgen; - - /* Specifies the value for EMC_DATA_BRLSHFT_0 */ - uint32_t EmcDataBrlshft0; - uint32_t EmcDataBrlshft1; - - uint32_t EmcDqsBrlshft0; - uint32_t EmcDqsBrlshft1; - - uint32_t EmcCmdBrlshft0; - uint32_t EmcCmdBrlshft1; - uint32_t EmcCmdBrlshft2; - uint32_t EmcCmdBrlshft3; - - uint32_t EmcQuseBrlshft0; - uint32_t EmcQuseBrlshft1; - uint32_t EmcQuseBrlshft2; - uint32_t EmcQuseBrlshft3; - - uint32_t EmcDllCfg0; - uint32_t EmcDllCfg1; - - uint32_t EmcPmcScratch1; - uint32_t EmcPmcScratch2; - uint32_t EmcPmcScratch3; - - uint32_t EmcPmacroPadCfgCtrl; - - uint32_t EmcPmacroVttgenCtrl0; - uint32_t EmcPmacroVttgenCtrl1; - uint32_t EmcPmacroVttgenCtrl2; - - uint32_t EmcPmacroBrickCtrlRfu1; - uint32_t EmcPmacroCmdBrickCtrlFdpd; - uint32_t EmcPmacroBrickCtrlRfu2; - uint32_t EmcPmacroDataBrickCtrlFdpd; - uint32_t EmcPmacroBgBiasCtrl0; - uint32_t EmcPmacroDataPadRxCtrl; - uint32_t EmcPmacroCmdPadRxCtrl; - uint32_t EmcPmacroDataRxTermMode; - uint32_t EmcPmacroCmdRxTermMode; - uint32_t EmcPmacroDataPadTxCtrl; - uint32_t EmcPmacroCommonPadTxCtrl; - uint32_t EmcPmacroCmdPadTxCtrl; - uint32_t EmcCfg3; - - uint32_t EmcPmacroTxPwrd0; - uint32_t EmcPmacroTxPwrd1; - uint32_t EmcPmacroTxPwrd2; - uint32_t EmcPmacroTxPwrd3; - uint32_t EmcPmacroTxPwrd4; - uint32_t EmcPmacroTxPwrd5; - - uint32_t EmcConfigSampleDelay; - - uint32_t EmcPmacroBrickMapping0; - uint32_t EmcPmacroBrickMapping1; - uint32_t EmcPmacroBrickMapping2; - - uint32_t EmcPmacroTxSelClkSrc0; - uint32_t EmcPmacroTxSelClkSrc1; - uint32_t EmcPmacroTxSelClkSrc2; - uint32_t EmcPmacroTxSelClkSrc3; - uint32_t EmcPmacroTxSelClkSrc4; - uint32_t EmcPmacroTxSelClkSrc5; - - uint32_t EmcPmacroDdllBypass; - - uint32_t EmcPmacroDdllPwrd0; - uint32_t EmcPmacroDdllPwrd1; - uint32_t EmcPmacroDdllPwrd2; - - uint32_t EmcPmacroCmdCtrl0; - uint32_t EmcPmacroCmdCtrl1; - uint32_t EmcPmacroCmdCtrl2; - - /* DRAM size information */ - - /* Specifies the value for MC_EMEM_ADR_CFG */ - uint32_t McEmemAdrCfg; - /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ - uint32_t McEmemAdrCfgDev0; - /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ - uint32_t McEmemAdrCfgDev1; - uint32_t McEmemAdrCfgChannelMask; - - /* Specifies the value for MC_EMEM_BANK_SWIZZLECfg0 */ - uint32_t McEmemAdrCfgBankMask0; - /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ - uint32_t McEmemAdrCfgBankMask1; - /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ - uint32_t McEmemAdrCfgBankMask2; - - /* - * Specifies the value for MC_EMEM_CFG which holds the external memory - * size (in KBytes) - */ - uint32_t McEmemCfg; - - /* MC arbitration configuration */ - - /* Specifies the value for MC_EMEM_ARB_CFG */ - uint32_t McEmemArbCfg; - /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ - uint32_t McEmemArbOutstandingReq; - - uint32_t McEmemArbRefpbHpCtrl; - uint32_t McEmemArbRefpbBankCtrl; - - /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ - uint32_t McEmemArbTimingRcd; - /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ - uint32_t McEmemArbTimingRp; - /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ - uint32_t McEmemArbTimingRc; - /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ - uint32_t McEmemArbTimingRas; - /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ - uint32_t McEmemArbTimingFaw; - /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ - uint32_t McEmemArbTimingRrd; - /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ - uint32_t McEmemArbTimingRap2Pre; - /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ - uint32_t McEmemArbTimingWap2Pre; - /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ - uint32_t McEmemArbTimingR2R; - /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ - uint32_t McEmemArbTimingW2W; - /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ - uint32_t McEmemArbTimingR2W; - /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ - uint32_t McEmemArbTimingW2R; - - uint32_t McEmemArbTimingRFCPB; - - /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ - uint32_t McEmemArbDaTurns; - /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ - uint32_t McEmemArbDaCovers; - /* Specifies the value for MC_EMEM_ARB_MISC0 */ - uint32_t McEmemArbMisc0; - /* Specifies the value for MC_EMEM_ARB_MISC1 */ - uint32_t McEmemArbMisc1; - uint32_t McEmemArbMisc2; - - /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ - uint32_t McEmemArbRing1Throttle; - /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ - uint32_t McEmemArbOverride; - /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ - uint32_t McEmemArbOverride1; - /* Specifies the value for MC_EMEM_ARB_RSV */ - uint32_t McEmemArbRsv; - - uint32_t McDaCfg0; - uint32_t McEmemArbTimingCcdmw; - - /* Specifies the value for MC_CLKEN_OVERRIDE */ - uint32_t McClkenOverride; - - /* Specifies the value for MC_STAT_CONTROL */ - uint32_t McStatControl; - - /* Specifies the value for MC_VIDEO_PROTECT_BOM */ - uint32_t McVideoProtectBom; - /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ - uint32_t McVideoProtectBomAdrHi; - /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ - uint32_t McVideoProtectSizeMb; - /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ - uint32_t McVideoProtectVprOverride; - /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ - uint32_t McVideoProtectVprOverride1; - /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ - uint32_t McVideoProtectGpuOverride0; - /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ - uint32_t McVideoProtectGpuOverride1; - /* Specifies the value for MC_SEC_CARVEOUT_BOM */ - uint32_t McSecCarveoutBom; - /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ - uint32_t McSecCarveoutAdrHi; - /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ - uint32_t McSecCarveoutSizeMb; - /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL. - VIDEO_PROTECT_WRITEAccess */ - uint32_t McVideoProtectWriteAccess; - /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL. - SEC_CARVEOUT_WRITEAccess */ - uint32_t McSecCarveoutProtectWriteAccess; - - /* Write-Protect Regions (WPR) */ - uint32_t McGeneralizedCarveout1Bom; - uint32_t McGeneralizedCarveout1BomHi; - uint32_t McGeneralizedCarveout1Size128kb; - uint32_t McGeneralizedCarveout1Access0; - uint32_t McGeneralizedCarveout1Access1; - uint32_t McGeneralizedCarveout1Access2; - uint32_t McGeneralizedCarveout1Access3; - uint32_t McGeneralizedCarveout1Access4; - uint32_t McGeneralizedCarveout1ForceInternalAccess0; - uint32_t McGeneralizedCarveout1ForceInternalAccess1; - uint32_t McGeneralizedCarveout1ForceInternalAccess2; - uint32_t McGeneralizedCarveout1ForceInternalAccess3; - uint32_t McGeneralizedCarveout1ForceInternalAccess4; - uint32_t McGeneralizedCarveout1Cfg0; - - uint32_t McGeneralizedCarveout2Bom; - uint32_t McGeneralizedCarveout2BomHi; - uint32_t McGeneralizedCarveout2Size128kb; - uint32_t McGeneralizedCarveout2Access0; - uint32_t McGeneralizedCarveout2Access1; - uint32_t McGeneralizedCarveout2Access2; - uint32_t McGeneralizedCarveout2Access3; - uint32_t McGeneralizedCarveout2Access4; - uint32_t McGeneralizedCarveout2ForceInternalAccess0; - uint32_t McGeneralizedCarveout2ForceInternalAccess1; - uint32_t McGeneralizedCarveout2ForceInternalAccess2; - uint32_t McGeneralizedCarveout2ForceInternalAccess3; - uint32_t McGeneralizedCarveout2ForceInternalAccess4; - uint32_t McGeneralizedCarveout2Cfg0; - - uint32_t McGeneralizedCarveout3Bom; - uint32_t McGeneralizedCarveout3BomHi; - uint32_t McGeneralizedCarveout3Size128kb; - uint32_t McGeneralizedCarveout3Access0; - uint32_t McGeneralizedCarveout3Access1; - uint32_t McGeneralizedCarveout3Access2; - uint32_t McGeneralizedCarveout3Access3; - uint32_t McGeneralizedCarveout3Access4; - uint32_t McGeneralizedCarveout3ForceInternalAccess0; - uint32_t McGeneralizedCarveout3ForceInternalAccess1; - uint32_t McGeneralizedCarveout3ForceInternalAccess2; - uint32_t McGeneralizedCarveout3ForceInternalAccess3; - uint32_t McGeneralizedCarveout3ForceInternalAccess4; - uint32_t McGeneralizedCarveout3Cfg0; - - uint32_t McGeneralizedCarveout4Bom; - uint32_t McGeneralizedCarveout4BomHi; - uint32_t McGeneralizedCarveout4Size128kb; - uint32_t McGeneralizedCarveout4Access0; - uint32_t McGeneralizedCarveout4Access1; - uint32_t McGeneralizedCarveout4Access2; - uint32_t McGeneralizedCarveout4Access3; - uint32_t McGeneralizedCarveout4Access4; - uint32_t McGeneralizedCarveout4ForceInternalAccess0; - uint32_t McGeneralizedCarveout4ForceInternalAccess1; - uint32_t McGeneralizedCarveout4ForceInternalAccess2; - uint32_t McGeneralizedCarveout4ForceInternalAccess3; - uint32_t McGeneralizedCarveout4ForceInternalAccess4; - uint32_t McGeneralizedCarveout4Cfg0; - - uint32_t McGeneralizedCarveout5Bom; - uint32_t McGeneralizedCarveout5BomHi; - uint32_t McGeneralizedCarveout5Size128kb; - uint32_t McGeneralizedCarveout5Access0; - uint32_t McGeneralizedCarveout5Access1; - uint32_t McGeneralizedCarveout5Access2; - uint32_t McGeneralizedCarveout5Access3; - uint32_t McGeneralizedCarveout5Access4; - uint32_t McGeneralizedCarveout5ForceInternalAccess0; - uint32_t McGeneralizedCarveout5ForceInternalAccess1; - uint32_t McGeneralizedCarveout5ForceInternalAccess2; - uint32_t McGeneralizedCarveout5ForceInternalAccess3; - uint32_t McGeneralizedCarveout5ForceInternalAccess4; - uint32_t McGeneralizedCarveout5Cfg0; - - /* Specifies enable for CA training */ - uint32_t EmcCaTrainingEnable; - - /* Set if bit 6 select is greater than bit 7 select; uses aremc. - spec packet SWIZZLE_BIT6_GT_BIT7 */ - uint32_t SwizzleRankByteEncode; - /* Specifies enable and offset for patched boot ROM write */ - uint32_t BootRomPatchControl; - /* Specifies data for patched boot ROM write */ - uint32_t BootRomPatchData; - - /* Specifies the value for MC_MTS_CARVEOUT_BOM */ - uint32_t McMtsCarveoutBom; - /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ - uint32_t McMtsCarveoutAdrHi; - /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ - uint32_t McMtsCarveoutSizeMb; - /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ - uint32_t McMtsCarveoutRegCtrl; - - /* End */ -}; - -#endif /* __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ */ diff --git a/sept/sept-secondary/src/sdram_params.h b/sept/sept-secondary/src/sdram_params.h new file mode 100644 index 000000000..72e34d4bd --- /dev/null +++ b/sept/sept-secondary/src/sdram_params.h @@ -0,0 +1,1041 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2020 Atmosphère-NX + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef FUSEE_SDRAM_PARAMS_H_ +#define FUSEE_SDRAM_PARAMS_H_ + +#include + +typedef enum { + NvBootMemoryType_None = 0, + NvBootMemoryType_Ddr = 0, + NvBootMemoryType_LpDdr = 0, + NvBootMemoryType_Ddr2 = 0, + NvBootMemoryType_LpDdr2, + NvBootMemoryType_Ddr3, + NvBootMemoryType_LpDdr4, + NvBootMemoryType_Num, + NvBootMemoryType_Unused = 0X7FFFFFF, +} NvBootMemoryType; + +typedef struct { + NvBootMemoryType MemoryType; + uint32_t PllMInputDivider; + uint32_t PllMFeedbackDivider; + uint32_t PllMStableTime; + uint32_t PllMSetupControl; + uint32_t PllMPostDivider; + uint32_t PllMKCP; + uint32_t PllMKVCO; + uint32_t EmcBctSpare0; + uint32_t EmcBctSpare1; + uint32_t EmcBctSpare2; + uint32_t EmcBctSpare3; + uint32_t EmcBctSpare4; + uint32_t EmcBctSpare5; + uint32_t EmcBctSpare6; + uint32_t EmcBctSpare7; + uint32_t EmcBctSpare8; + uint32_t EmcBctSpare9; + uint32_t EmcBctSpare10; + uint32_t EmcBctSpare11; + uint32_t EmcBctSpare12; + uint32_t EmcBctSpare13; + uint32_t EmcClockSource; + uint32_t EmcClockSourceDll; + uint32_t ClkRstControllerPllmMisc2Override; + uint32_t ClkRstControllerPllmMisc2OverrideEnable; + uint32_t ClearClk2Mc1; + uint32_t EmcAutoCalInterval; + uint32_t EmcAutoCalConfig; + uint32_t EmcAutoCalConfig2; + uint32_t EmcAutoCalConfig3; + uint32_t EmcAutoCalConfig4; + uint32_t EmcAutoCalConfig5; + uint32_t EmcAutoCalConfig6; + uint32_t EmcAutoCalConfig7; + uint32_t EmcAutoCalConfig8; + uint32_t EmcAutoCalVrefSel0; + uint32_t EmcAutoCalVrefSel1; + uint32_t EmcAutoCalChannel; + uint32_t EmcPmacroAutocalCfg0; + uint32_t EmcPmacroAutocalCfg1; + uint32_t EmcPmacroAutocalCfg2; + uint32_t EmcPmacroRxTerm; + uint32_t EmcPmacroDqTxDrv; + uint32_t EmcPmacroCaTxDrv; + uint32_t EmcPmacroCmdTxDrv; + uint32_t EmcPmacroAutocalCfgCommon; + uint32_t EmcPmacroZctrl; + uint32_t EmcAutoCalWait; + uint32_t EmcXm2CompPadCtrl; + uint32_t EmcXm2CompPadCtrl2; + uint32_t EmcXm2CompPadCtrl3; + uint32_t EmcAdrCfg; + uint32_t EmcPinProgramWait; + uint32_t EmcPinExtraWait; + uint32_t EmcPinGpioEn; + uint32_t EmcPinGpio; + uint32_t EmcTimingControlWait; + uint32_t EmcRc; + uint32_t EmcRfc; + uint32_t EmcRfcPb; + uint32_t EmcRefctrl2; + uint32_t EmcRfcSlr; + uint32_t EmcRas; + uint32_t EmcRp; + uint32_t EmcR2r; + uint32_t EmcW2w; + uint32_t EmcR2w; + uint32_t EmcW2r; + uint32_t EmcR2p; + uint32_t EmcW2p; + uint32_t EmcTppd; + uint32_t EmcCcdmw; + uint32_t EmcRdRcd; + uint32_t EmcWrRcd; + uint32_t EmcRrd; + uint32_t EmcRext; + uint32_t EmcWext; + uint32_t EmcWdv; + uint32_t EmcWdvChk; + uint32_t EmcWsv; + uint32_t EmcWev; + uint32_t EmcWdvMask; + uint32_t EmcWsDuration; + uint32_t EmcWeDuration; + uint32_t EmcQUse; + uint32_t EmcQuseWidth; + uint32_t EmcIbdly; + uint32_t EmcObdly; + uint32_t EmcEInput; + uint32_t EmcEInputDuration; + uint32_t EmcPutermExtra; + uint32_t EmcPutermWidth; + uint32_t EmcQRst; + uint32_t EmcQSafe; + uint32_t EmcRdv; + uint32_t EmcRdvMask; + uint32_t EmcRdvEarly; + uint32_t EmcRdvEarlyMask; + uint32_t EmcQpop; + uint32_t EmcRefresh; + uint32_t EmcBurstRefreshNum; + uint32_t EmcPreRefreshReqCnt; + uint32_t EmcPdEx2Wr; + uint32_t EmcPdEx2Rd; + uint32_t EmcPChg2Pden; + uint32_t EmcAct2Pden; + uint32_t EmcAr2Pden; + uint32_t EmcRw2Pden; + uint32_t EmcCke2Pden; + uint32_t EmcPdex2Cke; + uint32_t EmcPdex2Mrr; + uint32_t EmcTxsr; + uint32_t EmcTxsrDll; + uint32_t EmcTcke; + uint32_t EmcTckesr; + uint32_t EmcTpd; + uint32_t EmcTfaw; + uint32_t EmcTrpab; + uint32_t EmcTClkStable; + uint32_t EmcTClkStop; + uint32_t EmcTRefBw; + uint32_t EmcFbioCfg5; + uint32_t EmcFbioCfg7; + uint32_t EmcFbioCfg8; + uint32_t EmcCmdMappingCmd0_0; + uint32_t EmcCmdMappingCmd0_1; + uint32_t EmcCmdMappingCmd0_2; + uint32_t EmcCmdMappingCmd1_0; + uint32_t EmcCmdMappingCmd1_1; + uint32_t EmcCmdMappingCmd1_2; + uint32_t EmcCmdMappingCmd2_0; + uint32_t EmcCmdMappingCmd2_1; + uint32_t EmcCmdMappingCmd2_2; + uint32_t EmcCmdMappingCmd3_0; + uint32_t EmcCmdMappingCmd3_1; + uint32_t EmcCmdMappingCmd3_2; + uint32_t EmcCmdMappingByte; + uint32_t EmcFbioSpare; + uint32_t EmcCfgRsv; + uint32_t EmcMrs; + uint32_t EmcEmrs; + uint32_t EmcEmrs2; + uint32_t EmcEmrs3; + uint32_t EmcMrw1; + uint32_t EmcMrw2; + uint32_t EmcMrw3; + uint32_t EmcMrw4; + uint32_t EmcMrw6; + uint32_t EmcMrw8; + uint32_t EmcMrw9; + uint32_t EmcMrw10; + uint32_t EmcMrw12; + uint32_t EmcMrw13; + uint32_t EmcMrw14; + uint32_t EmcMrwExtra; + uint32_t EmcWarmBootMrwExtra; + uint32_t EmcWarmBootExtraModeRegWriteEnable; + uint32_t EmcExtraModeRegWriteEnable; + uint32_t EmcMrwResetCommand; + uint32_t EmcMrwResetNInitWait; + uint32_t EmcMrsWaitCnt; + uint32_t EmcMrsWaitCnt2; + uint32_t EmcCfg; + uint32_t EmcCfg2; + uint32_t EmcCfgPipe; + uint32_t EmcCfgPipeClk; + uint32_t EmcFdpdCtrlCmdNoRamp; + uint32_t EmcCfgUpdate; + uint32_t EmcDbg; + uint32_t EmcDbgWriteMux; + uint32_t EmcCmdQ; + uint32_t EmcMc2EmcQ; + uint32_t EmcDynSelfRefControl; + uint32_t AhbArbitrationXbarCtrlMemInitDone; + uint32_t EmcCfgDigDll; + uint32_t EmcCfgDigDll_1; + uint32_t EmcCfgDigDllPeriod; + uint32_t EmcDevSelect; + uint32_t EmcSelDpdCtrl; + uint32_t EmcFdpdCtrlDq; + uint32_t EmcFdpdCtrlCmd; + uint32_t EmcPmacroIbVrefDq_0; + uint32_t EmcPmacroIbVrefDq_1; + uint32_t EmcPmacroIbVrefDqs_0; + uint32_t EmcPmacroIbVrefDqs_1; + uint32_t EmcPmacroIbRxrt; + uint32_t EmcCfgPipe1; + uint32_t EmcCfgPipe2; + uint32_t EmcPmacroQuseDdllRank0_0; + uint32_t EmcPmacroQuseDdllRank0_1; + uint32_t EmcPmacroQuseDdllRank0_2; + uint32_t EmcPmacroQuseDdllRank0_3; + uint32_t EmcPmacroQuseDdllRank0_4; + uint32_t EmcPmacroQuseDdllRank0_5; + uint32_t EmcPmacroQuseDdllRank1_0; + uint32_t EmcPmacroQuseDdllRank1_1; + uint32_t EmcPmacroQuseDdllRank1_2; + uint32_t EmcPmacroQuseDdllRank1_3; + uint32_t EmcPmacroQuseDdllRank1_4; + uint32_t EmcPmacroQuseDdllRank1_5; + uint32_t EmcPmacroObDdllLongDqRank0_0; + uint32_t EmcPmacroObDdllLongDqRank0_1; + uint32_t EmcPmacroObDdllLongDqRank0_2; + uint32_t EmcPmacroObDdllLongDqRank0_3; + uint32_t EmcPmacroObDdllLongDqRank0_4; + uint32_t EmcPmacroObDdllLongDqRank0_5; + uint32_t EmcPmacroObDdllLongDqRank1_0; + uint32_t EmcPmacroObDdllLongDqRank1_1; + uint32_t EmcPmacroObDdllLongDqRank1_2; + uint32_t EmcPmacroObDdllLongDqRank1_3; + uint32_t EmcPmacroObDdllLongDqRank1_4; + uint32_t EmcPmacroObDdllLongDqRank1_5; + uint32_t EmcPmacroObDdllLongDqsRank0_0; + uint32_t EmcPmacroObDdllLongDqsRank0_1; + uint32_t EmcPmacroObDdllLongDqsRank0_2; + uint32_t EmcPmacroObDdllLongDqsRank0_3; + uint32_t EmcPmacroObDdllLongDqsRank0_4; + uint32_t EmcPmacroObDdllLongDqsRank0_5; + uint32_t EmcPmacroObDdllLongDqsRank1_0; + uint32_t EmcPmacroObDdllLongDqsRank1_1; + uint32_t EmcPmacroObDdllLongDqsRank1_2; + uint32_t EmcPmacroObDdllLongDqsRank1_3; + uint32_t EmcPmacroObDdllLongDqsRank1_4; + uint32_t EmcPmacroObDdllLongDqsRank1_5; + uint32_t EmcPmacroIbDdllLongDqsRank0_0; + uint32_t EmcPmacroIbDdllLongDqsRank0_1; + uint32_t EmcPmacroIbDdllLongDqsRank0_2; + uint32_t EmcPmacroIbDdllLongDqsRank0_3; + uint32_t EmcPmacroIbDdllLongDqsRank1_0; + uint32_t EmcPmacroIbDdllLongDqsRank1_1; + uint32_t EmcPmacroIbDdllLongDqsRank1_2; + uint32_t EmcPmacroIbDdllLongDqsRank1_3; + uint32_t EmcPmacroDdllLongCmd_0; + uint32_t EmcPmacroDdllLongCmd_1; + uint32_t EmcPmacroDdllLongCmd_2; + uint32_t EmcPmacroDdllLongCmd_3; + uint32_t EmcPmacroDdllLongCmd_4; + uint32_t EmcPmacroDdllShortCmd_0; + uint32_t EmcPmacroDdllShortCmd_1; + uint32_t EmcPmacroDdllShortCmd_2; + uint32_t WarmBootWait; + uint32_t EmcOdtWrite; + uint32_t EmcZcalInterval; + uint32_t EmcZcalWaitCnt; + uint32_t EmcZcalMrwCmd; + uint32_t EmcMrsResetDll; + uint32_t EmcZcalInitDev0; + uint32_t EmcZcalInitDev1; + uint32_t EmcZcalInitWait; + uint32_t EmcZcalWarmColdBootEnables; + uint32_t EmcMrwLpddr2ZcalWarmBoot; + uint32_t EmcZqCalDdr3WarmBoot; + uint32_t EmcZqCalLpDdr4WarmBoot; + uint32_t EmcZcalWarmBootWait; + uint32_t EmcMrsWarmBootEnable; + uint32_t EmcMrsResetDllWait; + uint32_t EmcMrsExtra; + uint32_t EmcWarmBootMrsExtra; + uint32_t EmcEmrsDdr2DllEnable; + uint32_t EmcMrsDdr2DllReset; + uint32_t EmcEmrsDdr2OcdCalib; + uint32_t EmcDdr2Wait; + uint32_t EmcClkenOverride; + uint32_t EmcExtraRefreshNum; + uint32_t EmcClkenOverrideAllWarmBoot; + uint32_t McClkenOverrideAllWarmBoot; + uint32_t EmcCfgDigDllPeriodWarmBoot; + uint32_t PmcVddpSel; + uint32_t PmcVddpSelWait; + uint32_t PmcDdrPwr; + uint32_t PmcDdrCfg; + uint32_t PmcIoDpd3Req; + uint32_t PmcIoDpd3ReqWait; + uint32_t PmcIoDpd4ReqWait; + uint32_t PmcRegShort; + uint32_t PmcNoIoPower; + uint32_t PmcDdrCntrlWait; + uint32_t PmcDdrCntrl; + uint32_t EmcAcpdControl; + uint32_t EmcSwizzleRank0Byte0; + uint32_t EmcSwizzleRank0Byte1; + uint32_t EmcSwizzleRank0Byte2; + uint32_t EmcSwizzleRank0Byte3; + uint32_t EmcSwizzleRank1Byte0; + uint32_t EmcSwizzleRank1Byte1; + uint32_t EmcSwizzleRank1Byte2; + uint32_t EmcSwizzleRank1Byte3; + uint32_t EmcTxdsrvttgen; + uint32_t EmcDataBrlshft0; + uint32_t EmcDataBrlshft1; + uint32_t EmcDqsBrlshft0; + uint32_t EmcDqsBrlshft1; + uint32_t EmcCmdBrlshft0; + uint32_t EmcCmdBrlshft1; + uint32_t EmcCmdBrlshft2; + uint32_t EmcCmdBrlshft3; + uint32_t EmcQuseBrlshft0; + uint32_t EmcQuseBrlshft1; + uint32_t EmcQuseBrlshft2; + uint32_t EmcQuseBrlshft3; + uint32_t EmcDllCfg0; + uint32_t EmcDllCfg1; + uint32_t EmcPmcScratch1; + uint32_t EmcPmcScratch2; + uint32_t EmcPmcScratch3; + uint32_t EmcPmacroPadCfgCtrl; + uint32_t EmcPmacroVttgenCtrl0; + uint32_t EmcPmacroVttgenCtrl1; + uint32_t EmcPmacroVttgenCtrl2; + uint32_t EmcPmacroBrickCtrlRfu1; + uint32_t EmcPmacroCmdBrickCtrlFdpd; + uint32_t EmcPmacroBrickCtrlRfu2; + uint32_t EmcPmacroDataBrickCtrlFdpd; + uint32_t EmcPmacroBgBiasCtrl0; + uint32_t EmcPmacroDataPadRxCtrl; + uint32_t EmcPmacroCmdPadRxCtrl; + uint32_t EmcPmacroDataRxTermMode; + uint32_t EmcPmacroCmdRxTermMode; + uint32_t EmcPmacroDataPadTxCtrl; + uint32_t EmcPmacroCommonPadTxCtrl; + uint32_t EmcPmacroCmdPadTxCtrl; + uint32_t EmcCfg3; + uint32_t EmcPmacroTxPwrd0; + uint32_t EmcPmacroTxPwrd1; + uint32_t EmcPmacroTxPwrd2; + uint32_t EmcPmacroTxPwrd3; + uint32_t EmcPmacroTxPwrd4; + uint32_t EmcPmacroTxPwrd5; + uint32_t EmcConfigSampleDelay; + uint32_t EmcPmacroBrickMapping0; + uint32_t EmcPmacroBrickMapping1; + uint32_t EmcPmacroBrickMapping2; + uint32_t EmcPmacroTxSelClkSrc0; + uint32_t EmcPmacroTxSelClkSrc1; + uint32_t EmcPmacroTxSelClkSrc2; + uint32_t EmcPmacroTxSelClkSrc3; + uint32_t EmcPmacroTxSelClkSrc4; + uint32_t EmcPmacroTxSelClkSrc5; + uint32_t EmcPmacroDdllBypass; + uint32_t EmcPmacroDdllPwrd0; + uint32_t EmcPmacroDdllPwrd1; + uint32_t EmcPmacroDdllPwrd2; + uint32_t EmcPmacroCmdCtrl0; + uint32_t EmcPmacroCmdCtrl1; + uint32_t EmcPmacroCmdCtrl2; + uint32_t McEmemAdrCfg; + uint32_t McEmemAdrCfgDev0; + uint32_t McEmemAdrCfgDev1; + uint32_t McEmemAdrCfgChannelMask; + uint32_t McEmemAdrCfgBankMask0; + uint32_t McEmemAdrCfgBankMask1; + uint32_t McEmemAdrCfgBankMask2; + uint32_t McEmemCfg; + uint32_t McEmemArbCfg; + uint32_t McEmemArbOutstandingReq; + uint32_t McEmemArbRefpbHpCtrl; + uint32_t McEmemArbRefpbBankCtrl; + uint32_t McEmemArbTimingRcd; + uint32_t McEmemArbTimingRp; + uint32_t McEmemArbTimingRc; + uint32_t McEmemArbTimingRas; + uint32_t McEmemArbTimingFaw; + uint32_t McEmemArbTimingRrd; + uint32_t McEmemArbTimingRap2Pre; + uint32_t McEmemArbTimingWap2Pre; + uint32_t McEmemArbTimingR2R; + uint32_t McEmemArbTimingW2W; + uint32_t McEmemArbTimingR2W; + uint32_t McEmemArbTimingW2R; + uint32_t McEmemArbTimingRFCPB; + uint32_t McEmemArbDaTurns; + uint32_t McEmemArbDaCovers; + uint32_t McEmemArbMisc0; + uint32_t McEmemArbMisc1; + uint32_t McEmemArbMisc2; + uint32_t McEmemArbRing1Throttle; + uint32_t McEmemArbOverride; + uint32_t McEmemArbOverride1; + uint32_t McEmemArbRsv; + uint32_t McDaCfg0; + uint32_t McEmemArbTimingCcdmw; + uint32_t McClkenOverride; + uint32_t McStatControl; + uint32_t McVideoProtectBom; + uint32_t McVideoProtectBomAdrHi; + uint32_t McVideoProtectSizeMb; + uint32_t McVideoProtectVprOverride; + uint32_t McVideoProtectVprOverride1; + uint32_t McVideoProtectGpuOverride0; + uint32_t McVideoProtectGpuOverride1; + uint32_t McSecCarveoutBom; + uint32_t McSecCarveoutAdrHi; + uint32_t McSecCarveoutSizeMb; + uint32_t McVideoProtectWriteAccess; + uint32_t McSecCarveoutProtectWriteAccess; + uint32_t McGeneralizedCarveout1Bom; + uint32_t McGeneralizedCarveout1BomHi; + uint32_t McGeneralizedCarveout1Size128kb; + uint32_t McGeneralizedCarveout1Access0; + uint32_t McGeneralizedCarveout1Access1; + uint32_t McGeneralizedCarveout1Access2; + uint32_t McGeneralizedCarveout1Access3; + uint32_t McGeneralizedCarveout1Access4; + uint32_t McGeneralizedCarveout1ForceInternalAccess0; + uint32_t McGeneralizedCarveout1ForceInternalAccess1; + uint32_t McGeneralizedCarveout1ForceInternalAccess2; + uint32_t McGeneralizedCarveout1ForceInternalAccess3; + uint32_t McGeneralizedCarveout1ForceInternalAccess4; + uint32_t McGeneralizedCarveout1Cfg0; + uint32_t McGeneralizedCarveout2Bom; + uint32_t McGeneralizedCarveout2BomHi; + uint32_t McGeneralizedCarveout2Size128kb; + uint32_t McGeneralizedCarveout2Access0; + uint32_t McGeneralizedCarveout2Access1; + uint32_t McGeneralizedCarveout2Access2; + uint32_t McGeneralizedCarveout2Access3; + uint32_t McGeneralizedCarveout2Access4; + uint32_t McGeneralizedCarveout2ForceInternalAccess0; + uint32_t McGeneralizedCarveout2ForceInternalAccess1; + uint32_t McGeneralizedCarveout2ForceInternalAccess2; + uint32_t McGeneralizedCarveout2ForceInternalAccess3; + uint32_t McGeneralizedCarveout2ForceInternalAccess4; + uint32_t McGeneralizedCarveout2Cfg0; + uint32_t McGeneralizedCarveout3Bom; + uint32_t McGeneralizedCarveout3BomHi; + uint32_t McGeneralizedCarveout3Size128kb; + uint32_t McGeneralizedCarveout3Access0; + uint32_t McGeneralizedCarveout3Access1; + uint32_t McGeneralizedCarveout3Access2; + uint32_t McGeneralizedCarveout3Access3; + uint32_t McGeneralizedCarveout3Access4; + uint32_t McGeneralizedCarveout3ForceInternalAccess0; + uint32_t McGeneralizedCarveout3ForceInternalAccess1; + uint32_t McGeneralizedCarveout3ForceInternalAccess2; + uint32_t McGeneralizedCarveout3ForceInternalAccess3; + uint32_t McGeneralizedCarveout3ForceInternalAccess4; + uint32_t McGeneralizedCarveout3Cfg0; + uint32_t McGeneralizedCarveout4Bom; + uint32_t McGeneralizedCarveout4BomHi; + uint32_t McGeneralizedCarveout4Size128kb; + uint32_t McGeneralizedCarveout4Access0; + uint32_t McGeneralizedCarveout4Access1; + uint32_t McGeneralizedCarveout4Access2; + uint32_t McGeneralizedCarveout4Access3; + uint32_t McGeneralizedCarveout4Access4; + uint32_t McGeneralizedCarveout4ForceInternalAccess0; + uint32_t McGeneralizedCarveout4ForceInternalAccess1; + uint32_t McGeneralizedCarveout4ForceInternalAccess2; + uint32_t McGeneralizedCarveout4ForceInternalAccess3; + uint32_t McGeneralizedCarveout4ForceInternalAccess4; + uint32_t McGeneralizedCarveout4Cfg0; + uint32_t McGeneralizedCarveout5Bom; + uint32_t McGeneralizedCarveout5BomHi; + uint32_t McGeneralizedCarveout5Size128kb; + uint32_t McGeneralizedCarveout5Access0; + uint32_t McGeneralizedCarveout5Access1; + uint32_t McGeneralizedCarveout5Access2; + uint32_t McGeneralizedCarveout5Access3; + uint32_t McGeneralizedCarveout5Access4; + uint32_t McGeneralizedCarveout5ForceInternalAccess0; + uint32_t McGeneralizedCarveout5ForceInternalAccess1; + uint32_t McGeneralizedCarveout5ForceInternalAccess2; + uint32_t McGeneralizedCarveout5ForceInternalAccess3; + uint32_t McGeneralizedCarveout5ForceInternalAccess4; + uint32_t McGeneralizedCarveout5Cfg0; + uint32_t EmcCaTrainingEnable; + uint32_t SwizzleRankByteEncode; + uint32_t BootRomPatchControl; + uint32_t BootRomPatchData; + uint32_t McMtsCarveoutBom; + uint32_t McMtsCarveoutAdrHi; + uint32_t McMtsCarveoutSizeMb; + uint32_t McMtsCarveoutRegCtrl; +} sdram_params_erista_t; + +typedef struct { + NvBootMemoryType MemoryType; + uint32_t PllMInputDivider; + uint32_t PllMFeedbackDivider; + uint32_t PllMStableTime; + uint32_t PllMSetupControl; + uint32_t PllMPostDivider; + uint32_t PllMKCP; + uint32_t PllMKVCO; + uint32_t EmcBctSpare0; + uint32_t EmcBctSpare1; + uint32_t EmcBctSpare2; + uint32_t EmcBctSpare3; + uint32_t EmcBctSpare4; + uint32_t EmcBctSpare5; + uint32_t EmcBctSpare6; + uint32_t EmcBctSpare7; + uint32_t EmcBctSpare8; + uint32_t EmcBctSpare9; + uint32_t EmcBctSpare10; + uint32_t EmcBctSpare11; + uint32_t EmcBctSpare12; + uint32_t EmcBctSpare13; + uint32_t EmcBctSpareSecure0; + uint32_t EmcBctSpareSecure1; + uint32_t EmcBctSpareSecure2; + uint32_t EmcBctSpareSecure3; + uint32_t EmcBctSpareSecure4; + uint32_t EmcBctSpareSecure5; + uint32_t EmcBctSpareSecure6; + uint32_t EmcBctSpareSecure7; + uint32_t EmcBctSpareSecure8; + uint32_t EmcBctSpareSecure9; + uint32_t EmcBctSpareSecure10; + uint32_t EmcBctSpareSecure11; + uint32_t EmcBctSpareSecure12; + uint32_t EmcBctSpareSecure13; + uint32_t EmcBctSpareSecure14; + uint32_t EmcBctSpareSecure15; + uint32_t EmcBctSpareSecure16; + uint32_t EmcBctSpareSecure17; + uint32_t EmcBctSpareSecure18; + uint32_t EmcBctSpareSecure19; + uint32_t EmcBctSpareSecure20; + uint32_t EmcBctSpareSecure21; + uint32_t EmcBctSpareSecure22; + uint32_t EmcBctSpareSecure23; + uint32_t EmcClockSource; + uint32_t EmcClockSourceDll; + uint32_t ClkRstControllerPllmMisc2Override; + uint32_t ClkRstControllerPllmMisc2OverrideEnable; + uint32_t ClearClk2Mc1; + uint32_t EmcAutoCalInterval; + uint32_t EmcAutoCalConfig; + uint32_t EmcAutoCalConfig2; + uint32_t EmcAutoCalConfig3; + uint32_t EmcAutoCalConfig4; + uint32_t EmcAutoCalConfig5; + uint32_t EmcAutoCalConfig6; + uint32_t EmcAutoCalConfig7; + uint32_t EmcAutoCalConfig8; + uint32_t EmcAutoCalConfig9; + uint32_t EmcAutoCalVrefSel0; + uint32_t EmcAutoCalVrefSel1; + uint32_t EmcAutoCalChannel; + uint32_t EmcPmacroAutocalCfg0; + uint32_t EmcPmacroAutocalCfg1; + uint32_t EmcPmacroAutocalCfg2; + uint32_t EmcPmacroRxTerm; + uint32_t EmcPmacroDqTxDrv; + uint32_t EmcPmacroCaTxDrv; + uint32_t EmcPmacroCmdTxDrv; + uint32_t EmcPmacroAutocalCfgCommon; + uint32_t EmcPmacroZctrl; + uint32_t EmcAutoCalWait; + uint32_t EmcXm2CompPadCtrl; + uint32_t EmcXm2CompPadCtrl2; + uint32_t EmcXm2CompPadCtrl3; + uint32_t EmcAdrCfg; + uint32_t EmcPinProgramWait; + uint32_t EmcPinExtraWait; + uint32_t EmcPinGpioEn; + uint32_t EmcPinGpio; + uint32_t EmcTimingControlWait; + uint32_t EmcRc; + uint32_t EmcRfc; + uint32_t EmcRfcPb; + uint32_t EmcRefctrl2; + uint32_t EmcRfcSlr; + uint32_t EmcRas; + uint32_t EmcRp; + uint32_t EmcR2r; + uint32_t EmcW2w; + uint32_t EmcR2w; + uint32_t EmcW2r; + uint32_t EmcR2p; + uint32_t EmcW2p; + uint32_t EmcTppd; + uint32_t EmcTrtm; + uint32_t EmcTwtm; + uint32_t EmcTratm; + uint32_t EmcTwatm; + uint32_t EmcTr2ref; + uint32_t EmcCcdmw; + uint32_t EmcRdRcd; + uint32_t EmcWrRcd; + uint32_t EmcRrd; + uint32_t EmcRext; + uint32_t EmcWext; + uint32_t EmcWdv; + uint32_t EmcWdvChk; + uint32_t EmcWsv; + uint32_t EmcWev; + uint32_t EmcWdvMask; + uint32_t EmcWsDuration; + uint32_t EmcWeDuration; + uint32_t EmcQUse; + uint32_t EmcQuseWidth; + uint32_t EmcIbdly; + uint32_t EmcObdly; + uint32_t EmcEInput; + uint32_t EmcEInputDuration; + uint32_t EmcPutermExtra; + uint32_t EmcPutermWidth; + uint32_t EmcQRst; + uint32_t EmcQSafe; + uint32_t EmcRdv; + uint32_t EmcRdvMask; + uint32_t EmcRdvEarly; + uint32_t EmcRdvEarlyMask; + uint32_t EmcQpop; + uint32_t EmcRefresh; + uint32_t EmcBurstRefreshNum; + uint32_t EmcPreRefreshReqCnt; + uint32_t EmcPdEx2Wr; + uint32_t EmcPdEx2Rd; + uint32_t EmcPChg2Pden; + uint32_t EmcAct2Pden; + uint32_t EmcAr2Pden; + uint32_t EmcRw2Pden; + uint32_t EmcCke2Pden; + uint32_t EmcPdex2Cke; + uint32_t EmcPdex2Mrr; + uint32_t EmcTxsr; + uint32_t EmcTxsrDll; + uint32_t EmcTcke; + uint32_t EmcTckesr; + uint32_t EmcTpd; + uint32_t EmcTfaw; + uint32_t EmcTrpab; + uint32_t EmcTClkStable; + uint32_t EmcTClkStop; + uint32_t EmcTRefBw; + uint32_t EmcFbioCfg5; + uint32_t EmcFbioCfg7; + uint32_t EmcFbioCfg8; + uint32_t EmcCmdMappingCmd0_0; + uint32_t EmcCmdMappingCmd0_1; + uint32_t EmcCmdMappingCmd0_2; + uint32_t EmcCmdMappingCmd1_0; + uint32_t EmcCmdMappingCmd1_1; + uint32_t EmcCmdMappingCmd1_2; + uint32_t EmcCmdMappingCmd2_0; + uint32_t EmcCmdMappingCmd2_1; + uint32_t EmcCmdMappingCmd2_2; + uint32_t EmcCmdMappingCmd3_0; + uint32_t EmcCmdMappingCmd3_1; + uint32_t EmcCmdMappingCmd3_2; + uint32_t EmcCmdMappingByte; + uint32_t EmcFbioSpare; + uint32_t EmcCfgRsv; + uint32_t EmcMrs; + uint32_t EmcEmrs; + uint32_t EmcEmrs2; + uint32_t EmcEmrs3; + uint32_t EmcMrw1; + uint32_t EmcMrw2; + uint32_t EmcMrw3; + uint32_t EmcMrw4; + uint32_t EmcMrw6; + uint32_t EmcMrw8; + uint32_t EmcMrw9; + uint32_t EmcMrw10; + uint32_t EmcMrw12; + uint32_t EmcMrw13; + uint32_t EmcMrw14; + uint32_t EmcMrwExtra; + uint32_t EmcWarmBootMrwExtra; + uint32_t EmcWarmBootExtraModeRegWriteEnable; + uint32_t EmcExtraModeRegWriteEnable; + uint32_t EmcMrwResetCommand; + uint32_t EmcMrwResetNInitWait; + uint32_t EmcMrsWaitCnt; + uint32_t EmcMrsWaitCnt2; + uint32_t EmcCfg; + uint32_t EmcCfg2; + uint32_t EmcCfgPipe; + uint32_t EmcCfgPipeClk; + uint32_t EmcFdpdCtrlCmdNoRamp; + uint32_t EmcCfgUpdate; + uint32_t EmcDbg; + uint32_t EmcDbgWriteMux; + uint32_t EmcCmdQ; + uint32_t EmcMc2EmcQ; + uint32_t EmcDynSelfRefControl; + uint32_t AhbArbitrationXbarCtrlMemInitDone; + uint32_t EmcCfgDigDll; + uint32_t EmcCfgDigDll_1; + uint32_t EmcCfgDigDllPeriod; + uint32_t EmcDevSelect; + uint32_t EmcSelDpdCtrl; + uint32_t EmcFdpdCtrlDq; + uint32_t EmcFdpdCtrlCmd; + uint32_t EmcPmacroIbVrefDq_0; + uint32_t EmcPmacroIbVrefDq_1; + uint32_t EmcPmacroIbVrefDqs_0; + uint32_t EmcPmacroIbVrefDqs_1; + uint32_t EmcPmacroIbRxrt; + uint32_t EmcCfgPipe1; + uint32_t EmcCfgPipe2; + uint32_t EmcPmacroQuseDdllRank0_0; + uint32_t EmcPmacroQuseDdllRank0_1; + uint32_t EmcPmacroQuseDdllRank0_2; + uint32_t EmcPmacroQuseDdllRank0_3; + uint32_t EmcPmacroQuseDdllRank0_4; + uint32_t EmcPmacroQuseDdllRank0_5; + uint32_t EmcPmacroQuseDdllRank1_0; + uint32_t EmcPmacroQuseDdllRank1_1; + uint32_t EmcPmacroQuseDdllRank1_2; + uint32_t EmcPmacroQuseDdllRank1_3; + uint32_t EmcPmacroQuseDdllRank1_4; + uint32_t EmcPmacroQuseDdllRank1_5; + uint32_t EmcPmacroObDdllLongDqRank0_0; + uint32_t EmcPmacroObDdllLongDqRank0_1; + uint32_t EmcPmacroObDdllLongDqRank0_2; + uint32_t EmcPmacroObDdllLongDqRank0_3; + uint32_t EmcPmacroObDdllLongDqRank0_4; + uint32_t EmcPmacroObDdllLongDqRank0_5; + uint32_t EmcPmacroObDdllLongDqRank1_0; + uint32_t EmcPmacroObDdllLongDqRank1_1; + uint32_t EmcPmacroObDdllLongDqRank1_2; + uint32_t EmcPmacroObDdllLongDqRank1_3; + uint32_t EmcPmacroObDdllLongDqRank1_4; + uint32_t EmcPmacroObDdllLongDqRank1_5; + uint32_t EmcPmacroObDdllLongDqsRank0_0; + uint32_t EmcPmacroObDdllLongDqsRank0_1; + uint32_t EmcPmacroObDdllLongDqsRank0_2; + uint32_t EmcPmacroObDdllLongDqsRank0_3; + uint32_t EmcPmacroObDdllLongDqsRank0_4; + uint32_t EmcPmacroObDdllLongDqsRank0_5; + uint32_t EmcPmacroObDdllLongDqsRank1_0; + uint32_t EmcPmacroObDdllLongDqsRank1_1; + uint32_t EmcPmacroObDdllLongDqsRank1_2; + uint32_t EmcPmacroObDdllLongDqsRank1_3; + uint32_t EmcPmacroObDdllLongDqsRank1_4; + uint32_t EmcPmacroObDdllLongDqsRank1_5; + uint32_t EmcPmacroIbDdllLongDqsRank0_0; + uint32_t EmcPmacroIbDdllLongDqsRank0_1; + uint32_t EmcPmacroIbDdllLongDqsRank0_2; + uint32_t EmcPmacroIbDdllLongDqsRank0_3; + uint32_t EmcPmacroIbDdllLongDqsRank1_0; + uint32_t EmcPmacroIbDdllLongDqsRank1_1; + uint32_t EmcPmacroIbDdllLongDqsRank1_2; + uint32_t EmcPmacroIbDdllLongDqsRank1_3; + uint32_t EmcPmacroDdllLongCmd_0; + uint32_t EmcPmacroDdllLongCmd_1; + uint32_t EmcPmacroDdllLongCmd_2; + uint32_t EmcPmacroDdllLongCmd_3; + uint32_t EmcPmacroDdllLongCmd_4; + uint32_t EmcPmacroDdllShortCmd_0; + uint32_t EmcPmacroDdllShortCmd_1; + uint32_t EmcPmacroDdllShortCmd_2; + uint32_t EmcPmacroDdllPeriodicOffset; + uint32_t WarmBootWait; + uint32_t EmcOdtWrite; + uint32_t EmcZcalInterval; + uint32_t EmcZcalWaitCnt; + uint32_t EmcZcalMrwCmd; + uint32_t EmcMrsResetDll; + uint32_t EmcZcalInitDev0; + uint32_t EmcZcalInitDev1; + uint32_t EmcZcalInitWait; + uint32_t EmcZcalWarmColdBootEnables; + uint32_t EmcMrwLpddr2ZcalWarmBoot; + uint32_t EmcZqCalDdr3WarmBoot; + uint32_t EmcZqCalLpDdr4WarmBoot; + uint32_t EmcZcalWarmBootWait; + uint32_t EmcMrsWarmBootEnable; + uint32_t EmcMrsResetDllWait; + uint32_t EmcMrsExtra; + uint32_t EmcWarmBootMrsExtra; + uint32_t EmcEmrsDdr2DllEnable; + uint32_t EmcMrsDdr2DllReset; + uint32_t EmcEmrsDdr2OcdCalib; + uint32_t EmcDdr2Wait; + uint32_t EmcClkenOverride; + uint32_t EmcExtraRefreshNum; + uint32_t EmcClkenOverrideAllWarmBoot; + uint32_t McClkenOverrideAllWarmBoot; + uint32_t EmcCfgDigDllPeriodWarmBoot; + uint32_t PmcVddpSel; + uint32_t PmcVddpSelWait; + uint32_t PmcDdrCfg; + uint32_t PmcIoDpd3Req; + uint32_t PmcIoDpd3ReqWait; + uint32_t PmcIoDpd4ReqWait; + uint32_t PmcRegShort; + uint32_t PmcNoIoPower; + uint32_t PmcDdrCntrlWait; + uint32_t PmcDdrCntrl; + uint32_t EmcAcpdControl; + uint32_t EmcSwizzleRank0Byte0; + uint32_t EmcSwizzleRank0Byte1; + uint32_t EmcSwizzleRank0Byte2; + uint32_t EmcSwizzleRank0Byte3; + uint32_t EmcSwizzleRank1Byte0; + uint32_t EmcSwizzleRank1Byte1; + uint32_t EmcSwizzleRank1Byte2; + uint32_t EmcSwizzleRank1Byte3; + uint32_t EmcTxdsrvttgen; + uint32_t EmcDataBrlshft0; + uint32_t EmcDataBrlshft1; + uint32_t EmcDqsBrlshft0; + uint32_t EmcDqsBrlshft1; + uint32_t EmcCmdBrlshft0; + uint32_t EmcCmdBrlshft1; + uint32_t EmcCmdBrlshft2; + uint32_t EmcCmdBrlshft3; + uint32_t EmcQuseBrlshft0; + uint32_t EmcQuseBrlshft1; + uint32_t EmcQuseBrlshft2; + uint32_t EmcQuseBrlshft3; + uint32_t EmcPmacroDllCfg0; + uint32_t EmcPmacroDllCfg1; + uint32_t EmcPmcScratch1; + uint32_t EmcPmcScratch2; + uint32_t EmcPmcScratch3; + uint32_t EmcPmacroPadCfgCtrl; + uint32_t EmcPmacroVttgenCtrl0; + uint32_t EmcPmacroVttgenCtrl1; + uint32_t EmcPmacroVttgenCtrl2; + uint32_t EmcPmacroDsrVttgenCtrl0; + uint32_t EmcPmacroBrickCtrlRfu1; + uint32_t EmcPmacroCmdBrickCtrlFdpd; + uint32_t EmcPmacroBrickCtrlRfu2; + uint32_t EmcPmacroDataBrickCtrlFdpd; + uint32_t EmcPmacroBgBiasCtrl0; + uint32_t EmcPmacroDataPadRxCtrl; + uint32_t EmcPmacroCmdPadRxCtrl; + uint32_t EmcPmacroDataRxTermMode; + uint32_t EmcPmacroCmdRxTermMode; + uint32_t EmcPmacroDataPadTxCtrl; + uint32_t EmcPmacroCmdPadTxCtrl; + uint32_t EmcCfg3; + uint32_t EmcPmacroTxPwrd0; + uint32_t EmcPmacroTxPwrd1; + uint32_t EmcPmacroTxPwrd2; + uint32_t EmcPmacroTxPwrd3; + uint32_t EmcPmacroTxPwrd4; + uint32_t EmcPmacroTxPwrd5; + uint32_t EmcConfigSampleDelay; + uint32_t EmcPmacroBrickMapping0; + uint32_t EmcPmacroBrickMapping1; + uint32_t EmcPmacroBrickMapping2; + uint32_t EmcPmacroTxSelClkSrc0; + uint32_t EmcPmacroTxSelClkSrc1; + uint32_t EmcPmacroTxSelClkSrc2; + uint32_t EmcPmacroTxSelClkSrc3; + uint32_t EmcPmacroTxSelClkSrc4; + uint32_t EmcPmacroTxSelClkSrc5; + uint32_t EmcPmacroPerbitFgcgCtrl0; + uint32_t EmcPmacroPerbitFgcgCtrl1; + uint32_t EmcPmacroPerbitFgcgCtrl2; + uint32_t EmcPmacroPerbitFgcgCtrl3; + uint32_t EmcPmacroPerbitFgcgCtrl4; + uint32_t EmcPmacroPerbitFgcgCtrl5; + uint32_t EmcPmacroPerbitRfuCtrl0; + uint32_t EmcPmacroPerbitRfuCtrl1; + uint32_t EmcPmacroPerbitRfuCtrl2; + uint32_t EmcPmacroPerbitRfuCtrl3; + uint32_t EmcPmacroPerbitRfuCtrl4; + uint32_t EmcPmacroPerbitRfuCtrl5; + uint32_t EmcPmacroPerbitRfu1Ctrl0; + uint32_t EmcPmacroPerbitRfu1Ctrl1; + uint32_t EmcPmacroPerbitRfu1Ctrl2; + uint32_t EmcPmacroPerbitRfu1Ctrl3; + uint32_t EmcPmacroPerbitRfu1Ctrl4; + uint32_t EmcPmacroPerbitRfu1Ctrl5; + uint32_t EmcPmacroDataPiCtrl; + uint32_t EmcPmacroCmdPiCtrl; + uint32_t EmcPmacroDdllBypass; + uint32_t EmcPmacroDdllPwrd0; + uint32_t EmcPmacroDdllPwrd1; + uint32_t EmcPmacroDdllPwrd2; + uint32_t EmcPmacroCmdCtrl0; + uint32_t EmcPmacroCmdCtrl1; + uint32_t EmcPmacroCmdCtrl2; + uint32_t McEmemAdrCfg; + uint32_t McEmemAdrCfgDev0; + uint32_t McEmemAdrCfgDev1; + uint32_t McEmemAdrCfgChannelMask; + uint32_t McEmemAdrCfgBankMask0; + uint32_t McEmemAdrCfgBankMask1; + uint32_t McEmemAdrCfgBankMask2; + uint32_t McEmemCfg; + uint32_t McEmemArbCfg; + uint32_t McEmemArbOutstandingReq; + uint32_t McEmemArbRefpbHpCtrl; + uint32_t McEmemArbRefpbBankCtrl; + uint32_t McEmemArbTimingRcd; + uint32_t McEmemArbTimingRp; + uint32_t McEmemArbTimingRc; + uint32_t McEmemArbTimingRas; + uint32_t McEmemArbTimingFaw; + uint32_t McEmemArbTimingRrd; + uint32_t McEmemArbTimingRap2Pre; + uint32_t McEmemArbTimingWap2Pre; + uint32_t McEmemArbTimingR2R; + uint32_t McEmemArbTimingW2W; + uint32_t McEmemArbTimingR2W; + uint32_t McEmemArbTimingW2R; + uint32_t McEmemArbTimingRFCPB; + uint32_t McEmemArbDaTurns; + uint32_t McEmemArbDaCovers; + uint32_t McEmemArbMisc0; + uint32_t McEmemArbMisc1; + uint32_t McEmemArbMisc2; + uint32_t McEmemArbRing1Throttle; + uint32_t McEmemArbOverride; + uint32_t McEmemArbOverride1; + uint32_t McEmemArbRsv; + uint32_t McDaCfg0; + uint32_t McEmemArbTimingCcdmw; + uint32_t McClkenOverride; + uint32_t McStatControl; + uint32_t McVideoProtectBom; + uint32_t McVideoProtectBomAdrHi; + uint32_t McVideoProtectSizeMb; + uint32_t McVideoProtectVprOverride; + uint32_t McVideoProtectVprOverride1; + uint32_t McVideoProtectGpuOverride0; + uint32_t McVideoProtectGpuOverride1; + uint32_t McSecCarveoutBom; + uint32_t McSecCarveoutAdrHi; + uint32_t McSecCarveoutSizeMb; + uint32_t McVideoProtectWriteAccess; + uint32_t McSecCarveoutProtectWriteAccess; + uint32_t McGeneralizedCarveout1Bom; + uint32_t McGeneralizedCarveout1BomHi; + uint32_t McGeneralizedCarveout1Size128kb; + uint32_t McGeneralizedCarveout1Access0; + uint32_t McGeneralizedCarveout1Access1; + uint32_t McGeneralizedCarveout1Access2; + uint32_t McGeneralizedCarveout1Access3; + uint32_t McGeneralizedCarveout1Access4; + uint32_t McGeneralizedCarveout1ForceInternalAccess0; + uint32_t McGeneralizedCarveout1ForceInternalAccess1; + uint32_t McGeneralizedCarveout1ForceInternalAccess2; + uint32_t McGeneralizedCarveout1ForceInternalAccess3; + uint32_t McGeneralizedCarveout1ForceInternalAccess4; + uint32_t McGeneralizedCarveout1Cfg0; + uint32_t McGeneralizedCarveout2Bom; + uint32_t McGeneralizedCarveout2BomHi; + uint32_t McGeneralizedCarveout2Size128kb; + uint32_t McGeneralizedCarveout2Access0; + uint32_t McGeneralizedCarveout2Access1; + uint32_t McGeneralizedCarveout2Access2; + uint32_t McGeneralizedCarveout2Access3; + uint32_t McGeneralizedCarveout2Access4; + uint32_t McGeneralizedCarveout2ForceInternalAccess0; + uint32_t McGeneralizedCarveout2ForceInternalAccess1; + uint32_t McGeneralizedCarveout2ForceInternalAccess2; + uint32_t McGeneralizedCarveout2ForceInternalAccess3; + uint32_t McGeneralizedCarveout2ForceInternalAccess4; + uint32_t McGeneralizedCarveout2Cfg0; + uint32_t McGeneralizedCarveout3Bom; + uint32_t McGeneralizedCarveout3BomHi; + uint32_t McGeneralizedCarveout3Size128kb; + uint32_t McGeneralizedCarveout3Access0; + uint32_t McGeneralizedCarveout3Access1; + uint32_t McGeneralizedCarveout3Access2; + uint32_t McGeneralizedCarveout3Access3; + uint32_t McGeneralizedCarveout3Access4; + uint32_t McGeneralizedCarveout3ForceInternalAccess0; + uint32_t McGeneralizedCarveout3ForceInternalAccess1; + uint32_t McGeneralizedCarveout3ForceInternalAccess2; + uint32_t McGeneralizedCarveout3ForceInternalAccess3; + uint32_t McGeneralizedCarveout3ForceInternalAccess4; + uint32_t McGeneralizedCarveout3Cfg0; + uint32_t McGeneralizedCarveout4Bom; + uint32_t McGeneralizedCarveout4BomHi; + uint32_t McGeneralizedCarveout4Size128kb; + uint32_t McGeneralizedCarveout4Access0; + uint32_t McGeneralizedCarveout4Access1; + uint32_t McGeneralizedCarveout4Access2; + uint32_t McGeneralizedCarveout4Access3; + uint32_t McGeneralizedCarveout4Access4; + uint32_t McGeneralizedCarveout4ForceInternalAccess0; + uint32_t McGeneralizedCarveout4ForceInternalAccess1; + uint32_t McGeneralizedCarveout4ForceInternalAccess2; + uint32_t McGeneralizedCarveout4ForceInternalAccess3; + uint32_t McGeneralizedCarveout4ForceInternalAccess4; + uint32_t McGeneralizedCarveout4Cfg0; + uint32_t McGeneralizedCarveout5Bom; + uint32_t McGeneralizedCarveout5BomHi; + uint32_t McGeneralizedCarveout5Size128kb; + uint32_t McGeneralizedCarveout5Access0; + uint32_t McGeneralizedCarveout5Access1; + uint32_t McGeneralizedCarveout5Access2; + uint32_t McGeneralizedCarveout5Access3; + uint32_t McGeneralizedCarveout5Access4; + uint32_t McGeneralizedCarveout5ForceInternalAccess0; + uint32_t McGeneralizedCarveout5ForceInternalAccess1; + uint32_t McGeneralizedCarveout5ForceInternalAccess2; + uint32_t McGeneralizedCarveout5ForceInternalAccess3; + uint32_t McGeneralizedCarveout5ForceInternalAccess4; + uint32_t McGeneralizedCarveout5Cfg0; + uint32_t EmcCaTrainingEnable; + uint32_t SwizzleRankByteEncode; + uint32_t BootRomPatchControl; + uint32_t BootRomPatchData; + uint32_t McMtsCarveoutBom; + uint32_t McMtsCarveoutAdrHi; + uint32_t McMtsCarveoutSizeMb; + uint32_t McMtsCarveoutRegCtrl; + uint32_t McUntranslatedRegionCheck; + uint32_t BCT_NA; +} sdram_params_mariko_t; + +#endif