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fusee: perform only pmic reboots on mariko

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This commit is contained in:
Michael Scire 2021-01-05 00:55:29 -08:00
parent c06f0440fd
commit 557903cfa7
2 changed files with 159 additions and 80 deletions
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107
fusee/fusee-primary/fusee-primary-main/src/utils.c
View file

@ -22,9 +22,11 @@
#include "fuse.h"
#include "pmc.h"
#include "timers.h"
#include "i2c.h"
#include "panic.h"
#include "car.h"
#include "btn.h"
#include "max77620.h"
#include "../../../fusee/common/log.h"
#include "../../../fusee/common/vsprintf.h"
#include "../../../fusee/common/display/video_fb.h"
@ -37,6 +39,37 @@
#undef u8
#undef u32
static bool is_soc_mariko(void) {
return fuse_get_soc_type() == 1;
}
__attribute__((noreturn)) static void shutdown_system(bool reboot) {
/* Ensure that i2c5 is in a coherent state. */
i2c_config(I2C_5);
clkrst_reboot(CARDEVICE_I2C5);
i2c_init(I2C_5);
/* Get value, set or clear software reset mask. */
uint8_t on_off_2_val = 0;
i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG2, &on_off_2_val, 1);
if (reboot) {
on_off_2_val |= MAX77620_ONOFFCNFG2_SFT_RST_WK;
} else {
on_off_2_val &= ~(MAX77620_ONOFFCNFG2_SFT_RST_WK);
}
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG2, &on_off_2_val, 1);
/* Set software reset mask. */
uint8_t on_off_1_val = 0;
i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &on_off_1_val, 1);
on_off_1_val |= MAX77620_ONOFFCNFG1_SFT_RST;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &on_off_1_val, 1);
while (true) {
/* Wait for reboot. */
}
}
extern uint8_t __reboot_start__[], __reboot_end__[];
void wait(uint32_t microseconds) {
@ -70,43 +103,47 @@ __attribute__((noreturn)) void pmc_reboot(uint32_t scratch0) {
}
__attribute__((noreturn)) void reboot_to_self(void) {
/* Patch SDRAM init to perform an SVC immediately after second write */
APBDEV_PMC_SCRATCH45_0 = 0x2E38DFFF;
APBDEV_PMC_SCRATCH46_0 = 0x6001DC28;
/* Set SVC handler to jump to reboot stub in IRAM. */
APBDEV_PMC_SCRATCH33_0 = 0x4003F000;
APBDEV_PMC_SCRATCH40_0 = 0x6000F208;
if (is_soc_mariko()) {
/* If mariko, we can't reboot to self/payload, so just reboot. */
shutdown_system(true);
} else {
/* Patch SDRAM init to perform an SVC immediately after second write */
APBDEV_PMC_SCRATCH45_0 = 0x2E38DFFF;
APBDEV_PMC_SCRATCH46_0 = 0x6001DC28;
/* Set SVC handler to jump to reboot stub in IRAM. */
APBDEV_PMC_SCRATCH33_0 = 0x4003F000;
APBDEV_PMC_SCRATCH40_0 = 0x6000F208;
/* Copy reboot stub into IRAM high. */
for (size_t i = 0; i < rebootstub_bin_size; i += sizeof(uint32_t)) {
write32le((void *)0x4003F000, i, read32le(rebootstub_bin, i));
/* Copy reboot stub into IRAM high. */
for (size_t i = 0; i < rebootstub_bin_size; i += sizeof(uint32_t)) {
write32le((void *)0x4003F000, i, read32le(rebootstub_bin, i));
}
/* Copy our low part into safe IRAM. */
for (size_t i = 0; i < 0x8000; i += sizeof(uint32_t)) {
write32le((void *)0x40030000, i, read32le((void *)0x40008000, i));
}
/* Copy our start page into fatal IRAM. */
for (size_t i = 0; i < 0x1000; i += sizeof(uint32_t)) {
write32le((void *)0x4003D000, i, read32le((void *)0x40010000, i));
}
/* Copy our reboot handler to the rebootstub target. */
for (size_t i = 0; i < (__reboot_end__ - __reboot_start__); i += sizeof(uint32_t)) {
write32le((void *)0x40010000, i, read32le(__reboot_start__, i));
}
/* Trigger warm reboot. */
APBDEV_PMC_SCRATCH0_0 = (1 << 0);
/* Reset the processor. */
APBDEV_PMC_CONTROL = BIT(4);
while (true) {
/* Wait for reboot. */
}
}
/* Copy our low part into safe IRAM. */
for (size_t i = 0; i < 0x8000; i += sizeof(uint32_t)) {
write32le((void *)0x40030000, i, read32le((void *)0x40008000, i));
}
/* Copy our start page into fatal IRAM. */
for (size_t i = 0; i < 0x1000; i += sizeof(uint32_t)) {
write32le((void *)0x4003D000, i, read32le((void *)0x40010000, i));
}
/* Copy our reboot handler to the rebootstub target. */
for (size_t i = 0; i < (__reboot_end__ - __reboot_start__); i += sizeof(uint32_t)) {
write32le((void *)0x40010000, i, read32le(__reboot_start__, i));
}
/* Trigger warm reboot. */
APBDEV_PMC_SCRATCH0_0 = (1 << 0);
/* Reset the processor. */
APBDEV_PMC_CONTROL = BIT(4);
while (true) {
/* Wait for reboot. */
}
}
__attribute__((noreturn)) void wait_for_button_and_reboot(void) {

118
fusee/fusee-secondary/src/utils.c
View file

@ -23,7 +23,9 @@
#include "car.h"
#include "timers.h"
#include "btn.h"
#include "i2c.h"
#include "panic.h"
#include "max77620.h"
#include "../../../fusee/common/log.h"
#include <stdio.h>
@ -37,6 +39,37 @@
#undef u8
#undef u32
static bool is_soc_mariko(void) {
return fuse_get_soc_type() == 1;
}
__attribute__((noreturn)) static void shutdown_system(bool reboot) {
/* Ensure that i2c5 is in a coherent state. */
i2c_config(I2C_5);
clkrst_reboot(CARDEVICE_I2C5);
i2c_init(I2C_5);
/* Get value, set or clear software reset mask. */
uint8_t on_off_2_val = 0;
i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG2, &on_off_2_val, 1);
if (reboot) {
on_off_2_val |= MAX77620_ONOFFCNFG2_SFT_RST_WK;
} else {
on_off_2_val &= ~(MAX77620_ONOFFCNFG2_SFT_RST_WK);
}
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG2, &on_off_2_val, 1);
/* Set software reset mask. */
uint8_t on_off_1_val = 0;
i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &on_off_1_val, 1);
on_off_1_val |= MAX77620_ONOFFCNFG1_SFT_RST;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &on_off_1_val, 1);
while (true) {
/* Wait for reboot. */
}
}
void wait(uint32_t microseconds) {
uint32_t old_time = TIMERUS_CNTR_1US_0;
while (TIMERUS_CNTR_1US_0 - old_time <= microseconds) {
@ -67,21 +100,26 @@ __attribute__((noreturn)) void pmc_reboot(uint32_t scratch0) {
}
__attribute__((noreturn)) static void reboot_to_payload(void) {
/* Patch SDRAM init to perform an SVC immediately after second write */
APBDEV_PMC_SCRATCH45_0 = 0x2E38DFFF;
APBDEV_PMC_SCRATCH46_0 = 0x6001DC28;
/* Set SVC handler to jump to reboot stub in IRAM. */
APBDEV_PMC_SCRATCH33_0 = 0x4003F000;
APBDEV_PMC_SCRATCH40_0 = 0x6000F208;
if (is_soc_mariko()) {
/* Reboot to payload isn't possible on mariko, so just do normal reboot. */
shutdown_system(true);
} else {
/* Patch SDRAM init to perform an SVC immediately after second write */
APBDEV_PMC_SCRATCH45_0 = 0x2E38DFFF;
APBDEV_PMC_SCRATCH46_0 = 0x6001DC28;
/* Set SVC handler to jump to reboot stub in IRAM. */
APBDEV_PMC_SCRATCH33_0 = 0x4003F000;
APBDEV_PMC_SCRATCH40_0 = 0x6000F208;
/* Copy reboot stub into IRAM high. */
for (size_t i = 0; i < rebootstub_bin_size; i += sizeof(uint32_t)) {
write32le((void *)0x4003F000, i, read32le(rebootstub_bin, i));
/* Copy reboot stub into IRAM high. */
for (size_t i = 0; i < rebootstub_bin_size; i += sizeof(uint32_t)) {
write32le((void *)0x4003F000, i, read32le(rebootstub_bin, i));
}
/* Trigger warm reboot. */
pmc_reboot(1 << 0);
while (true) { }
}
/* Trigger warm reboot. */
pmc_reboot(1 << 0);
while (true) { }
}
__attribute__((noreturn)) void reboot_to_fusee_primary(void) {
@ -94,33 +132,37 @@ __attribute__((noreturn)) void reboot_to_fusee_primary(void) {
}
__attribute__((noreturn)) void reboot_to_sept(const void *tsec_fw, size_t tsec_fw_length, const void *stage2, size_t stage2_size) {
if (is_soc_mariko()) {
/* Reboot to sept isn't possible on mariko, so just do normal reboot. */
shutdown_system(true);
} else {
/* Copy tsec firmware. */
for (size_t i = 0; i < tsec_fw_length; i += sizeof(uint32_t)) {
write32le((void *)0x40010F00, i, read32le(tsec_fw, i));
}
MAKE_REG32(0x40010EFC) = tsec_fw_length;
/* Copy tsec firmware. */
for (size_t i = 0; i < tsec_fw_length; i += sizeof(uint32_t)) {
write32le((void *)0x40010F00, i, read32le(tsec_fw, i));
/* Copy stage 2. */
for (size_t i = 0; i < stage2_size; i += sizeof(uint32_t)) {
write32le((void *)0x40016FE0, i, read32le(stage2, i));
}
/* Copy sept into IRAM low. */
for (size_t i = 0; i < sept_primary_bin_size; i += sizeof(uint32_t)) {
write32le((void *)0x4003F000, i, read32le(sept_primary_bin, i));
}
/* Patch SDRAM init to perform an SVC immediately after second write */
APBDEV_PMC_SCRATCH45_0 = 0x2E38DFFF;
APBDEV_PMC_SCRATCH46_0 = 0x6001DC28;
/* Set SVC handler to jump to reboot stub in IRAM. */
APBDEV_PMC_SCRATCH33_0 = 0x4003F000;
APBDEV_PMC_SCRATCH40_0 = 0x6000F208;
/* Trigger warm reboot. */
pmc_reboot(1 << 0);
while (true) { }
}
MAKE_REG32(0x40010EFC) = tsec_fw_length;
/* Copy stage 2. */
for (size_t i = 0; i < stage2_size; i += sizeof(uint32_t)) {
write32le((void *)0x40016FE0, i, read32le(stage2, i));
}
/* Copy sept into IRAM low. */
for (size_t i = 0; i < sept_primary_bin_size; i += sizeof(uint32_t)) {
write32le((void *)0x4003F000, i, read32le(sept_primary_bin, i));
}
/* Patch SDRAM init to perform an SVC immediately after second write */
APBDEV_PMC_SCRATCH45_0 = 0x2E38DFFF;
APBDEV_PMC_SCRATCH46_0 = 0x6001DC28;
/* Set SVC handler to jump to reboot stub in IRAM. */
APBDEV_PMC_SCRATCH33_0 = 0x4003F000;
APBDEV_PMC_SCRATCH40_0 = 0x6000F208;
/* Trigger warm reboot. */
pmc_reboot(1 << 0);
while (true) { }
}
__attribute__((noreturn)) void reboot_to_iram_payload(void *payload, size_t payload_size) {