mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-11-09 22:56:35 +00:00
hexkyz
GitHub
commit
116eb6c67c
2 changed files with 119 additions and 17 deletions
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@ -17,37 +17,37 @@ void uart_init(UartDevice dev, uint32_t baud) {
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/* Set baud rate. */
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uint32_t rate = (8 * baud + 408000000) / (16 * baud);
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uart->UART_LCR = 0x80; /* Enable DLAB. */
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uart->UART_LCR = UART_LCR_DLAB; /* Enable DLAB. */
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uart->UART_THR_DLAB = (uint8_t)rate; /* Divisor latch LSB. */
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uart->UART_IER_DLAB = (uint8_t)(rate >> 8); /* Divisor latch MSB. */
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uart->UART_LCR = 0; /* Diable DLAB. */
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/* Setup UART in fifo mode. */
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uart->UART_IER_DLAB = 0;
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uart->UART_IIR_FCR = 7; /* Enable and clear TX and RX FIFOs. */
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uart->UART_IIR_FCR = UART_FCR_FCR_EN_FIFO | UART_FCR_RX_CLR | UART_FCR_TX_CLR; /* Enable and clear TX and RX FIFOs. */
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uart->UART_LSR;
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wait(3 * ((baud + 999999) / baud));
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uart->UART_LCR = 3; /* Set word length 8. */
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uart->UART_LCR = UART_LCR_WD_LENGTH_8; /* Set word length 8. */
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uart->UART_MCR = 0;
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uart->UART_MSR = 0;
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uart->UART_IRDA_CSR = 0;
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uart->UART_RX_FIFO_CFG = 1;
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uart->UART_RX_FIFO_CFG = 1; /* Set RX_FIFO trigger level */
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uart->UART_MIE = 0;
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uart->UART_ASR = 0;
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}
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void uart_wait_idle(UartDevice dev, uint32_t which) {
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while (!(get_uart_device(dev)->UART_VENDOR_STATUS & which)) {
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/* This function blocks until the UART device (dev) is in the desired state (status). Make sure the desired state can be reached! */
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void uart_wait_idle(UartDevice dev, UartVendorStatus status) {
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while (!(get_uart_device(dev)->UART_VENDOR_STATUS & status)) {
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/* Wait */
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}
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}
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void uart_send(UartDevice dev, const void *buf, size_t len)
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{
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void uart_send(UartDevice dev, const void *buf, size_t len) {
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volatile uart_t *uart = get_uart_device(dev);
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for (size_t i = 0; i < len; i++) {
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while (uart->UART_LSR & UART_TX_FIFO_FULL) {
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while (uart->UART_LSR & UART_LSR_TX_FIFO_FULL) {
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/* Wait until the TX FIFO isn't full */
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}
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uart->UART_THR_DLAB = *((const uint8_t *)buf + i);
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@ -58,9 +58,9 @@ void uart_recv(UartDevice dev, void *buf, size_t len) {
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volatile uart_t *uart = get_uart_device(dev);
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for (size_t i = 0; i < len; i++) {
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while (uart->UART_LSR & UART_RX_FIFO_EMPTY) {
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while (uart->UART_LSR & UART_LSR_RX_FIFO_EMPTY) {
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/* Wait until the RX FIFO isn't empty */
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}
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*((uint8_t *)buf + i) = uart->UART_THR_DLAB;
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*((uint8_t *)buf + i) = uart->UART_THR_DLAB;
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}
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}
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@ -13,6 +13,8 @@ static inline uintptr_t get_uart_base(void) {
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#define UART_BASE (get_uart_base())
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#define BAUD_115200 115200
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/* Exosphère: add the clkreset values for UART C,D,E */
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typedef enum {
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UART_A = 0,
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@ -22,12 +24,112 @@ typedef enum {
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UART_E = 4,
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} UartDevice;
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#define BAUD_115200 115200
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/* 36.3.12 UART_VENDOR_STATUS_0_0 */
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typedef enum {
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UART_VENDOR_STATE_TX_IDLE = 1 << 0,
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UART_VENDOR_STATE_RX_IDLE = 1 << 1,
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#define UART_TX_IDLE 0x00000001
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#define UART_RX_IDLE 0x00000002
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#define UART_TX_FIFO_FULL 0x100
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#define UART_RX_FIFO_EMPTY 0x200
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/* This bit is set to 1 when a read is issued to an empty FIFO and gets cleared on register read (sticky bit until read)
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0 = NO_UNDERRUN
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1 = UNDERRUN
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*/
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UART_VENDOR_STATE_RX_UNDERRUN = 1 << 2,
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/* This bit is set to 1 when write data is issued to the TX FIFO when it is already full and gets cleared on register read (sticky bit until read)
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0 = NO_OVERRUN
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1 = OVERRUN
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*/
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UART_VENDOR_STATE_TX_OVERRUN = 1 << 3,
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UART_VENDOR_STATE_RX_FIFO_COUNTER = 0b111111 << 16, /* reflects number of current entries in RX FIFO */
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UART_VENDOR_STATE_TX_FIFO_COUNTER = 0b111111 << 24 /* reflects number of current entries in TX FIFO */
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} UartVendorStatus;
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/* 36.3.6 UART_LSR_0 */
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typedef enum {
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UART_LSR_RDR = 1 << 0, /* Receiver Data Ready */
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UART_LSR_OVRF = 1 << 1, /* Receiver Overrun Error */
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UART_LSR_PERR = 1 << 2, /* Parity Error */
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UART_LSR_FERR = 1 << 3, /* Framing Error */
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UART_LSR_BRK = 1 << 4, /* BREAK condition detected on line */
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UART_LSR_THRE = 1 << 5, /* Transmit Holding Register is Empty -- OK to write data */
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UART_LSR_TMTY = 1 << 6, /* Transmit Shift Register empty status */
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UART_LSR_FIFOE = 1 << 7, /* Receive FIFO Error */
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UART_LSR_TX_FIFO_FULL = 1 << 8, /* Transmitter FIFO full status */
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UART_LSR_RX_FIFO_EMPTY = 1 << 9, /* Receiver FIFO empty status */
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} UartLineStatus;
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/* 36.3.4 UART_LCR_0 */
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typedef enum {
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UART_LCR_WD_LENGTH_5 = 0, /* word length 5 */
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UART_LCR_WD_LENGTH_6 = 1, /* word length 6 */
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UART_LCR_WD_LENGTH_7 = 2, /* word length 7 */
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UART_LCR_WD_LENGTH_8 = 3, /* word length 8 */
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/* STOP:
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0 = Transmit 1 stop bit
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1 = Transmit 2 stop bits (receiver always checks for 1 stop bit)
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*/
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UART_LCR_STOP = 1 << 2,
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UART_LCR_PAR = 1 << 3, /* Parity enabled */
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UART_LCR_EVEN = 1 << 4, /* Even parity format. There will always be an even number of 1s in the binary representation (PAR = 1) */
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UART_LCR_SET_P = 1 << 5, /* Set (force) parity to value in LCR[4] */
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UART_LCR_SET_B = 1 << 6, /* Set BREAK condition -- Transmitter sends all zeroes to indicate BREAK */
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UART_LCR_DLAB = 1 << 7, /* Divisor Latch Access Bit (set to allow programming of the DLH, DLM Divisors) */
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} UartLineControl;
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/* 36.3.3 UART_IIR_FCR_0 */
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typedef enum {
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UART_FCR_FCR_EN_FIFO = 1 << 0, /* Enable the transmit and receive FIFOs. This bit should be enabled */
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UART_FCR_RX_CLR = 1 << 1, /* Clears the contents of the receive FIFO and resets its counter logic to 0 (the receive shift register is not cleared or altered). This bit returns to 0 after clearing the FIFOs */
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UART_FCR_TX_CLR = 1 << 2, /* Clears the contents of the transmit FIFO and resets its counter logic to 0 (the transmit shift register is not cleared or altered). This bit returns to 0 after clearing the FIFOs */
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/* DMA:
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0 = DMA_MODE_0
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1 = DMA_MODE_1
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*/
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UART_FCR_DMA = 1 << 3,
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/* TX_TRIG
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0 = FIFO_COUNT_GREATER_16
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1 = FIFO_COUNT_GREATER_8
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2 = FIFO_COUNT_GREATER_4
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3 = FIFO_COUNT_GREATER_1
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*/
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UART_FCR_TX_TRIG = 3 << 4,
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UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_16 = 0 << 4,
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UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_8 = 1 << 4,
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UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_4 = 2 << 4,
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UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_1 = 3 << 4,
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/* RX_TRIG
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0 = FIFO_COUNT_GREATER_1
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1 = FIFO_COUNT_GREATER_4
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2 = FIFO_COUNT_GREATER_8
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3 = FIFO_COUNT_GREATER_16
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*/
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UART_FCR_RX_TRIG = 3 << 6,
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UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_1 = 0 << 6,
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UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_4 = 1 << 6,
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UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_8 = 2 << 6,
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UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_16 = 3 << 6,
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} UartFifoControl;
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/* 36.3.3 UART_IIR_FCR_0 */
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typedef enum {
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UART_IIR_IS_STA = 1 << 0, /* Interrupt Pending if ZERO */
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UART_IIR_IS_PRI0 = 1 << 1, /* Encoded Interrupt ID Refer to IIR[3:0] table [36.3.3] */
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UART_IIR_IS_PRI1 = 1 << 2, /* Encoded Interrupt ID Refer to IIR[3:0] table */
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UART_IIR_IS_PRI2 = 1 << 3, /* Encoded Interrupt ID Refer to IIR[3:0] table */
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/* FIFO Mode Status
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0 = 16450 mode (no FIFO)
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1 = 16550 mode (FIFO)
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*/
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UART_IIR_EN_FIFO = 3 << 6,
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UART_IIR_MODE_16450 = 0 << 6,
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UART_IIR_MODE_16550 = 1 << 6,
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} UartInterruptIdentification;
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typedef struct {
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/* 0x00 */ uint32_t UART_THR_DLAB;
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@ -48,7 +150,7 @@ typedef struct {
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void uart_select(UartDevice dev);
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void uart_init(UartDevice dev, uint32_t baud);
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void uart_wait_idle(UartDevice dev, uint32_t which);
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void uart_wait_idle(UartDevice dev, UartVendorStatus status);
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void uart_send(UartDevice dev, const void *buf, size_t len);
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void uart_recv(UartDevice dev, void *buf, size_t len);
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