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Merge pull request #114 from desowin/sdmmc-errata

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Set SDMMC controller to SDR104 as a workaround
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hexkyz 2018-06-04 16:20:19 +01:00 committed by GitHub
parent bfaa618749 0534e36cf8
commit 7e5fda86b2
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GPG key ID: 4AEE18F83AFDEB23
2 changed files with 4 additions and 2 deletions
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3
fusee/fusee-primary/src/sdmmc.c
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@ -1360,7 +1360,8 @@ static int sdmmc_apply_clock_speed(struct mmc *mmc, enum sdmmc_bus_speed speed,
case SDMMC_SPEED_SDR50:
mmc->regs->host_control |= MMC_HOST_ENABLE_HIGH_SPEED;
mmc->configure_clock(mmc, MMC_CLOCK_SOURCE_SDR50, MMC_CLOCK_DIVIDER_SDR50, MMC_CLOCK_CONTROL_FREQUENCY_PASSTHROUGH);
sdmmc_set_uhs_mode(mmc, SDMMC_SPEED_SDR50);
// Tegra X1 Series Processors Silicon Errata MMC-2 mentions setting SDR104 mode as workaround.
sdmmc_set_uhs_mode(mmc, SDMMC_SPEED_SDR104);
execute_tuning = true;
tuning_attempts = MMC_VENDOR_TUNING_TRIES_SDR50;

3
fusee/fusee-secondary/src/sdmmc.c
View file

@ -1360,7 +1360,8 @@ static int sdmmc_apply_clock_speed(struct mmc *mmc, enum sdmmc_bus_speed speed,
case SDMMC_SPEED_SDR50:
mmc->regs->host_control |= MMC_HOST_ENABLE_HIGH_SPEED;
mmc->configure_clock(mmc, MMC_CLOCK_SOURCE_SDR50, MMC_CLOCK_DIVIDER_SDR50, MMC_CLOCK_CONTROL_FREQUENCY_PASSTHROUGH);
sdmmc_set_uhs_mode(mmc, SDMMC_SPEED_SDR50);
// Tegra X1 Series Processors Silicon Errata MMC-2 mentions setting SDR104 mode as workaround.
sdmmc_set_uhs_mode(mmc, SDMMC_SPEED_SDR104);
execute_tuning = true;
tuning_attempts = MMC_VENDOR_TUNING_TRIES_SDR50;