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The bdk flag BDK_SDMMC_UHS_DDR200_SUPPORT can be used to enable it. SD Card DDR200 (DDR208) support Proper procedure: 1. Check that Vendor Specific Command System is supported. Used as Enable DDR200 Bus. 2. Enable DDR200 bus mode via setting 14 to Group 2 via CMD6. Access Mode group is left to default 0 (SDR12). 3. Setup clock to 200 or 208 MHz. 4. Set host to DDR bus mode that supports such high clocks. Some hosts have special mode, others use DDR50 and others HS400. 5. Execute Tuning. The true validation that this value in Group 2 activates it, is that DDR50 bus and clocks/timings work fully after that point. On Tegra X1, that can be done with DDR50 host mode. Tuning though can't be done automatically on any DDR mode. So it needs to be done manually and selected tap will be applied from the biggest sampling window. Finally, all that simply works, because the marketing materials for DDR200 are basically overstatements to sell the feature. DDR200 is simply SDR104 in DDR mode, so sampling on rising and falling edge and with variable output data window. It can be supported by any host that is fast enough to support DDR at 200/208MHz and can do hw/sw tuning for finding the proper sampling window in that mode. Using a SDMMC controller on DDR200 mode at 400MHz, has latency allowance implications. The MC/EMC must be clocked enough to be able to serve the requests in time (512B in 1.28 ns). |
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| .. | ||
| actmon.c | ||
| actmon.h | ||
| bpmp.c | ||
| bpmp.h | ||
| ccplex.c | ||
| ccplex.h | ||
| clock.c | ||
| clock.h | ||
| fuse.c | ||
| fuse.h | ||
| gpio.c | ||
| gpio.h | ||
| hw_init.c | ||
| hw_init.h | ||
| i2c.c | ||
| i2c.h | ||
| irq.c | ||
| irq.h | ||
| kfuse.c | ||
| kfuse.h | ||
| pinmux.c | ||
| pinmux.h | ||
| pmc.c | ||
| pmc.h | ||
| pmc_lp0_t210.h | ||
| t210.h | ||
| timer.c | ||
| timer.h | ||
| uart.c | ||
| uart.h | ||