mirror of
https://github.com/CTCaer/hekate
synced 2024-11-05 03:16:35 +00:00
202 lines
7.7 KiB
C
202 lines
7.7 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _CLOCK_H_
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#define _CLOCK_H_
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#include "../utils/types.h"
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/*! Clock registers. */
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#define CLK_RST_CONTROLLER_RST_SOURCE 0x0
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#define CLK_RST_CONTROLLER_RST_DEVICES_L 0x4
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#define CLK_RST_CONTROLLER_RST_DEVICES_H 0x8
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#define CLK_RST_CONTROLLER_RST_DEVICES_U 0xC
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L 0x10
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H 0x14
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U 0x18
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#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY 0x20
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#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER 0x24
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#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY 0x28
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#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER 0x2C
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#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30
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#define CLK_RST_CONTROLLER_MISC_CLK_ENB 0x48
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#define CLK_RST_CONTROLLER_OSC_CTRL 0x50
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#define CLK_RST_CONTROLLER_PLLC_BASE 0x80
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#define CLK_RST_CONTROLLER_PLLC_OUT 0x84
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#define CLK_RST_CONTROLLER_PLLC_MISC 0x88
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#define CLK_RST_CONTROLLER_PLLC_MISC_1 0x8C
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#define CLK_RST_CONTROLLER_PLLM_BASE 0x90
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#define CLK_RST_CONTROLLER_PLLM_MISC1 0x98
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#define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C
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#define CLK_RST_CONTROLLER_PLLP_BASE 0xA0
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#define CLK_RST_CONTROLLER_PLLD_BASE 0xD0
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#define CLK_RST_CONTROLLER_PLLD_MISC1 0xD8
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#define CLK_RST_CONTROLLER_PLLD_MISC 0xDC
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#define CLK_RST_CONTROLLER_PLLX_BASE 0xE0
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#define CLK_RST_CONTROLLER_PLLX_MISC 0xE4
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#define CLK_RST_CONTROLLER_PLLE_BASE 0xE8
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#define CLK_RST_CONTROLLER_PLLE_MISC 0xEC
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA 0xF8
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB 0xFC
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#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM 0x110
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 0x124
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 0x128
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#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 0x138
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#define CLK_RST_CONTROLLER_CLK_SOURCE_VI 0x148
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 0x150
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 0x154
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 0x164
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA 0x178
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB 0x17C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X 0x180
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 0x198
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC 0x1A0
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 0x1B8
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 0x1BC
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD 0x1C0
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#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE 0x1D4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC 0x1F4
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X 0x280
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#define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284
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#define CLK_RST_CONTROLLER_CLK_ENB_X_CLR 0x288
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#define CLK_RST_CONTROLLER_RST_DEVICES_X 0x28C
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#define CLK_RST_CONTROLLER_RST_DEV_X_SET 0x290
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#define CLK_RST_CONTROLLER_RST_DEV_X_CLR 0x294
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_Y 0x298
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#define CLK_RST_CONTROLLER_CLK_ENB_Y_SET 0x29C
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#define CLK_RST_CONTROLLER_CLK_ENB_Y_CLR 0x2A0
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#define CLK_RST_CONTROLLER_RST_DEVICES_Y 0x2A4
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#define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2A8
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#define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2AC
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#define CLK_RST_CONTROLLER_RST_DEV_L_SET 0x300
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#define CLK_RST_CONTROLLER_RST_DEV_L_CLR 0x304
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#define CLK_RST_CONTROLLER_RST_DEV_H_SET 0x308
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#define CLK_RST_CONTROLLER_RST_DEV_H_CLR 0x30C
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#define CLK_RST_CONTROLLER_RST_DEV_U_SET 0x310
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#define CLK_RST_CONTROLLER_RST_DEV_U_CLR 0x314
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#define CLK_RST_CONTROLLER_CLK_ENB_L_SET 0x320
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#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR 0x324
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#define CLK_RST_CONTROLLER_CLK_ENB_H_SET 0x328
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#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR 0x32C
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#define CLK_RST_CONTROLLER_CLK_ENB_U_SET 0x330
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#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR 0x334
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#define CLK_RST_CONTROLLER_RST_DEVICES_V 0x358
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#define CLK_RST_CONTROLLER_RST_DEVICES_W 0x35C
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_V 0x360
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_W 0x364
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#define CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2 0x388
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC 0x3A0
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD 0x3A4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT 0x3B4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 0x3C4
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SYS 0x400
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SE 0x42C
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#define CLK_RST_CONTROLLER_RST_DEV_V_CLR 0x434
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#define CLK_RST_CONTROLLER_CLK_ENB_V_SET 0x440
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#define CLK_RST_CONTROLLER_CLK_ENB_V_CLR 0x444
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#define CLK_RST_CONTROLLER_CLK_ENB_W_SET 0x448
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#define CLK_RST_CONTROLLER_CLK_ENB_W_CLR 0x44C
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#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET 0x450
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#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR 0x454
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#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2 0x488
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#define CLK_RST_CONTROLLER_PLLE_AUX 0x48C
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#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S0 0x4A0
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#define CLK_RST_CONTROLLER_PLLX_MISC_3 0x518
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE 0x554
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#define CLK_RST_CONTROLLER_SPARE_REG0 0x55C
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#define CLK_RST_CONTROLLER_PLLC4_BASE 0x5A4
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#define CLK_RST_CONTROLLER_PLLC4_MISC 0x5A8
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#define CLK_RST_CONTROLLER_PLLC_MISC_2 0x5D0
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#define CLK_RST_CONTROLLER_PLLC4_OUT 0x5E4
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#define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E8
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#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP 0x620
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 0x65C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x664
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL 0x66C
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM 0x694
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#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC 0x6A0
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#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER 0x704
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE 0x710
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#define CLK_NO_SOURCE 0x0
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/*! PLL control and status bits */
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#define PLLCX_BASE_ENABLE (1 << 30)
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#define PLLCX_BASE_REF_DIS (1 << 29)
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#define PLLCX_BASE_LOCK (1 << 27)
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#define PLLC_MISC_RESET (1 << 30)
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#define PLLC_MISC1_IDDQ (1 << 27)
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#define PLLC_OUT1_CLKEN (1 << 1)
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#define PLLC_OUT1_RSTN_CLR (1 << 0)
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#define PLLC4_MISC_EN_LCKDET (1 << 30)
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#define PLLC4_BASE_IDDQ (1 << 18)
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#define PLLC4_OUT3_CLKEN (1 << 1)
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#define PLLC4_OUT3_RSTN_CLR (1 << 0)
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/*! Generic clock descriptor. */
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typedef struct _clock_t
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{
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u32 reset;
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u32 enable;
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u32 source;
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u8 index;
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u8 clk_src;
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u8 clk_div;
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} clock_t;
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/*! Generic clock enable/disable. */
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void clock_enable(const clock_t *clk);
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void clock_disable(const clock_t *clk);
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/*! Clock control for specific hardware portions. */
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void clock_enable_fuse(bool enable);
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void clock_enable_uart(u32 idx);
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void clock_enable_i2c(u32 idx);
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void clock_disable_i2c(u32 idx);
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void clock_enable_se();
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void clock_enable_tzram();
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void clock_enable_host1x();
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void clock_disable_host1x();
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void clock_enable_tsec();
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void clock_disable_tsec();
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void clock_enable_sor_safe();
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void clock_disable_sor_safe();
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void clock_enable_sor0();
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void clock_disable_sor0();
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void clock_enable_sor1();
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void clock_disable_sor1();
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void clock_enable_kfuse();
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void clock_disable_kfuse();
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void clock_enable_cl_dvfs();
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void clock_disable_cl_dvfs();
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void clock_enable_coresight();
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void clock_disable_coresight();
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void clock_enable_pwm();
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void clock_disable_pwm();
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void clock_enable_pllc(u32 divn);
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void clock_disable_pllc();
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void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val);
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void clock_sdmmc_get_card_clock_div(u32 *pout, u16 *pdivisor, u32 type);
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int clock_sdmmc_is_not_reset_and_enabled(u32 id);
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void clock_sdmmc_enable(u32 id, u32 val);
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void clock_sdmmc_disable(u32 id);
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#endif
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