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https://github.com/CTCaer/hekate
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The bdk flag BDK_SDMMC_UHS_DDR200_SUPPORT can be used to enable it. SD Card DDR200 (DDR208) support Proper procedure: 1. Check that Vendor Specific Command System is supported. Used as Enable DDR200 Bus. 2. Enable DDR200 bus mode via setting 14 to Group 2 via CMD6. Access Mode group is left to default 0 (SDR12). 3. Setup clock to 200 or 208 MHz. 4. Set host to DDR bus mode that supports such high clocks. Some hosts have special mode, others use DDR50 and others HS400. 5. Execute Tuning. The true validation that this value in Group 2 activates it, is that DDR50 bus and clocks/timings work fully after that point. On Tegra X1, that can be done with DDR50 host mode. Tuning though can't be done automatically on any DDR mode. So it needs to be done manually and selected tap will be applied from the biggest sampling window. Finally, all that simply works, because the marketing materials for DDR200 are basically overstatements to sell the feature. DDR200 is simply SDR104 in DDR mode, so sampling on rising and falling edge and with variable output data window. It can be supported by any host that is fast enough to support DDR at 200/208MHz and can do hw/sw tuning for finding the proper sampling window in that mode. Using a SDMMC controller on DDR200 mode at 400MHz, has latency allowance implications. The MC/EMC must be clocked enough to be able to serve the requests in time (512B in 1.28 ns).
333 lines
11 KiB
C
333 lines
11 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2023 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _SDMMC_DRIVER_H_
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#define _SDMMC_DRIVER_H_
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#include <utils/types.h>
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#include <storage/sdmmc_t210.h>
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/*! SDMMC controller IDs. */
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#define SDMMC_1 0 // Version 4.00.
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#define SDMMC_2 1 // Version 5.1.
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#define SDMMC_3 2 // Version 4.00.
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#define SDMMC_4 3 // Version 5.1.
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/*! SDMMC power types. */
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#define SDMMC_POWER_OFF 0
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#define SDMMC_POWER_1_8 1
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#define SDMMC_POWER_3_3 2
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/*! SDMMC response types. */
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#define SDMMC_RSP_TYPE_0 0
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#define SDMMC_RSP_TYPE_1 1
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#define SDMMC_RSP_TYPE_2 2
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#define SDMMC_RSP_TYPE_3 3
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#define SDMMC_RSP_TYPE_4 4
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#define SDMMC_RSP_TYPE_5 5
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/*! SDMMC bus widths. */
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#define SDMMC_BUS_WIDTH_1 0
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#define SDMMC_BUS_WIDTH_4 1
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#define SDMMC_BUS_WIDTH_8 2
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/*! SDMMC mask interrupt status. */
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#define SDMMC_MASKINT_MASKED 0
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#define SDMMC_MASKINT_NOERROR 1
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#define SDMMC_MASKINT_ERROR 2
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/*! SDMMC present state. 0x24. */
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#define SDHCI_CMD_INHIBIT BIT(0)
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#define SDHCI_DATA_INHIBIT BIT(1)
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#define SDHCI_DAT_LINE_ACTIVE BIT(2)
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#define SDHCI_RETUNING_REQUEST BIT(3)
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#define SDHCI_EMMC_LINE_LVL_MASK (0xFU << 4)
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#define SDHCI_DATA_4_LVL BIT(4) // eMMC only.
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#define SDHCI_DATA_5_LVL BIT(5) // eMMC only.
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#define SDHCI_DATA_6_LVL BIT(6) // eMMC only.
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#define SDHCI_DATA_7_LVL BIT(7) // eMMC only.
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#define SDHCI_DOING_WRITE BIT(8)
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#define SDHCI_DOING_READ BIT(9) // SD only.
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#define SDHCI_SPACE_AVAILABLE BIT(10) // Write buffer empty.
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#define SDHCI_DATA_AVAILABLE BIT(11) // Read buffer has data.
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#define SDHCI_CARD_PRESENT BIT(16)
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#define SDHCI_CD_STABLE BIT(17)
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#define SDHCI_CD_LVL BIT(18)
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#define SDHCI_WRITE_PROTECT BIT(19)
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#define SDHCI_DATA_LVL_MASK 0xF00000
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#define SDHCI_DATA_0_LVL BIT(20)
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#define SDHCI_DATA_1_LVL BIT(21)
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#define SDHCI_DATA_2_LVL BIT(22)
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#define SDHCI_DATA_3_LVL BIT(23)
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#define SDHCI_CMD_LVL BIT(24)
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/*! SDMMC transfer mode. 0x0C. */
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#define SDHCI_TRNS_DMA BIT(0)
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#define SDHCI_TRNS_BLK_CNT_EN BIT(1)
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#define SDHCI_TRNS_AUTO_CMD12 (1U << 2)
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#define SDHCI_TRNS_AUTO_CMD23 (2U << 2)
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#define SDHCI_TRNS_WRITE (0U << 4)
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#define SDHCI_TRNS_READ BIT(4)
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#define SDHCI_TRNS_MULTI BIT(5)
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#define SDHCI_TRNS_RTYPE_R1 (0U << 6)
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#define SDHCI_TRNS_RTYPE_R5 BIT(6)
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#define SDHCI_TRNS_RSP_ERR_CHK BIT(7)
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#define SDHCI_TRNS_RSP_INT_DIS BIT(8)
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/*! SDMMC command. 0x0E. */
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#define SDHCI_CMD_RESP_MASK 0x3
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#define SDHCI_CMD_RESP_NO_RESP 0x0
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#define SDHCI_CMD_RESP_LEN136 0x1
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#define SDHCI_CMD_RESP_LEN48 0x2
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#define SDHCI_CMD_RESP_LEN48_BUSY 0x3
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#define SDHCI_CMD_CRC BIT(3)
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#define SDHCI_CMD_INDEX BIT(4)
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#define SDHCI_CMD_DATA BIT(5)
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#define SDHCI_CMD_TYPE_NORMAL (0U << 6)
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#define SDHCI_CMD_TYPE_SUSPEND (1U << 6)
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#define SDHCI_CMD_TYPE_RESUME (2U << 6)
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#define SDHCI_CMD_TYPE_ABORT (3U << 6)
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#define SDHCI_CMD_IDX(cmd) ((cmd) << 8)
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/*! SDMMC host control. 0x28. */
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#define SDHCI_CTRL_LED BIT(0)
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#define SDHCI_CTRL_4BITBUS BIT(1) // SD only.
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#define SDHCI_CTRL_HISPD BIT(2) // SD only.
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#define SDHCI_CTRL_DMA_MASK (3U << 3)
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#define SDHCI_CTRL_SDMA (0U << 3)
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#define SDHCI_CTRL_ADMA1 (1U << 3)
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#define SDHCI_CTRL_ADMA32 (2U << 3)
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#define SDHCI_CTRL_ADMA64 (3U << 3)
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#define SDHCI_CTRL_8BITBUS BIT(5) // eMMC only (or UHS-II).
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#define SDHCI_CTRL_CDTEST_INS BIT(6)
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#define SDHCI_CTRL_CDTEST_EN BIT(7)
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/*! SDMMC host control 2. 0x3E. */
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#define SDHCI_CTRL_UHS_MASK 0x7
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#define SDHCI_CTRL_VDD_180 BIT(3)
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#define SDHCI_CTRL_DRV_TYPE_B (0U << 4)
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#define SDHCI_CTRL_DRV_TYPE_A (1U << 4)
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#define SDHCI_CTRL_DRV_TYPE_C (2U << 4)
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#define SDHCI_CTRL_DRV_TYPE_D (3U << 4)
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#define SDHCI_CTRL_EXEC_TUNING BIT(6)
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#define SDHCI_CTRL_TUNED_CLK_SHIFT 7
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#define SDHCI_CTRL_TUNED_CLK BIT(7)
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#define SDHCI_HOST_VERSION_4_EN BIT(12)
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#define SDHCI_ADDRESSING_64BIT_EN BIT(13)
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#define SDHCI_CTRL_PRESET_VAL_EN BIT(15)
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/*! SDMMC power control. 0x29. */
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#define SDHCI_POWER_ON BIT(0)
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#define SDHCI_POWER_180 (5U << 1)
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#define SDHCI_POWER_300 (6U << 1)
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#define SDHCI_POWER_330 (7U << 1)
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#define SDHCI_POWER_MASK 0xF1 // UHS-II only.
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/*! SDMMC clock control. 0x2C. */
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#define SDHCI_CLOCK_INT_EN BIT(0) // Internal Clock.
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#define SDHCI_CLOCK_INT_STABLE BIT(1) // Internal Clock Stable.
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#define SDHCI_CLOCK_CARD_EN BIT(2)
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#define SDHCI_PROG_CLOCK_MODE BIT(5)
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#define SDHCI_DIV_HI_SHIFT 6
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#define SDHCI_DIV_HI_MASK (3U << SDHCI_DIV_HI_SHIFT)
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#define SDHCI_DIV_LO_SHIFT 8
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#define SDHCI_DIV_MASK (0xFFU << SDHCI_DIV_LO_SHIFT)
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/*! SDMMC software reset. 0x2F. */
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#define SDHCI_RESET_ALL BIT(0)
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#define SDHCI_RESET_CMD BIT(1)
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#define SDHCI_RESET_DATA BIT(2)
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/*! SDMMC interrupt status and control. 0x30/0x34. */
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#define SDHCI_INT_RESPONSE BIT(0)
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#define SDHCI_INT_DATA_END BIT(1)
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#define SDHCI_INT_BLK_GAP BIT(2)
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#define SDHCI_INT_DMA_END BIT(3)
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#define SDHCI_INT_SPACE_AVAIL BIT(4) // Write buffer empty.
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#define SDHCI_INT_DATA_AVAIL BIT(5) // Read buffer has data.
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#define SDHCI_INT_CARD_INSERT BIT(6)
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#define SDHCI_INT_CARD_REMOVE BIT(7)
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#define SDHCI_INT_CARD_INT BIT(8)
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#define SDHCI_INT_RETUNE BIT(12)
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#define SDHCI_INT_ERROR BIT(15)
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/*! SDMMC error interrupt status and control. 0x32/0x36. */
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#define SDHCI_ERR_INT_TIMEOUT BIT(0)
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#define SDHCI_ERR_INT_CRC BIT(1)
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#define SDHCI_ERR_INT_END_BIT BIT(2)
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#define SDHCI_ERR_INT_INDEX BIT(3)
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#define SDHCI_ERR_INT_DATA_TIMEOUT BIT(4)
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#define SDHCI_ERR_INT_DATA_CRC BIT(5)
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#define SDHCI_ERR_INT_DATA_END_BIT BIT(6)
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#define SDHCI_ERR_INT_BUS_POWER BIT(7)
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#define SDHCI_ERR_INT_AUTO_CMD12 BIT(8)
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#define SDHCI_ERR_INT_ADMA BIT(9)
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#define SDHCI_ERR_INT_TUNE BIT(10)
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#define SDHCI_ERR_INT_RSP BIT(11)
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#define SDHCI_ERR_INT_TARGET_RSP BIT(12)
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#define SDHCI_ERR_INT_SPI BIT(13)
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#define SDHCI_ERR_INT_VND_BOOT_TMO BIT(14)
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#define SDHCI_ERR_INT_VND_BOOT_ACK BIT(15)
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#define SDHCI_ERR_INT_ALL_EXCEPT_ADMA_BUSPWR \
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(SDHCI_ERR_INT_AUTO_CMD12 | SDHCI_ERR_INT_DATA_END_BIT | \
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SDHCI_ERR_INT_DATA_CRC | SDHCI_ERR_INT_DATA_TIMEOUT | \
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SDHCI_ERR_INT_INDEX | SDHCI_ERR_INT_END_BIT | \
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SDHCI_ERR_INT_CRC | SDHCI_ERR_INT_TIMEOUT)
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/*! Host Capability 1. 0x40. */
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#define SDHCI_CAP_TM_CLK_FREQ_MASK 0x3F
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#define SDHCI_CAP_TM_UNIT_MHZ BIT(7)
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#define SDHCI_CAP_BASE_CLK_FREQ_MASK (0xFFU << 8)
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#define SDHCI_CAP_MAX_BLK_LEN_MASK (3U << 16)
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#define SDHCI_CAP_EMMC_8BIT BIT(18)
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#define SDHCI_CAP_ADMA2 BIT(19)
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#define SDHCI_CAP_HISPD BIT(21)
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#define SDHCI_CAP_SDMA BIT(22)
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#define SDHCI_CAP_SUSPEND_RESUME BIT(23)
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#define SDHCI_CAP_3_3_V BIT(24)
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#define SDHCI_CAP_3_0_V BIT(25)
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#define SDHCI_CAP_1_8_V BIT(26)
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#define SDHCI_CAP_64BIT BIT(28)
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#define SDHCI_CAP_ASYNC_INT BIT(29)
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#define SDHCI_CAP_SLOT_TYPE_MASK (3U << 30)
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#define SDHCI_CAP_SLOT_TYPE_REMOVABLE (0U << 30)
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#define SDHCI_CAP_SLOT_TYPE_EMBEDDED (1U << 30)
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#define SDHCI_CAP_SLOT_TYPE_SHARED (2U << 30)
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#define SDHCI_CAP_SLOT_TYPE_UHS2 (3U << 30)
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/*! Host Capability 2. 0x44. */
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#define SDHCI_CAP_SDR50 BIT(0)
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#define SDHCI_CAP_SDR5104 BIT(1)
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#define SDHCI_CAP_DDR50 BIT(2)
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#define SDHCI_CAP_UHS2 BIT(3)
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#define SDHCI_CAP_DRV_TYPE_A BIT(4)
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#define SDHCI_CAP_DRV_TYPE_C BIT(5)
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#define SDHCI_CAP_DRV_TYPE_D BIT(6)
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#define SDHCI_CAP_RSP_TIMER_CNT_MASK (0xFU << 8)
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#define SDHCI_CAP_SDR50_TUNING BIT(13)
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#define SDHCI_CAP_RSP_MODES_MASK (3U << 14)
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#define SDHCI_CAP_CLK_MULT (0xFFU << 16)
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#define SDHCI_CAP_ADMA3 BIT(27)
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#define SDHCI_CAP_VDD2_1_8V BIT(28)
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/*! SDMMC max current. 0x48 */
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#define SDHCI_MAX_CURRENT_3_3_V_MASK (0xFFU << 0)
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#define SDHCI_MAX_CURRENT_3_0_V_MASK (0xFFU << 8)
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#define SDHCI_MAX_CURRENT_1_8_V_MASK (0xFFU << 16)
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#define SDHCI_MAX_CURRENT_MULTIPLIER 4
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/*! SDMMC max current. 0x4C */
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#define SDHCI_MAX_CURRENT_1_8_V_VDD2_MASK (0xFFU << 0)
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/*! SD bus speeds. */
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#define UHS_SDR12_BUS_SPEED 0
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#define HIGH_SPEED_BUS_SPEED 1
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#define UHS_SDR25_BUS_SPEED 1
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#define UHS_SDR50_BUS_SPEED 2
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#define UHS_SDR104_BUS_SPEED 3
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#define UHS_DDR50_BUS_SPEED 4
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#define HS400_BUS_SPEED 5
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/*! SDMMC timmings. */
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#define SDHCI_TIMING_MMC_ID 0
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#define SDHCI_TIMING_MMC_LS26 1
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#define SDHCI_TIMING_MMC_HS52 2
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#define SDHCI_TIMING_MMC_HS200 3
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#define SDHCI_TIMING_MMC_HS400 4
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#define SDHCI_TIMING_SD_ID 5
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#define SDHCI_TIMING_SD_DS12 6
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#define SDHCI_TIMING_SD_HS25 7
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#define SDHCI_TIMING_UHS_SDR12 8
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#define SDHCI_TIMING_UHS_SDR25 9
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#define SDHCI_TIMING_UHS_SDR50 10
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#define SDHCI_TIMING_UHS_SDR104 11
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#define SDHCI_TIMING_UHS_DDR50 12
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// SDR104 with a 163.2MHz -> 81.6MHz clock.
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#define SDHCI_TIMING_UHS_SDR82 13 // GC FPGA. Obsolete and Repurposed. MMC_HS50 -> SDR82.
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#define SDHCI_TIMING_MMC_HS100 14 // GC ASIC.
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#define SDHCI_TIMING_UHS_DDR200 15
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/*! SDMMC Low power features. */
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#define SDMMC_POWER_SAVE_DISABLE 0
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#define SDMMC_POWER_SAVE_ENABLE 1
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/*! Helper for SWITCH command argument. */
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#define SDMMC_SWITCH(mode, index, value) (((mode) << 24) | ((index) << 16) | ((value) << 8))
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#define HW_TAP_TUNING 0x100
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#define INVALID_TAP 0x100
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/*! SDMMC controller context. */
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typedef struct _sdmmc_t
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{
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t210_sdmmc_t *regs;
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u32 id;
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u32 card_clock;
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u32 clock_stopped;
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int powersave_enabled;
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int manual_cal;
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int card_clock_enabled;
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int venclkctl_set;
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u32 venclkctl_tap;
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u32 expected_rsp_type;
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u32 dma_addr_next;
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u32 rsp[4];
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u32 rsp3;
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int t210b01;
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} sdmmc_t;
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/*! SDMMC command. */
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typedef struct _sdmmc_cmd_t
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{
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u16 cmd;
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u32 arg;
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u32 rsp_type;
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u32 check_busy;
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} sdmmc_cmd_t;
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/*! SDMMC request. */
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typedef struct _sdmmc_req_t
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{
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void *buf;
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u32 blksize;
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u32 num_sectors;
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int is_write;
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int is_multi_block;
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int is_auto_stop_trn;
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} sdmmc_req_t;
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int sdmmc_get_io_power(sdmmc_t *sdmmc);
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u32 sdmmc_get_bus_width(sdmmc_t *sdmmc);
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void sdmmc_set_bus_width(sdmmc_t *sdmmc, u32 bus_width);
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void sdmmc_save_tap_value(sdmmc_t *sdmmc);
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int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type);
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void sdmmc_card_clock_powersave(sdmmc_t *sdmmc, int powersave_enable);
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int sdmmc_get_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 size, u32 type);
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int sdmmc_tuning_execute(sdmmc_t *sdmmc, u32 type, u32 cmd);
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int sdmmc_stop_transmission(sdmmc_t *sdmmc, u32 *rsp);
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bool sdmmc_get_sd_inserted();
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int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type);
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void sdmmc_end(sdmmc_t *sdmmc);
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void sdmmc_init_cmd(sdmmc_cmd_t *cmdbuf, u16 cmd, u32 arg, u32 rsp_type, u32 check_busy);
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int sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *blkcnt_out);
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int sdmmc_enable_low_voltage(sdmmc_t *sdmmc);
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#endif
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