mirror of
https://github.com/CTCaer/hekate
synced 2024-07-06 00:13:29 +00:00
5e8eb1c57a
This will fix everything that uses a timer (or sleep). Without this any function like eMMC/SD read/write/verify, TSEC/SE, etc can break when the time reaches the max value of the u32 microsecond timer (71minutes). This fixes every possible breakage, including backup and restore (read/write/verify errors) that takes a lot of time. The new max before a timer reset is now 48 days (the old one was 71 minutes)
138 lines
2.9 KiB
C
Executable file
138 lines
2.9 KiB
C
Executable file
/*
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* Copyright (c) 2018 naehrwert
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include "tsec.h"
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#include "clock.h"
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#include "t210.h"
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#include "heap.h"
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#include "util.h"
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static int _tsec_dma_wait_idle()
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{
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u32 timeout = get_tmr_ms() + 10000;
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while (!(TSEC(0x1118) & 2))
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if (get_tmr_ms() > timeout)
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return 0;
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return 1;
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}
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static int _tsec_dma_pa_to_internal_100(int not_imem, int i_offset, int pa_offset)
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{
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u32 cmd;
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if (not_imem)
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cmd = 0x600; // DMA 0x100 bytes
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else
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cmd = 0x10; // dma imem
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TSEC(0x1114) = i_offset; // tsec_dmatrfmoffs_r
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TSEC(0x111C) = pa_offset; // tsec_dmatrffboffs_r
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TSEC(0x1118) = cmd; // tsec_dmatrfcmd_r
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return _tsec_dma_wait_idle();
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}
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int tsec_query(u8 *dst, u32 rev, void *fw)
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{
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int res = 0;
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//Enable clocks.
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clock_enable_host1x();
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clock_enable_tsec();
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clock_enable_sor_safe();
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clock_enable_sor0();
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clock_enable_sor1();
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clock_enable_kfuse();
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//Configure Falcon.
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TSEC(0x110C) = 0; // tsec_dmactl_r
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TSEC(0x1010) = 0xFFF2; // tsec_irqmset_r
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TSEC(0x101C) = 0xFFF0; // tsec_irqdest_r
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TSEC(0x1048) = 3; // tsec_itfen_r
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if (!_tsec_dma_wait_idle())
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{
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res = -1;
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goto out;
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}
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//Load firmware.
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u8 *fwbuf = (u8 *)malloc(0x2000);
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u8 *fwbuf_aligned = (u8 *)ALIGN((u32)fwbuf + 0x1000, 0x100);
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memcpy(fwbuf_aligned, fw, 0xF00);
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TSEC(0x1110) = (u32)fwbuf_aligned >> 8;// tsec_dmatrfbase_r
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for (u32 addr = 0; addr < 0xF00; addr += 0x100)
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if (!_tsec_dma_pa_to_internal_100(0, addr, addr))
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{
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res = -2;
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goto out_free;
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}
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//Execute firmware.
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HOST1X(0x3300) = 0x34C2E1DA;
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TSEC(0x1044) = 0;
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TSEC(0x1040) = rev;
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TSEC(0x1104) = 0; // tsec_bootvec_r
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TSEC(0x1100) = 2; // tsec_cpuctl_r
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if (!_tsec_dma_wait_idle())
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{
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res = -3;
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goto out_free;
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}
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u32 timeout = get_tmr_ms() + 2000;
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while (!TSEC(0x1044))
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if (get_tmr_ms() > timeout)
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{
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res = -4;
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goto out_free;
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}
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if (TSEC(0x1044) != 0xB0B0B0B0)
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{
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res = -5;
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goto out_free;
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}
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//Fetch result.
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HOST1X(0x3300) = 0;
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u32 buf[4];
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buf[0] = SOR1(0x1E8);
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buf[1] = SOR1(0x21C);
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buf[2] = SOR1(0x208);
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buf[3] = SOR1(0x20C);
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SOR1(0x1E8) = 0;
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SOR1(0x21C) = 0;
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SOR1(0x208) = 0;
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SOR1(0x20C) = 0;
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memcpy(dst, &buf, 0x10);
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out_free:;
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free(fwbuf);
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out:;
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//Disable clocks.
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clock_disable_kfuse();
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clock_disable_sor1();
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clock_disable_sor0();
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clock_disable_sor_safe();
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clock_disable_tsec();
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clock_disable_host1x();
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return res;
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}
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