mirror of
https://github.com/CTCaer/hekate
synced 2024-09-07 00:29:00 +00:00
![CTCaer](/assets/img/avatar_default.png)
It now supports more than one crypto block and keys are expected to slot 0 and up to slot 5.
226 lines
4.8 KiB
C
226 lines
4.8 KiB
C
/*
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* eMMC BIS driver for Nintendo Switch
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*
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* Copyright (c) 2019 shchmue
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* Copyright (c) 2019-2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include "../../../common/memory_map.h"
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#include "../sec/se.h"
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#include "../storage/nx_emmc.h"
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#include "../storage/sdmmc.h"
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#include "../utils/types.h"
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#define MAX_SEC_CACHE_ENTRIES 1500
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typedef struct _sector_cache_t
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{
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u32 sector;
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u32 visit_cnt;
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u8 tweak[0x10];
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u8 data[0x200];
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u8 align[8];
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} sector_cache_t;
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static u8 ks_crypt = 0;
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static u8 ks_tweak = 0;
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static u32 sector_cache_cnt = 0;
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static emmc_part_t *system_part = NULL;
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static sector_cache_t *sector_cache = (sector_cache_t *)NX_BIS_CACHE_ADDR;
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static void _gf256_mul_x_le(u8 *block)
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{
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u8 *pdata = (u8 *)block;
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u32 carry = 0;
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for (u32 i = 0; i < 0x10; i++)
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{
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u8 b = pdata[i];
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pdata[i] = (b << 1) | carry;
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carry = b >> 7;
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}
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if (carry)
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pdata[0x0] ^= 0x87;
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}
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static int _nx_aes_xts_crypt_sec(u32 ks1, u32 ks2, u32 enc, u8 *tweak, bool regen_tweak, u32 tweak_exp, u64 sec, void *dst, void *src, u32 sec_size)
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{
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u8 *pdst = (u8 *)dst;
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u8 *psrc = (u8 *)src;
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if (regen_tweak)
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{
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for (int i = 0xF; i >= 0; i--)
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{
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tweak[i] = sec & 0xFF;
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sec >>= 8;
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}
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if (!se_aes_crypt_block_ecb(ks1, 1, tweak, tweak))
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return 0;
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}
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for (u32 i = 0; i < (tweak_exp << 5); i++)
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_gf256_mul_x_le(tweak);
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u8 tmp_tweak[0x10];
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memcpy(tmp_tweak, tweak, 0x10);
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// We are assuming a 0x10-aligned sector size in this implementation.
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for (u32 i = 0; i < (sec_size >> 4); i++)
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{
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for (u32 j = 0; j < 0x10; j++)
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pdst[j] = psrc[j] ^ tweak[j];
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_gf256_mul_x_le(tweak);
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psrc += 0x10;
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pdst += 0x10;
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}
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se_aes_crypt_ecb(ks2, enc, dst, sec_size, src, sec_size);
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memcpy(tweak, tmp_tweak, 0x10);
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pdst = (u8 *)dst;
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for (u32 i = 0; i < (sec_size >> 4); i++)
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{
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for (u32 j = 0; j < 0x10; j++)
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pdst[j] = pdst[j] ^ tweak[j];
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_gf256_mul_x_le(tweak);
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pdst += 0x10;
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}
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return 1;
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}
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static int nx_emmc_bis_read_block(u32 sector, u32 count, void *buff)
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{
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if (!system_part)
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return 3; // Not ready.
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static u32 prev_cluster = -1;
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static u32 prev_sector = 0;
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static u8 tweak[0x10];
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u32 cache_idx = 0;
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u32 tweak_exp = 0;
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bool regen_tweak = true;
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bool cache_sector = false;
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if (count == 1)
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{
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for ( ; cache_idx < sector_cache_cnt; cache_idx++)
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{
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if (sector_cache[cache_idx].sector == sector)
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{
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sector_cache[cache_idx].visit_cnt++;
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memcpy(buff, sector_cache[cache_idx].data, 0x200);
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memcpy(tweak, sector_cache[cache_idx].tweak, 0x10);
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prev_sector = sector;
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prev_cluster = sector >> 5;
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return 0;
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}
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}
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// add to cache
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if (cache_idx == sector_cache_cnt && cache_idx < MAX_SEC_CACHE_ENTRIES)
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{
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sector_cache[cache_idx].sector = sector;
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sector_cache[cache_idx].visit_cnt++;
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cache_sector = true;
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sector_cache_cnt++;
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}
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}
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if (nx_emmc_part_read(&emmc_storage, system_part, sector, count, buff))
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{
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if (prev_cluster != sector >> 5) // Sector in different cluster than last read.
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{
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prev_cluster = sector >> 5;
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tweak_exp = sector % 0x20;
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}
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else if (sector > prev_sector) // Sector in same cluster and past last sector.
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{
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tweak_exp = sector - prev_sector - 1;
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regen_tweak = false;
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}
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else // Sector in same cluster and before or same as last sector.
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tweak_exp = sector % 0x20;
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// Maximum one cluster (1 XTS crypto block 16KB).
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_nx_aes_xts_crypt_sec(ks_tweak, ks_crypt, 0, tweak, regen_tweak, tweak_exp, prev_cluster, buff, buff, count << 9);
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if (cache_sector)
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{
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memcpy(sector_cache[cache_idx].data, buff, 0x200);
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memcpy(sector_cache[cache_idx].tweak, tweak, 0x10);
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}
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prev_sector = sector + count - 1;
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return 0;
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}
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// Error occurred.
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return 1;
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}
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int nx_emmc_bis_read(u32 sector, u32 count, void *buff)
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{
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int res = 1;
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u8 *buf = (u8 *)buff;
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u32 curr_sct = sector;
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while (count)
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{
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u32 sct_cnt = MIN(count, 0x20);
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res = nx_emmc_bis_read_block(curr_sct, sct_cnt, buf);
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if (res)
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return 1;
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count -= sct_cnt;
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curr_sct += sct_cnt;
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buf += 512 * sct_cnt;
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}
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return res;
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}
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void nx_emmc_bis_init(emmc_part_t *part)
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{
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system_part = part;
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sector_cache_cnt = 0;
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switch (part->index)
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{
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case 0: // PRODINFO.
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case 1: // PRODINFOF.
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ks_crypt = 0;
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ks_tweak = 1;
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break;
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case 8: // SAFE.
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ks_crypt = 2;
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ks_tweak = 3;
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break;
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case 9: // SYSTEM.
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case 10: // USER.
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ks_crypt = 4;
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ks_tweak = 5;
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break;
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}
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}
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