mirror of
https://github.com/CTCaer/hekate
synced 2024-11-03 02:26:35 +00:00
5e8eb1c57a
This will fix everything that uses a timer (or sleep). Without this any function like eMMC/SD read/write/verify, TSEC/SE, etc can break when the time reaches the max value of the u32 microsecond timer (71minutes). This fixes every possible breakage, including backup and restore (read/write/verify errors) that takes a lot of time. The new max before a timer reset is now 48 days (the old one was 71 minutes)
98 lines
1.9 KiB
C
Executable file
98 lines
1.9 KiB
C
Executable file
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (C) 2018 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "util.h"
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#include "t210.h"
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u32 get_tmr_s()
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{
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return RTC(0x8); //RTC_SECONDS
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}
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u32 get_tmr_ms()
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{
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// The registers must be read with the following order:
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// -> RTC_MILLI_SECONDS (0x10) -> RTC_SHADOW_SECONDS (0x8)
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return (RTC(0x10) | (RTC(0xC)<< 10));
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}
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u32 get_tmr_us()
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{
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return TMR(0x10); //TMRUS
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}
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void msleep(u32 milliseconds)
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{
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u32 start = get_tmr_ms();
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while ((get_tmr_ms() - start) <= milliseconds)
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;
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}
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void usleep(u32 microseconds)
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{
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u32 start = get_tmr_us();
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while ((get_tmr_us() - start) <= microseconds)
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;
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}
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void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops)
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{
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for(u32 i = 0; i < num_ops; i++)
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base[ops[i].off] = ops[i].val;
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}
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#define CRC32C_POLY 0x82F63B78
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u32 crc32c(const void *buf, u32 len)
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{
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const u8 *cbuf = (const u8 *)buf;
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u32 crc = 0xFFFFFFFF;
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while (len--)
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{
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crc ^= *cbuf++;
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for (int i = 0; i < 8; i++)
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crc = crc & 1 ? (crc >> 1) ^ CRC32C_POLY : crc >> 1;
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}
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return ~crc;
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}
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u32 memcmp32sparse(const u32 *buf1, const u32 *buf2, u32 len)
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{
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u32 len32 = len / 4;
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if (!(len32 % 32))
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{
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while (len32)
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{
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len32 -= 32;
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if(buf1[len32] != buf2[len32])
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return 1;
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}
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}
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else
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{
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while (len32)
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{
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len32 -= 32;
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if(buf1[len32] != buf2[len32])
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return 1;
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if (len32 < 32)
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return 0;
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}
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}
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return 0;
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}
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