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https://github.com/CTCaer/hekate
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![CTCaer](/assets/img/avatar_default.png)
- BDK_MINERVA_CFG_FROM_RAM: enables support for getting minerva configuration from nyx storage - BDK_HW_EXTRA_DEINIT: enables extra deinit in hw_reinit_workaround - BDK_SDMMC_OC_AND_EXTRA_PRINT: enables eMMC OC support (533 MB/s) and extra error printing
214 lines
5.2 KiB
C
214 lines
5.2 KiB
C
/*
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* Copyright (c) 2019-2022 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include <stdlib.h>
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#include "minerva.h"
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#include <ianos/ianos.h>
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#include <mem/emc.h>
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#include <soc/clock.h>
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#include <soc/fuse.h>
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#include <soc/hw_init.h>
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#include <soc/t210.h>
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#include <utils/util.h>
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extern volatile nyx_storage_t *nyx_str;
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void (*minerva_cfg)(mtc_config_t *mtc_cfg, void *);
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u32 minerva_init()
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{
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u32 curr_ram_idx = 0;
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minerva_cfg = NULL;
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mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
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//!TODO: Not supported on T210B01 yet.
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if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01)
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return 0;
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#ifdef BDK_MINERVA_CFG_FROM_RAM
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// Set table to nyx storage.
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mtc_cfg->mtc_table = (emc_table_t *)nyx_str->mtc_table;
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// Check if Minerva is already initialized.
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if (mtc_cfg->init_done == MTC_INIT_MAGIC)
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{
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mtc_cfg->train_mode = OP_PERIODIC_TRAIN; // Retrain if needed.
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u32 ep_addr = ianos_loader("bootloader/sys/libsys_minerva.bso", DRAM_LIB, (void *)mtc_cfg);
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minerva_cfg = (void *)ep_addr;
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return !minerva_cfg ? 1 : 0;
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}
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else
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{
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mtc_config_t mtc_tmp;
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mtc_tmp.mtc_table = mtc_cfg->mtc_table;
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mtc_tmp.sdram_id = fuse_read_dramid(false);
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mtc_tmp.init_done = MTC_NEW_MAGIC;
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u32 ep_addr = ianos_loader("bootloader/sys/libsys_minerva.bso", DRAM_LIB, (void *)&mtc_tmp);
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// Ensure that Minerva is new.
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if (mtc_tmp.init_done == MTC_INIT_MAGIC)
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minerva_cfg = (void *)ep_addr;
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else
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mtc_cfg->init_done = 0;
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// Copy Minerva context to Nyx storage.
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if (minerva_cfg)
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memcpy(mtc_cfg, (void *)&mtc_tmp, sizeof(mtc_config_t));
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}
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#else
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memset(mtc_cfg, 0, sizeof(mtc_config_t));
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// Set table to nyx storage.
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mtc_cfg->mtc_table = (emc_table_t *)nyx_str->mtc_table;
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mtc_cfg->sdram_id = fuse_read_dramid(false);
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mtc_cfg->init_done = MTC_NEW_MAGIC; // Initialize mtc table.
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u32 ep_addr = ianos_loader("bootloader/sys/libsys_minerva.bso", DRAM_LIB, (void *)mtc_cfg);
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// Ensure that Minerva is new.
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if (mtc_cfg->init_done == MTC_INIT_MAGIC)
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minerva_cfg = (void *)ep_addr;
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else
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mtc_cfg->init_done = 0;
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#endif
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if (!minerva_cfg)
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return 1;
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// Get current frequency
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u32 current_emc_clk_src = CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC);
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for (curr_ram_idx = 0; curr_ram_idx < 10; curr_ram_idx++)
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{
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if (current_emc_clk_src == mtc_cfg->mtc_table[curr_ram_idx].clk_src_emc)
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break;
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}
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mtc_cfg->rate_from = mtc_cfg->mtc_table[curr_ram_idx].rate_khz;
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mtc_cfg->rate_to = FREQ_204;
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mtc_cfg->train_mode = OP_TRAIN;
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minerva_cfg(mtc_cfg, NULL);
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mtc_cfg->rate_to = FREQ_800;
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minerva_cfg(mtc_cfg, NULL);
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mtc_cfg->rate_to = FREQ_1600;
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minerva_cfg(mtc_cfg, NULL);
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// FSP WAR.
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mtc_cfg->train_mode = OP_SWITCH;
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mtc_cfg->rate_to = FREQ_800;
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minerva_cfg(mtc_cfg, NULL);
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// Switch to max.
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mtc_cfg->rate_to = FREQ_1600;
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minerva_cfg(mtc_cfg, NULL);
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return 0;
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}
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void minerva_change_freq(minerva_freq_t freq)
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{
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if (!minerva_cfg)
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return;
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// Check if requested frequency is different. Do not allow otherwise because it will hang.
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mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
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if (mtc_cfg->rate_from != freq)
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{
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mtc_cfg->rate_to = freq;
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mtc_cfg->train_mode = OP_SWITCH;
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minerva_cfg(mtc_cfg, NULL);
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}
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}
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void minerva_prep_boot_freq()
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{
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if (!minerva_cfg)
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return;
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mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
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// Check if there's RAM OC. If not exit.
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if (mtc_cfg->mtc_table[mtc_cfg->table_entries - 1].rate_khz == FREQ_1600)
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return;
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// FSP WAR.
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minerva_change_freq(FREQ_204);
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// Scale down to 800 MHz boot freq.
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minerva_change_freq(FREQ_800);
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}
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void minerva_prep_boot_l4t()
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{
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if (!minerva_cfg)
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return;
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mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
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// Set init frequency.
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minerva_change_freq(FREQ_204);
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// Train the rest of the frequencies.
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mtc_cfg->train_mode = OP_TRAIN;
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for (u32 i = 0; i < mtc_cfg->table_entries; i++)
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{
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mtc_cfg->rate_to = mtc_cfg->mtc_table[i].rate_khz;
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// Skip already trained frequencies.
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if (mtc_cfg->rate_to == FREQ_204 || mtc_cfg->rate_to == FREQ_800 || mtc_cfg->rate_to == FREQ_1600)
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continue;
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// Train frequency.
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minerva_cfg(mtc_cfg, NULL);
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}
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// Do FSP WAR and scale to 800 MHz as boot freq.
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bool fsp_opwr_enabled = !!(EMC(EMC_MRW3) & 0xC0);
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if (fsp_opwr_enabled)
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minerva_change_freq(FREQ_666);
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minerva_change_freq(FREQ_800);
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// Do not let other mtc ops.
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mtc_cfg->init_done = 0;
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}
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void minerva_periodic_training()
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{
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if (!minerva_cfg)
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return;
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mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
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if (mtc_cfg->rate_from == FREQ_1600)
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{
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mtc_cfg->train_mode = OP_PERIODIC_TRAIN;
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minerva_cfg(mtc_cfg, NULL);
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}
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}
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emc_table_t *minerva_get_mtc_table()
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{
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if (!minerva_cfg)
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return NULL;
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mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
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return mtc_cfg->mtc_table;
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}
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