mirror of
https://github.com/CTCaer/hekate
synced 2024-09-07 08:39:00 +00:00
742 lines
22 KiB
C
742 lines
22 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018 st4rk
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* Copyright (c) 2018 Ced2911
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* Copyright (c) 2018-2019 CTCaer
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* Copyright (c) 2018 balika011
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include "hos.h"
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#include "hos_config.h"
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#include "sept.h"
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#include "secmon_exo.h"
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#include "../config/config.h"
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#include "../gfx/di.h"
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#include "../mem/heap.h"
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#include "../mem/mc.h"
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#include "../mem/minerva.h"
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#include "../sec/se.h"
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#include "../sec/se_t210.h"
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#include "../sec/tsec.h"
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#include "../soc/bpmp.h"
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#include "../soc/cluster.h"
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#include "../soc/fuse.h"
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#include "../soc/pmc.h"
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#include "../soc/smmu.h"
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#include "../soc/t210.h"
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#include "../storage/emummc.h"
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#include "../storage/nx_emmc.h"
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#include "../storage/sdmmc.h"
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#include "../utils/util.h"
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#include "../gfx/gfx.h"
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extern hekate_config h_cfg;
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extern void sd_unmount();
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extern bool sd_mount();
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//#define DPRINTF(...) gfx_printf(__VA_ARGS__)
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#define DPRINTF(...)
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#define EHPRINTF(text) \
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({ display_backlight_brightness(h_cfg.backlight, 1000); \
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gfx_con.mute = false; \
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gfx_printf("%k"text"%k\n", 0xFFFF0000, 0xFFCCCCCC); })
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#define EHPRINTFARGS(text, args...) \
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({ display_backlight_brightness(h_cfg.backlight, 1000); \
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gfx_con.mute = false; \
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gfx_printf("%k"text"%k\n", 0xFFFF0000, args, 0xFFCCCCCC); })
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#define PKG2_LOAD_ADDR 0xA9800000
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// Secmon mailbox.
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#define SECMON_MB_ADDR 0x40002EF8
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#define SECMON7_MB_ADDR 0x400000F8
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typedef struct _secmon_mailbox_t
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{
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// < 4.0.0 Signals - 0: Not ready, 1: BCT ready, 2: DRAM and pkg2 ready, 3: Continue boot.
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// >= 4.0.0 Signals - 0: Not ready, 1: BCT ready, 2: DRAM ready, 4: pkg2 ready and continue boot.
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u32 in;
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// Non-zero: Secmon ready.
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u32 out;
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} secmon_mailbox_t;
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static const u8 keyblob_keyseeds[][0x10] = {
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{ 0xDF, 0x20, 0x6F, 0x59, 0x44, 0x54, 0xEF, 0xDC, 0x70, 0x74, 0x48, 0x3B, 0x0D, 0xED, 0x9F, 0xD3 }, //1.0.0
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{ 0x0C, 0x25, 0x61, 0x5D, 0x68, 0x4C, 0xEB, 0x42, 0x1C, 0x23, 0x79, 0xEA, 0x82, 0x25, 0x12, 0xAC }, //3.0.0
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{ 0x33, 0x76, 0x85, 0xEE, 0x88, 0x4A, 0xAE, 0x0A, 0xC2, 0x8A, 0xFD, 0x7D, 0x63, 0xC0, 0x43, 0x3B }, //3.0.1
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{ 0x2D, 0x1F, 0x48, 0x80, 0xED, 0xEC, 0xED, 0x3E, 0x3C, 0xF2, 0x48, 0xB5, 0x65, 0x7D, 0xF7, 0xBE }, //4.0.0
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{ 0xBB, 0x5A, 0x01, 0xF9, 0x88, 0xAF, 0xF5, 0xFC, 0x6C, 0xFF, 0x07, 0x9E, 0x13, 0x3C, 0x39, 0x80 }, //5.0.0
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{ 0xD8, 0xCC, 0xE1, 0x26, 0x6A, 0x35, 0x3F, 0xCC, 0x20, 0xF3, 0x2D, 0x3B, 0x51, 0x7D, 0xE9, 0xC0 } //6.0.0
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};
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static const u8 cmac_keyseed[0x10] =
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{ 0x59, 0xC7, 0xFB, 0x6F, 0xBE, 0x9B, 0xBE, 0x87, 0x65, 0x6B, 0x15, 0xC0, 0x53, 0x73, 0x36, 0xA5 };
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static const u8 master_keyseed_retail[0x10] =
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{ 0xD8, 0xA2, 0x41, 0x0A, 0xC6, 0xC5, 0x90, 0x01, 0xC6, 0x1D, 0x6A, 0x26, 0x7C, 0x51, 0x3F, 0x3C };
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static const u8 console_keyseed[0x10] =
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{ 0x4F, 0x02, 0x5F, 0x0E, 0xB6, 0x6D, 0x11, 0x0E, 0xDC, 0x32, 0x7D, 0x41, 0x86, 0xC2, 0xF4, 0x78 };
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static const u8 package2_keyseed[] =
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{ 0xFB, 0x8B, 0x6A, 0x9C, 0x79, 0x00, 0xC8, 0x49, 0xEF, 0xD2, 0x4D, 0x85, 0x4D, 0x30, 0xA0, 0xC7 };
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static const u8 master_keyseed_4xx_5xx_610[0x10] =
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{ 0x2D, 0xC1, 0xF4, 0x8D, 0xF3, 0x5B, 0x69, 0x33, 0x42, 0x10, 0xAC, 0x65, 0xDA, 0x90, 0x46, 0x66 };
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static const u8 master_keyseed_620[0x10] =
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{ 0x37, 0x4B, 0x77, 0x29, 0x59, 0xB4, 0x04, 0x30, 0x81, 0xF6, 0xE5, 0x8C, 0x6D, 0x36, 0x17, 0x9A };
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static const u8 console_keyseed_4xx_5xx[0x10] =
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{ 0x0C, 0x91, 0x09, 0xDB, 0x93, 0x93, 0x07, 0x81, 0x07, 0x3C, 0xC4, 0x16, 0x22, 0x7C, 0x6C, 0x28 };
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static void _se_lock(bool lock_se)
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{
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if (lock_se)
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{
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for (u32 i = 0; i < 16; i++)
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se_key_acc_ctrl(i, 0x15);
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for (u32 i = 0; i < 2; i++)
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se_rsa_acc_ctrl(i, 1);
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SE(0x4) = 0; // Make this reg secure only.
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SE(SE_KEY_TABLE_ACCESS_LOCK_OFFSET) = 0; // Make all key access regs secure only.
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SE(SE_RSA_KEYTABLE_ACCESS_LOCK_OFFSET) = 0; // Make all RSA access regs secure only.
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SE(SE_SECURITY_0) &= 0xFFFFFFFB; // Make access lock regs secure only.
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}
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memset((void *)IPATCH_BASE, 0, 14 * sizeof(u32));
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SB(SB_CSR) = SB_CSR_PIROM_DISABLE;
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// This is useful for documenting the bits in the SE config registers, so we can keep it around.
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/*gfx_printf("SE(SE_SECURITY_0) = %08X\n", SE(SE_SECURITY_0));
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gfx_printf("SE(0x4) = %08X\n", SE(0x4));
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gfx_printf("SE(SE_KEY_TABLE_ACCESS_LOCK_OFFSET) = %08X\n", SE(SE_KEY_TABLE_ACCESS_LOCK_OFFSET));
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gfx_printf("SE(SE_RSA_KEYTABLE_ACCESS_LOCK_OFFSET) = %08X\n", SE(SE_RSA_KEYTABLE_ACCESS_LOCK_OFFSET));
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for(u32 i = 0; i < 16; i++)
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gfx_printf("%02X ", SE(SE_KEY_TABLE_ACCESS_REG_OFFSET + i * 4) & 0xFF);
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gfx_putc('\n');
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for(u32 i = 0; i < 2; i++)
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gfx_printf("%02X ", SE(SE_RSA_KEYTABLE_ACCESS_REG_OFFSET + i * 4) & 0xFF);
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gfx_putc('\n');
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gfx_hexdump(SE_BASE, (void *)SE_BASE, 0x400);*/
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}
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void _pmc_scratch_lock(u32 kb)
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{
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switch (kb)
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{
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case KB_FIRMWARE_VERSION_100_200:
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case KB_FIRMWARE_VERSION_300:
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case KB_FIRMWARE_VERSION_301:
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PMC(APBDEV_PMC_SEC_DISABLE) = 0x7FFFF3;
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PMC(APBDEV_PMC_SEC_DISABLE2) = 0xFFFFFFFF;
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PMC(APBDEV_PMC_SEC_DISABLE3) = 0xFFAFFFFF;
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PMC(APBDEV_PMC_SEC_DISABLE4) = 0xFFFFFFFF;
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PMC(APBDEV_PMC_SEC_DISABLE5) = 0xFFFFFFFF;
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PMC(APBDEV_PMC_SEC_DISABLE6) = 0xFFFFFFFF;
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PMC(APBDEV_PMC_SEC_DISABLE7) = 0xFFFFFFFF;
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PMC(APBDEV_PMC_SEC_DISABLE8) = 0xFFAAFFFF;
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break;
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default:
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PMC(APBDEV_PMC_SEC_DISABLE2) |= 0x3FCFFFF;
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PMC(APBDEV_PMC_SEC_DISABLE4) |= 0x3F3FFFFF;
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PMC(APBDEV_PMC_SEC_DISABLE5) = 0xFFFFFFFF;
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PMC(APBDEV_PMC_SEC_DISABLE6) |= 0xF3FFC00F;
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PMC(APBDEV_PMC_SEC_DISABLE7) |= 0x3FFFFF;
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PMC(APBDEV_PMC_SEC_DISABLE8) |= 0xFF;
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break;
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}
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}
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void _sysctr0_reset()
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{
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SYSCTR0(SYSCTR0_CNTCR) = 0;
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SYSCTR0(SYSCTR0_COUNTERID0) = 0;
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SYSCTR0(SYSCTR0_COUNTERID1) = 0;
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SYSCTR0(SYSCTR0_COUNTERID2) = 0;
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SYSCTR0(SYSCTR0_COUNTERID3) = 0;
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SYSCTR0(SYSCTR0_COUNTERID4) = 0;
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SYSCTR0(SYSCTR0_COUNTERID5) = 0;
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SYSCTR0(SYSCTR0_COUNTERID6) = 0;
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SYSCTR0(SYSCTR0_COUNTERID7) = 0;
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SYSCTR0(SYSCTR0_COUNTERID8) = 0;
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SYSCTR0(SYSCTR0_COUNTERID9) = 0;
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SYSCTR0(SYSCTR0_COUNTERID10) = 0;
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SYSCTR0(SYSCTR0_COUNTERID11) = 0;
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}
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int keygen(u8 *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt, launch_ctxt_t *hos_ctxt)
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{
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u8 tmp[0x20];
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u32 retries = 0;
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if (kb > KB_FIRMWARE_VERSION_MAX)
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return 0;
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if (kb <= KB_FIRMWARE_VERSION_600)
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tsec_ctxt->size = 0xF00;
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else if (kb == KB_FIRMWARE_VERSION_620)
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tsec_ctxt->size = 0x2900;
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else if (kb == KB_FIRMWARE_VERSION_700)
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tsec_ctxt->size = 0x3000;
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else
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tsec_ctxt->size = 0x3300;
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// Prepare smmu tsec page for 6.2.0.
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if (kb == KB_FIRMWARE_VERSION_620)
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{
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u8 *tsec_paged = (u8 *)page_alloc(3);
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memcpy(tsec_paged, (void *)tsec_ctxt->fw, tsec_ctxt->size);
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tsec_ctxt->fw = tsec_paged;
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}
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// Get TSEC key.
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if (kb <= KB_FIRMWARE_VERSION_620)
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{
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while (tsec_query(tmp, kb, tsec_ctxt) < 0)
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{
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memset(tmp, 0x00, 0x20);
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retries++;
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// We rely on racing conditions, make sure we cover even the unluckiest cases.
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if (retries > 15)
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{
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EHPRINTF("\nFailed to get TSEC keys. Please try again.\n");
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return 0;
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}
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}
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}
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if (kb >= KB_FIRMWARE_VERSION_700)
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se_aes_unwrap_key(8, 12, package2_keyseed);
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else if (kb == KB_FIRMWARE_VERSION_620)
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{
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// Set TSEC key.
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se_aes_key_set(12, tmp, 0x10);
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// Set TSEC root key.
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se_aes_key_set(13, tmp + 0x10, 0x10);
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if (!(emu_cfg.enabled && !h_cfg.emummc_force_disable) && hos_ctxt->stock)
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{
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// Package2 key.
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se_aes_key_set(8, tmp + 0x10, 0x10);
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se_aes_unwrap_key(8, 8, master_keyseed_620);
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se_aes_unwrap_key(8, 8, master_keyseed_retail);
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se_aes_unwrap_key(8, 8, package2_keyseed);
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}
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else
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{
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// Decrypt keyblob and set keyslots
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se_aes_crypt_block_ecb(12, 0, tmp + 0x20, keyblob_keyseeds[0]);
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se_aes_unwrap_key(15, 14, tmp + 0x20);
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se_aes_unwrap_key(14, 15, console_keyseed_4xx_5xx);
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se_aes_unwrap_key(15, 15, console_keyseed);
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se_aes_unwrap_key(13, 13, master_keyseed_620);
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se_aes_unwrap_key(12, 13, master_keyseed_retail);
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se_aes_unwrap_key(10, 13, master_keyseed_4xx_5xx_610);
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// Package2 key.
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se_aes_unwrap_key(8, 12, package2_keyseed);
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h_cfg.se_keygen_done = 1;
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}
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}
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else
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{
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se_key_acc_ctrl(13, 0x15);
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se_key_acc_ctrl(14, 0x15);
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// Set TSEC key.
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se_aes_key_set(13, tmp, 0x10);
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// Derive keyblob keys from TSEC+SBK.
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se_aes_crypt_block_ecb(13, 0, tmp, keyblob_keyseeds[0]);
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se_aes_unwrap_key(15, 14, tmp);
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se_aes_crypt_block_ecb(13, 0, tmp, keyblob_keyseeds[kb]);
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se_aes_unwrap_key(13, 14, tmp);
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// Clear SBK.
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se_aes_key_clear(14);
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//TODO: verify keyblob CMAC.
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//se_aes_unwrap_key(11, 13, cmac_keyseed);
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//se_aes_cmac(tmp, 0x10, 11, keyblob + 0x10, 0xA0);
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//if (!memcmp(keyblob, tmp, 0x10))
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// return 0;
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se_aes_crypt_block_ecb(13, 0, tmp, cmac_keyseed);
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se_aes_unwrap_key(11, 13, cmac_keyseed);
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// Decrypt keyblob and set keyslots.
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se_aes_crypt_ctr(13, keyblob + 0x20, 0x90, keyblob + 0x20, 0x90, keyblob + 0x10);
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se_aes_key_set(11, keyblob + 0x20 + 0x80, 0x10); // Package1 key.
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se_aes_key_set(12, keyblob + 0x20, 0x10);
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se_aes_key_set(13, keyblob + 0x20, 0x10);
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se_aes_crypt_block_ecb(12, 0, tmp, master_keyseed_retail);
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switch (kb)
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{
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case KB_FIRMWARE_VERSION_100_200:
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case KB_FIRMWARE_VERSION_300:
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case KB_FIRMWARE_VERSION_301:
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se_aes_unwrap_key(13, 15, console_keyseed);
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se_aes_unwrap_key(12, 12, master_keyseed_retail);
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break;
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case KB_FIRMWARE_VERSION_400:
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se_aes_unwrap_key(13, 15, console_keyseed_4xx_5xx);
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se_aes_unwrap_key(15, 15, console_keyseed);
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se_aes_unwrap_key(14, 12, master_keyseed_4xx_5xx_610);
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se_aes_unwrap_key(12, 12, master_keyseed_retail);
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break;
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case KB_FIRMWARE_VERSION_500:
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case KB_FIRMWARE_VERSION_600:
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se_aes_unwrap_key(10, 15, console_keyseed_4xx_5xx);
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se_aes_unwrap_key(15, 15, console_keyseed);
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se_aes_unwrap_key(14, 12, master_keyseed_4xx_5xx_610);
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se_aes_unwrap_key(12, 12, master_keyseed_retail);
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break;
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}
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// Package2 key.
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se_key_acc_ctrl(8, 0x15);
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se_aes_unwrap_key(8, 12, package2_keyseed);
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}
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return 1;
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}
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static int _read_emmc_pkg1(launch_ctxt_t *ctxt)
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{
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int res = 0;
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sdmmc_storage_t storage;
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sdmmc_t sdmmc;
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emummc_storage_init_mmc(&storage, &sdmmc);
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// Read package1.
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ctxt->pkg1 = (void *)malloc(0x40000);
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emummc_storage_set_mmc_partition(&storage, 1);
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emummc_storage_read(&storage, 0x100000 / NX_EMMC_BLOCKSIZE, 0x40000 / NX_EMMC_BLOCKSIZE, ctxt->pkg1);
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ctxt->pkg1_id = pkg1_identify(ctxt->pkg1);
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if (!ctxt->pkg1_id)
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{
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EHPRINTF("Unknown pkg1 version.");
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goto out;
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}
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gfx_printf("Identified pkg1 and Keyblob %d\n\n", ctxt->pkg1_id->kb);
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// Read the correct keyblob.
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ctxt->keyblob = (u8 *)calloc(NX_EMMC_BLOCKSIZE, 1);
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emummc_storage_read(&storage, 0x180000 / NX_EMMC_BLOCKSIZE + ctxt->pkg1_id->kb, 1, ctxt->keyblob);
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res = 1;
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out:;
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sdmmc_storage_end(&storage);
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return res;
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}
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static u8 *_read_emmc_pkg2(launch_ctxt_t *ctxt)
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{
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u8 *bctBuf = NULL;
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sdmmc_storage_t storage;
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sdmmc_t sdmmc;
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if (!emummc_storage_init_mmc(&storage, &sdmmc))
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return NULL;
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emummc_storage_set_mmc_partition(&storage, 0);
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// Parse eMMC GPT.
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LIST_INIT(gpt);
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nx_emmc_gpt_parse(&gpt, &storage);
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DPRINTF("Parsed GPT\n");
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// Find package2 partition.
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emmc_part_t *pkg2_part = nx_emmc_part_find(&gpt, "BCPKG2-1-Normal-Main");
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if (!pkg2_part)
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goto out;
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// Read in package2 header and get package2 real size.
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//TODO: implement memalign for DMA buffers.
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static const u32 BCT_SIZE = 0x4000;
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bctBuf = (u8 *)malloc(BCT_SIZE);
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nx_emmc_part_read(&storage, pkg2_part, BCT_SIZE / NX_EMMC_BLOCKSIZE, 1, bctBuf);
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u32 *hdr = (u32 *)(bctBuf + 0x100);
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u32 pkg2_size = hdr[0] ^ hdr[2] ^ hdr[3];
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DPRINTF("pkg2 size on emmc is %08X\n", pkg2_size);
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|
|
|
// Read in Boot Config.
|
|
memset(bctBuf, 0, BCT_SIZE);
|
|
nx_emmc_part_read(&storage, pkg2_part, 0, BCT_SIZE / NX_EMMC_BLOCKSIZE, bctBuf);
|
|
|
|
// Read in package2.
|
|
u32 pkg2_size_aligned = ALIGN(pkg2_size, NX_EMMC_BLOCKSIZE);
|
|
DPRINTF("pkg2 size aligned is %08X\n", pkg2_size_aligned);
|
|
ctxt->pkg2 = malloc(pkg2_size_aligned);
|
|
ctxt->pkg2_size = pkg2_size;
|
|
nx_emmc_part_read(&storage, pkg2_part, BCT_SIZE / NX_EMMC_BLOCKSIZE,
|
|
pkg2_size_aligned / NX_EMMC_BLOCKSIZE, ctxt->pkg2);
|
|
out:;
|
|
nx_emmc_gpt_free(&gpt);
|
|
sdmmc_storage_end(&storage);
|
|
|
|
return bctBuf;
|
|
}
|
|
|
|
static void _free_launch_components(launch_ctxt_t *ctxt)
|
|
{
|
|
free(ctxt->keyblob);
|
|
free(ctxt->pkg1);
|
|
free(ctxt->pkg2);
|
|
free(ctxt->warmboot);
|
|
free(ctxt->secmon);
|
|
free(ctxt->kernel);
|
|
free(ctxt->kip1_patches);
|
|
}
|
|
|
|
int hos_launch(ini_sec_t *cfg)
|
|
{
|
|
minerva_change_freq(FREQ_1600);
|
|
launch_ctxt_t ctxt;
|
|
tsec_ctxt_t tsec_ctxt;
|
|
volatile secmon_mailbox_t *secmon_mb;
|
|
|
|
memset(&ctxt, 0, sizeof(launch_ctxt_t));
|
|
memset(&tsec_ctxt, 0, sizeof(tsec_ctxt_t));
|
|
list_init(&ctxt.kip1_list);
|
|
|
|
ctxt.cfg = cfg;
|
|
|
|
if (!gfx_con.mute)
|
|
gfx_clear_grey(0x1B);
|
|
gfx_con_setpos(0, 0);
|
|
|
|
gfx_printf("Initializing...\n\n");
|
|
|
|
// Read package1 and the correct keyblob.
|
|
if (!_read_emmc_pkg1(&ctxt))
|
|
return 0;
|
|
|
|
// Try to parse config if present.
|
|
if (ctxt.cfg && !parse_boot_config(&ctxt))
|
|
{
|
|
EHPRINTF("Wrong ini cfg or missing files!");
|
|
return 0;
|
|
}
|
|
|
|
// Enable emummc patching.
|
|
if (emu_cfg.enabled && !h_cfg.emummc_force_disable)
|
|
{
|
|
if (ctxt.stock)
|
|
{
|
|
EHPRINTF("Stock emuMMC is not supported yet!");
|
|
return 0;
|
|
}
|
|
|
|
ctxt.atmosphere = true; // Set atmosphere patching in case of Stock emuMMC and no fss0.
|
|
config_kip1patch(&ctxt, "emummc");
|
|
}
|
|
|
|
// Check if fuses lower than 4.0.0 and if yes apply NO Gamecard patch.
|
|
if (h_cfg.autonogc && !(fuse_read_odm(7) & ~0xF) && ctxt.pkg1_id->kb >= KB_FIRMWARE_VERSION_400)
|
|
config_kip1patch(&ctxt, "nogc");
|
|
|
|
gfx_printf("Loaded pkg1 & keyblob\n");
|
|
|
|
// Generate keys.
|
|
if (!h_cfg.se_keygen_done)
|
|
{
|
|
tsec_ctxt.fw = (u8 *)ctxt.pkg1 + ctxt.pkg1_id->tsec_off;
|
|
tsec_ctxt.pkg1 = ctxt.pkg1;
|
|
tsec_ctxt.pkg11_off = ctxt.pkg1_id->pkg11_off;
|
|
tsec_ctxt.secmon_base = ctxt.pkg1_id->secmon_base;
|
|
|
|
if (ctxt.pkg1_id->kb >= KB_FIRMWARE_VERSION_700 && !h_cfg.sept_run)
|
|
{
|
|
gfx_printf("Failed to run sept\n");
|
|
return 0;
|
|
}
|
|
|
|
if (!keygen(ctxt.keyblob, ctxt.pkg1_id->kb, &tsec_ctxt, &ctxt))
|
|
return 0;
|
|
DPRINTF("Generated keys\n");
|
|
if (ctxt.pkg1_id->kb <= KB_FIRMWARE_VERSION_600)
|
|
h_cfg.se_keygen_done = 1;
|
|
}
|
|
|
|
// Decrypt and unpack package1 if we require parts of it.
|
|
if (!ctxt.warmboot || !ctxt.secmon)
|
|
{
|
|
if (ctxt.pkg1_id->kb <= KB_FIRMWARE_VERSION_600)
|
|
pkg1_decrypt(ctxt.pkg1_id, ctxt.pkg1);
|
|
|
|
if (ctxt.pkg1_id->kb <= KB_FIRMWARE_VERSION_620 && !(emu_cfg.enabled && !h_cfg.emummc_force_disable))
|
|
{
|
|
pkg1_unpack((void *)ctxt.pkg1_id->warmboot_base, (void *)ctxt.pkg1_id->secmon_base, NULL, ctxt.pkg1_id, ctxt.pkg1);
|
|
gfx_printf("Decrypted & unpacked pkg1\n");
|
|
}
|
|
else
|
|
{
|
|
EHPRINTF("No mandatory secmon or warmboot provided!");
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
// Replace 'warmboot.bin' if requested.
|
|
if (ctxt.warmboot)
|
|
memcpy((void *)ctxt.pkg1_id->warmboot_base, ctxt.warmboot, ctxt.warmboot_size);
|
|
else
|
|
{
|
|
if (ctxt.pkg1_id->kb >= KB_FIRMWARE_VERSION_700)
|
|
{
|
|
EHPRINTF("No warmboot provided!");
|
|
return 0;
|
|
}
|
|
// Else we patch it to allow downgrading.
|
|
patch_t *warmboot_patchset = ctxt.pkg1_id->warmboot_patchset;
|
|
gfx_printf("%kPatching Warmboot%k\n", 0xFFFFBA00, 0xFFCCCCCC);
|
|
for (u32 i = 0; warmboot_patchset[i].off != 0xFFFFFFFF; i++)
|
|
*(vu32 *)(ctxt.pkg1_id->warmboot_base + warmboot_patchset[i].off) = warmboot_patchset[i].val;
|
|
}
|
|
// Set warmboot address in PMC if required.
|
|
if (ctxt.pkg1_id->set_warmboot)
|
|
PMC(APBDEV_PMC_SCRATCH1) = ctxt.pkg1_id->warmboot_base;
|
|
|
|
// Replace 'SecureMonitor' if requested.
|
|
if (ctxt.secmon)
|
|
memcpy((void *)ctxt.pkg1_id->secmon_base, ctxt.secmon, ctxt.secmon_size);
|
|
else if (ctxt.pkg1_id->secmon_patchset)
|
|
{
|
|
// Else we patch it to allow for an unsigned package2 and patched kernel.
|
|
patch_t *secmon_patchset = ctxt.pkg1_id->secmon_patchset;
|
|
gfx_printf("%kPatching Security Monitor%k\n", 0xFFFFBA00, 0xFFCCCCCC);
|
|
for (u32 i = 0; secmon_patchset[i].off != 0xFFFFFFFF; i++)
|
|
*(vu32 *)(ctxt.pkg1_id->secmon_base + secmon_patchset[i].off) = secmon_patchset[i].val;
|
|
}
|
|
|
|
gfx_printf("Loaded warmboot and secmon\n");
|
|
|
|
// Read package2.
|
|
u8 *bootConfigBuf = _read_emmc_pkg2(&ctxt);
|
|
if (!bootConfigBuf)
|
|
return 0;
|
|
|
|
gfx_printf("Read pkg2\n");
|
|
|
|
// Decrypt package2 and parse KIP1 blobs in INI1 section.
|
|
pkg2_hdr_t *pkg2_hdr = pkg2_decrypt(ctxt.pkg2);
|
|
if (!pkg2_hdr)
|
|
{
|
|
gfx_printf("Pkg2 decryption failed!\n");
|
|
return 0;
|
|
}
|
|
|
|
LIST_INIT(kip1_info);
|
|
pkg2_parse_kips(&kip1_info, pkg2_hdr, &ctxt.new_pkg2);
|
|
|
|
gfx_printf("Parsed ini1\n");
|
|
|
|
// Use the kernel included in package2 in case we didn't load one already.
|
|
if (!ctxt.kernel)
|
|
{
|
|
ctxt.kernel = pkg2_hdr->data;
|
|
ctxt.kernel_size = pkg2_hdr->sec_size[PKG2_SEC_KERNEL];
|
|
|
|
if (!ctxt.stock && (ctxt.svcperm || ctxt.debugmode || ctxt.atmosphere))
|
|
{
|
|
u8 kernel_hash[0x20];
|
|
// Hash only Kernel when it embeds INI1.
|
|
if (!ctxt.new_pkg2)
|
|
se_calc_sha256(kernel_hash, ctxt.kernel, ctxt.kernel_size);
|
|
else
|
|
se_calc_sha256(kernel_hash, ctxt.kernel + PKG2_NEWKERN_START,
|
|
*(u32 *)(ctxt.kernel + PKG2_NEWKERN_INI1_START) - PKG2_NEWKERN_START);
|
|
|
|
ctxt.pkg2_kernel_id = pkg2_identify(kernel_hash);
|
|
if (!ctxt.pkg2_kernel_id)
|
|
{
|
|
EHPRINTF("Failed to identify kernel!");
|
|
return 0;
|
|
}
|
|
|
|
|
|
// In case a kernel patch option is set; allows to disable SVC verification or/and enable debug mode.
|
|
kernel_patch_t *kernel_patchset = ctxt.pkg2_kernel_id->kernel_patchset;
|
|
if (kernel_patchset != NULL)
|
|
{
|
|
gfx_printf("%kPatching kernel%k\n", 0xFFFFBA00, 0xFFCCCCCC);
|
|
u32 *temp;
|
|
for (u32 i = 0; kernel_patchset[i].id != 0xFFFFFFFF; i++)
|
|
{
|
|
if ((ctxt.svcperm && kernel_patchset[i].id == SVC_VERIFY_DS)
|
|
|| (ctxt.debugmode && kernel_patchset[i].id == DEBUG_MODE_EN && !(ctxt.atmosphere && ctxt.secmon))
|
|
|| (ctxt.atmosphere && kernel_patchset[i].id == ATM_GEN_PATCH))
|
|
*(vu32 *)(ctxt.kernel + kernel_patchset[i].off) = kernel_patchset[i].val;
|
|
else if (ctxt.atmosphere && kernel_patchset[i].id == ATM_ARR_PATCH)
|
|
{
|
|
temp = (u32 *)kernel_patchset[i].ptr;
|
|
for (u32 j = 0; j < kernel_patchset[i].val; j++)
|
|
*(vu32 *)(ctxt.kernel + kernel_patchset[i].off + (j << 2)) = temp[j];
|
|
}
|
|
else if (kernel_patchset[i].id < SVC_VERIFY_DS)
|
|
*(vu32 *)(ctxt.kernel + kernel_patchset[i].off) = kernel_patchset[i].val;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// Merge extra KIP1s into loaded ones.
|
|
gfx_printf("%kPatching kips%k\n", 0xFFFFBA00, 0xFFCCCCCC);
|
|
LIST_FOREACH_ENTRY(merge_kip_t, mki, &ctxt.kip1_list, link)
|
|
pkg2_merge_kip(&kip1_info, (pkg2_kip1_t *)mki->kip1);
|
|
|
|
// Patch kip1s in memory if needed.
|
|
const char* unappliedPatch = pkg2_patch_kips(&kip1_info, ctxt.kip1_patches);
|
|
if (unappliedPatch != NULL)
|
|
{
|
|
EHPRINTFARGS("Failed to apply '%s'!", unappliedPatch);
|
|
sd_unmount(); // Just exiting is not enough until pkg2_patch_kips stops modifying the string passed into it.
|
|
|
|
_free_launch_components(&ctxt);
|
|
return 0; // MUST stop here, because if user requests 'nogc' but it's not applied, their GC controller gets updated!
|
|
}
|
|
|
|
// Rebuild and encrypt package2.
|
|
pkg2_build_encrypt((void *)PKG2_LOAD_ADDR, ctxt.kernel, ctxt.kernel_size, &kip1_info, ctxt.new_pkg2);
|
|
|
|
gfx_printf("Rebuilt & loaded pkg2\n");
|
|
|
|
// Unmount SD card.
|
|
sd_unmount();
|
|
|
|
gfx_printf("\n%kBooting...%k\n", 0xFF96FF00, 0xFFCCCCCC);
|
|
|
|
// Clear pkg1/pkg2 keys.
|
|
se_aes_key_clear(8);
|
|
se_aes_key_clear(11);
|
|
|
|
// Finalize per firmware keys.
|
|
int bootStateDramPkg2 = 0;
|
|
int bootStatePkg2Continue = 0;
|
|
|
|
switch (ctxt.pkg1_id->kb)
|
|
{
|
|
case KB_FIRMWARE_VERSION_100_200:
|
|
case KB_FIRMWARE_VERSION_300:
|
|
case KB_FIRMWARE_VERSION_301:
|
|
if (ctxt.pkg1_id->kb == KB_FIRMWARE_VERSION_300)
|
|
PMC(APBDEV_PMC_SECURE_SCRATCH32) = 0xE3; // Warmboot 3.0.0 PA address id.
|
|
else if (ctxt.pkg1_id->kb == KB_FIRMWARE_VERSION_301)
|
|
PMC(APBDEV_PMC_SECURE_SCRATCH32) = 0x104; // Warmboot 3.0.1/.2 PA address id.
|
|
se_key_acc_ctrl(12, 0xFF);
|
|
se_key_acc_ctrl(13, 0xFF);
|
|
bootStateDramPkg2 = 2;
|
|
bootStatePkg2Continue = 3;
|
|
break;
|
|
case KB_FIRMWARE_VERSION_400:
|
|
case KB_FIRMWARE_VERSION_500:
|
|
case KB_FIRMWARE_VERSION_600:
|
|
se_key_acc_ctrl(12, 0xFF);
|
|
se_key_acc_ctrl(15, 0xFF);
|
|
default:
|
|
bootStateDramPkg2 = 2;
|
|
bootStatePkg2Continue = 4;
|
|
break;
|
|
}
|
|
|
|
// Clear BCT area for retail units and copy it over if dev unit.
|
|
if (ctxt.pkg1_id->kb <= KB_FIRMWARE_VERSION_500)
|
|
{
|
|
memset((void *)0x4003D000, 0, 0x3000);
|
|
if ((fuse_read_odm(4) & 3) == 3)
|
|
memcpy((void *)0x4003D000, bootConfigBuf, 0x1000);
|
|
}
|
|
else
|
|
{
|
|
memset((void *)0x4003F000, 0, 0x1000);
|
|
if ((fuse_read_odm(4) & 3) == 3)
|
|
memcpy((void *)0x4003F800, bootConfigBuf, 0x800);
|
|
}
|
|
free(bootConfigBuf);
|
|
|
|
// Config Exosphère if booting full Atmosphère.
|
|
if (ctxt.atmosphere && ctxt.secmon)
|
|
config_exosphere(&ctxt);
|
|
|
|
// Finalize MC carveout.
|
|
if (ctxt.pkg1_id->kb <= KB_FIRMWARE_VERSION_301)
|
|
mc_config_carveout();
|
|
|
|
// Lock SE before starting 'SecureMonitor' if < 6.2.0, otherwise lock bootrom and ipatches.
|
|
_se_lock(ctxt.pkg1_id->kb <= KB_FIRMWARE_VERSION_600);
|
|
|
|
// Reset sysctr0 counters.
|
|
if (ctxt.pkg1_id->kb >= KB_FIRMWARE_VERSION_620)
|
|
_sysctr0_reset();
|
|
|
|
// < 4.0.0 pkg1.1 locks PMC scratches.
|
|
//_pmc_scratch_lock(ctxt.pkg1_id->kb);
|
|
|
|
// Set secmon mailbox address.
|
|
if (ctxt.pkg1_id->kb >= KB_FIRMWARE_VERSION_700)
|
|
secmon_mb = (secmon_mailbox_t *)SECMON7_MB_ADDR;
|
|
else
|
|
secmon_mb = (secmon_mailbox_t *)SECMON_MB_ADDR;
|
|
|
|
// Start from DRAM ready signal and reset outgoing value.
|
|
secmon_mb->in = bootStateDramPkg2;
|
|
secmon_mb->out = 0;
|
|
|
|
// Free allocated memory.
|
|
_free_launch_components(&ctxt);
|
|
|
|
// Disable display. This must be executed before secmon to provide support for all fw versions.
|
|
display_end();
|
|
|
|
// Clear EMC_SCRATCH0.
|
|
EMC(EMC_SCRATCH0) = 0;
|
|
|
|
// Flush cache and disable MMU.
|
|
bpmp_mmu_disable();
|
|
bpmp_clk_rate_set(BPMP_CLK_NORMAL);
|
|
minerva_change_freq(FREQ_800);
|
|
|
|
// emuMMC: Some cards (Sandisk U1), do not like a fast power cycle. Wait min 100ms.
|
|
sdmmc_storage_init_wait_sd();
|
|
|
|
// Wait for secmon to get ready.
|
|
if (smmu_is_used())
|
|
smmu_exit();
|
|
else
|
|
cluster_boot_cpu0(ctxt.pkg1_id->secmon_base);
|
|
while (!secmon_mb->out)
|
|
; // A usleep(1) only works when in IRAM or with a trained DRAM.
|
|
|
|
// Signal pkg2 ready and continue boot.
|
|
secmon_mb->in = bootStatePkg2Continue;
|
|
|
|
// Halt ourselves in waitevent state and resume if there's JTAG activity.
|
|
while (true)
|
|
bpmp_halt();
|
|
|
|
return 0;
|
|
}
|