mirror of
https://github.com/CTCaer/hekate
synced 2024-07-03 15:03:29 +00:00
66c4f30bdf
Additionally remove support for DRAM types that Switch platform does not have. This will reduce periodic training cost to 30us from 6ms.
630 lines
27 KiB
C
630 lines
27 KiB
C
/*
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* Minerva Training Cell
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* DRAM Training for Tegra X1 SoC. Supports DDR2/3 and LPDDR3/4.
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*
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* Copyright (c) 2018 CTCaer <ctcaer@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _MTC_MC_EMC_REGS_H_
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#define _MTC_MC_EMC_REGS_H_
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/* Clock controller registers */
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#define CLK_RST_CONTROLLER_PLLM_BASE 0x90
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#define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C
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#define PLLM_ENABLE (1 << 30)
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#define PLLM_LOCK (1 << 27)
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#define PLLM_EN_LCKDET (1 << 4)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C
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#define EMC_2X_CLK_SRC_SHIFT 29
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X 0x280
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#define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284
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#define CLK_RST_CONTROLLER_CLK_ENB_X_CLR 0x288
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#define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E8
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x664
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#define EMC_DLL_PLLM_VCOB (1 << 10)
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#define EMC_DLL_SWITCH_OUT (1 << 11)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE 0x724
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/* Memory controller registers */
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#define MC_EMEM_ADR_CFG 0x54
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#define MC_EMEM_ARB_CFG 0x90
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#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
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#define MC_EMEM_ARB_TIMING_RCD 0x98
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#define MC_EMEM_ARB_TIMING_RP 0x9C
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#define MC_EMEM_ARB_TIMING_RC 0xA0
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#define MC_EMEM_ARB_TIMING_RAS 0xA4
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#define MC_EMEM_ARB_TIMING_FAW 0xA8
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#define MC_EMEM_ARB_TIMING_RRD 0xAC
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#define MC_EMEM_ARB_TIMING_RAP2PRE 0xB0
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#define MC_EMEM_ARB_TIMING_WAP2PRE 0xB4
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#define MC_EMEM_ARB_TIMING_R2R 0xB8
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#define MC_EMEM_ARB_TIMING_W2W 0xBC
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#define MC_EMEM_ARB_TIMING_R2W 0xC0
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#define MC_EMEM_ARB_TIMING_W2R 0xC4
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#define MC_EMEM_ARB_MISC2 0xC8
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#define MC_EMEM_ARB_DA_TURNS 0xD0
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#define MC_EMEM_ARB_DA_COVERS 0xD4
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#define MC_EMEM_ARB_MISC0 0xD8
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#define MC_EMEM_ARB_MISC1 0xDC
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#define MC_EMEM_ARB_RING1_THROTTLE 0xE0
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#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2E4
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#define MC_LATENCY_ALLOWANCE_HC_0 0x310
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#define MC_LATENCY_ALLOWANCE_HC_1 0x314
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#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
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#define MC_LATENCY_ALLOWANCE_NVENC_0 0x328
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#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
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#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
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#define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
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#define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
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#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37C
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#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380
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#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390
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#define MC_LATENCY_ALLOWANCE_VIC_0 0x394
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#define MC_LATENCY_ALLOWANCE_VI2_0 0x398
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#define MC_LATENCY_ALLOWANCE_GPU_0 0x3AC
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#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3B8
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#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3BC
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#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3C0
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#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3C4
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#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3D8
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#define MC_LATENCY_ALLOWANCE_GPU2_0 0x3E8
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#define MC_MLL_MPCORER_PTSA_RATE 0x44C
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#define MC_FTOP_PTSA_RATE 0x50C
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#define MC_EMEM_ARB_TIMING_RFCPB 0x6C0
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#define MC_EMEM_ARB_TIMING_CCDMW 0x6C4
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#define MC_EMEM_ARB_REFPB_HP_CTRL 0x6F0
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#define MC_EMEM_ARB_REFPB_BANK_CTRL 0x6F4
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#define MC_PTSA_GRANT_DECREMENT 0x960
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#define MC_EMEM_ARB_DHYST_CTRL 0xBCC
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xBD0
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xBD4
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xBD8
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xBDC
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xBE0
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xBE4
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xBE8
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xBEC
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/* External Memory controller registers */
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#define EMC_INTSTATUS 0x0
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#define CLKCHANGE_COMPLETE_INT (1 << 4)
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#define EMC_DBG 0x8
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#define EMC_CFG 0xC
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#define EMC_PIN 0x24
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#define EMC_TIMING_CONTROL 0x28
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#define EMC_RC 0x2C
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#define EMC_RFC 0x30
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#define EMC_RAS 0x34
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#define EMC_RP 0x38
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#define EMC_R2W 0x3C
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#define EMC_W2R 0x40
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#define EMC_R2P 0x44
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#define EMC_W2P 0x48
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#define EMC_RD_RCD 0x4C
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#define EMC_WR_RCD 0x50
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#define EMC_RRD 0x54
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#define EMC_REXT 0x58
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#define EMC_WDV 0x5C
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#define EMC_QUSE 0x60
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#define EMC_QRST 0x64
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#define EMC_QSAFE 0x68
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#define EMC_RDV 0x6C
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#define EMC_REFRESH 0x70
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#define EMC_BURST_REFRESH_NUM 0x74
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#define EMC_PDEX2WR 0x78
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#define EMC_PDEX2RD 0x7C
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#define EMC_PCHG2PDEN 0x80
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#define EMC_ACT2PDEN 0x84
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#define EMC_AR2PDEN 0x88
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#define EMC_RW2PDEN 0x8C
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#define EMC_TXSR 0x90
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#define EMC_TCKE 0x94
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#define EMC_TFAW 0x98
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#define EMC_TRPAB 0x9C
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#define EMC_TCLKSTABLE 0xA0
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#define EMC_TCLKSTOP 0xA4
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#define EMC_TREFBW 0xA8
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#define EMC_TPPD 0xAC
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#define EMC_ODT_WRITE 0xB0
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#define EMC_PDEX2MRR 0xB4
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#define EMC_WEXT 0xB8
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#define EMC_RFC_SLR 0xC0
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#define EMC_MRS_WAIT_CNT2 0xC4
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#define EMC_MRS_WAIT_CNT 0xC8
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#define EMC_MRS 0xCC
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#define EMC_EMRS 0xD0
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#define EMC_REF 0xD4
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#define EMC_MRW 0xE8
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#define EMC_SELF_REF 0xE0
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#define EMC_MRR 0xEC
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#define EMC_FBIO_SPARE 0x100
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#define EMC_FBIO_CFG5 0x104
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#define EMC_PDEX2CKE 0x118
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#define EMC_CKE2PDEN 0x11C
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#define EMC_MPC 0x128
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#define EMC_EMRS2 0x12C
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#define EMC_MRW2 0x134
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#define EMC_MRW3 0x138
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#define EMC_MRW4 0x13C
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#define EMC_R2R 0x144
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#define EMC_EINPUT 0x14C
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#define EMC_EINPUT_DURATION 0x150
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#define EMC_PUTERM_EXTRA 0x154
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#define EMC_TCKESR 0x158
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#define EMC_TPD 0x15C
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#define EMC_AUTO_CAL_CONFIG 0x2A4
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#define EMC_EMC_STATUS 0x2B4
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#define TIMING_UPDATE_STALLED (1 << 23)
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#define MRR_DIVLD (1 << 20)
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#define IN_SELF_REFRESH_MASK (3 << 8)
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#define IN_POWERDOWN_MASK (3 << 4)
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#define REQ_FIFO_EMPTY (1 << 0)
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#define EMC_CFG_2 0x2B8
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#define EMC_CFG_DIG_DLL 0x2BC
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#define EMC_CFG_DIG_DLL_PERIOD 0x2C0
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#define EMC_DIG_DLL_STATUS 0x2C4
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#define EMC_RDV_MASK 0x2CC
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#define EMC_WDV_MASK 0x2D0
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#define EMC_RDV_EARLY_MASK 0x2D4
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#define EMC_RDV_EARLY 0x2D8
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#define EMC_AUTO_CAL_CONFIG8 0x2DC
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#define EMC_ZCAL_INTERVAL 0x2E0
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#define EMC_ZCAL_WAIT_CNT 0x2E4
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#define EMC_ZQ_CAL 0x2EC
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#define EMC_FDPD_CTRL_DQ 0x310
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#define EMC_FDPD_CTRL_CMD 0x314
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#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD 0x318
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#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD 0x31C
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#define EMC_SCRATCH0 0x324
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#define EMC_PMACRO_BRICK_CTRL_RFU1 0x330
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#define EMC_PMACRO_BRICK_CTRL_RFU2 0x334
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#define EMC_TR_TIMING_0 0x3B4
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#define EMC_TR_CTRL_0 0x3B8
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#define EMC_TR_CTRL_1 0x3BC
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#define EMC_SWITCH_BACK_CTRL 0x3C0
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#define EMC_TR_RDV 0x3C4
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#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3CC
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#define EMC_SEL_DPD_CTRL 0x3D8
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#define EMC_PRE_REFRESH_REQ_CNT 0x3DC
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#define EMC_DYN_SELF_REF_CONTROL 0x3E0
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#define EMC_TXSRDLL 0x3E4
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#define EMC_CCFIFO_ADDR 0x3E8
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#define EMC_CCFIFO_DATA 0x3EC
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#define EMC_CCFIFO_STATUS 0x3F0
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#define EMC_TR_QPOP 0x3F4
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#define EMC_TR_RDV_MASK 0x3F8
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#define EMC_TR_QSAFE 0x3FC
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#define EMC_TR_QRST 0x400
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#define EMC_AUTO_CAL_CONFIG2 0x458
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#define EMC_AUTO_CAL_CONFIG3 0x45C
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#define EMC_TR_DVFS 0x460
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#define EMC_AUTO_CAL_CHANNEL 0x464
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#define EMC_IBDLY 0x468
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#define EMC_OBDLY 0x46c
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#define EMC_TXDSRVTTGEN 0x480
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#define EMC_WE_DURATION 0x48C
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#define EMC_WS_DURATION 0x490
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#define EMC_WEV 0x494
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#define EMC_WSV 0x498
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#define EMC_CFG_3 0x49C
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#define EMC_MRW6 0x4A4
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#define EMC_MRW7 0x4A8
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#define EMC_MRW8 0x4AC
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#define EMC_MRW14 0x4C4
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#define EMC_MRW15 0x4D0
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#define EMC_CFG_SYNC 0x4D4
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#define EMC_FDPD_CTRL_CMD_NO_RAMP 0x4D8
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#define EMC_WDV_CHK 0x4E0
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#define EMC_CFG_PIPE_2 0x554
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#define EMC_CFG_PIPE_CLK 0x558
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#define EMC_CFG_PIPE_1 0x55C
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#define EMC_CFG_PIPE 0x560
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#define EMC_QPOP 0x564
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#define EMC_QUSE_WIDTH 0x568
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#define EMC_PUTERM_WIDTH 0x56C
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#define EMC_AUTO_CAL_CONFIG7 0x574
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#define EMC_REFCTRL2 0x580
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#define EMC_FBIO_CFG7 0x584
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#define EMC_DATA_BRLSHFT_0 0x588
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#define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT 0
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#define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT 3
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#define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT 6
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#define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT 9
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#define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT 12
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#define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT 15
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#define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT 18
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#define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT 21
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#define EMC_DATA_BRLSHFT_1 0x58C
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#define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT 0
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#define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT 3
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#define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT 6
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#define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT 9
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#define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT 12
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#define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT 15
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#define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT 18
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#define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT 21
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#define EMC_RFCPB 0x590
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#define EMC_DQS_BRLSHFT_0 0x594
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#define EMC_DQS_BRLSHFT_1 0x598
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#define EMC_CMD_BRLSHFT_0 0x59C
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#define EMC_CMD_BRLSHFT_1 0x5A0
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#define EMC_CMD_BRLSHFT_2 0x5A4
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#define EMC_CMD_BRLSHFT_3 0x5A8
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#define EMC_QUSE_BRLSHFT_0 0x5AC
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#define EMC_AUTO_CAL_CONFIG4 0x5B0
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#define EMC_AUTO_CAL_CONFIG5 0x5B4
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#define EMC_QUSE_BRLSHFT_1 0x5B8
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#define EMC_QUSE_BRLSHFT_2 0x5BC
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#define EMC_CCDMW 0x5C0
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#define EMC_QUSE_BRLSHFT_3 0x5C4
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#define EMC_AUTO_CAL_CONFIG6 0x5CC
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#define EMC_DLL_CFG_0 0x5E4
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#define EMC_DLL_CFG_1 0x5E8
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#define EMC_CONFIG_SAMPLE_DELAY 0x5F0
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#define EMC_CFG_UPDATE 0x5F4
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#define EMC_PMACRO_QUSE_DDLL_RANK0_0 0x600
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#define EMC_PMACRO_QUSE_DDLL_RANK0_1 0x604
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#define EMC_PMACRO_QUSE_DDLL_RANK0_2 0x608
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#define EMC_PMACRO_QUSE_DDLL_RANK0_3 0x60C
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#define EMC_PMACRO_QUSE_DDLL_RANK0_4 0x610
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#define EMC_PMACRO_QUSE_DDLL_RANK0_5 0x614
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#define EMC_PMACRO_QUSE_DDLL_RANK1_4 0x630
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#define EMC_PMACRO_QUSE_DDLL_RANK1_5 0x634
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#define EMC_PMACRO_QUSE_DDLL_RANK1_0 0x620
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#define EMC_PMACRO_QUSE_DDLL_RANK1_1 0x624
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#define EMC_PMACRO_QUSE_DDLL_RANK1_2 0x628
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#define EMC_PMACRO_QUSE_DDLL_RANK1_3 0x62C
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 0x640
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 0x644
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 0x648
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 0x64C
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 0x650
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 0x654
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 0x660
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 0x664
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 0x668
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 0x66C
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4 0x670
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5 0x674
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0 0x680
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1 0x684
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2 0x688
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3 0x68C
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4 0x690
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5 0x694
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0 0x6A0
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1 0x6A4
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2 0x6A8
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3 0x6AC
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4 0x6B0
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#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5 0x6B4
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0 0x6C0
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1 0x6C4
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2 0x6C8
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3 0x6CC
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0 0x6E0
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1 0x6E4
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2 0x6E8
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#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3 0x6EC
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#define EMC_PMACRO_TX_PWRD_0 0x720
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#define EMC_PMACRO_TX_PWRD_1 0x724
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#define EMC_PMACRO_TX_PWRD_2 0x728
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#define EMC_PMACRO_TX_PWRD_3 0x72C
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#define EMC_PMACRO_TX_PWRD_4 0x730
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#define EMC_PMACRO_TX_PWRD_5 0x734
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#define EMC_PMACRO_TX_SEL_CLK_SRC_0 0x740
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#define EMC_PMACRO_TX_SEL_CLK_SRC_1 0x744
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#define EMC_PMACRO_TX_SEL_CLK_SRC_3 0x74C
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#define EMC_PMACRO_TX_SEL_CLK_SRC_2 0x748
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#define EMC_PMACRO_TX_SEL_CLK_SRC_4 0x750
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#define EMC_PMACRO_TX_SEL_CLK_SRC_5 0x754
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#define EMC_PMACRO_DDLL_BYPASS 0x760
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#define EMC_PMACRO_DDLL_PWRD_0 0x770
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#define EMC_PMACRO_DDLL_PWRD_1 0x774
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#define EMC_PMACRO_DDLL_PWRD_2 0x778
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#define EMC_PMACRO_CMD_CTRL_0 0x780
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#define EMC_PMACRO_CMD_CTRL_1 0x784
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#define EMC_PMACRO_CMD_CTRL_2 0x788
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0x800
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0x804
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0x808
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 0x80C
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0x810
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0x814
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0x818
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 0x81C
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0x820
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0x824
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0x828
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 0x82C
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0x830
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0x834
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0x838
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 0x83C
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0x840
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0x844
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0x848
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 0x84C
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0x850
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0x854
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0x858
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 0x85C
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0x860
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0x864
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0x868
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 0x86C
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0x870
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0x874
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0x878
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 0x87C
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 0x880
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 0x884
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 0x888
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3 0x88C
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 0x890
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 0x894
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 0x898
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3 0x89C
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 0x8A0
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 0x8A4
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 0x8A8
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3 0x8AC
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 0x8B0
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 0x8B4
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 0x8B8
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3 0x8BC
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0x900
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0x904
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0x908
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 0x90C
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0x910
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0x914
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0x918
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 0x91C
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0x920
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0x924
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0x928
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 0x92C
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0x930
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0x934
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0x938
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 0x93C
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0x940
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0x944
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0x948
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 0x94C
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0x950
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0x954
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0x958
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 0x95C
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0x960
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0x964
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0x968
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 0x96C
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0x970
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0x974
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0x978
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 0x97C
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0 0x980
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1 0x984
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2 0x988
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3 0x98C
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0 0x990
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1 0x994
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2 0x998
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3 0x99C
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0 0x9A0
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1 0x9A4
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2 0x9A8
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3 0x9AC
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0 0x9B0
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1 0x9B4
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2 0x9B8
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#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3 0x9BC
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0xA00
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0xA04
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0xA08
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0xA10
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0xA14
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0xA18
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0xA20
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0xA24
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0xA28
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0xA30
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0xA34
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0xA38
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0xA40
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0xA44
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0xA48
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0xA50
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0xA54
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0xA58
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0xA60
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0xA64
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0xA68
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0xA70
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0xA74
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0xA78
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0xB00
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0xB04
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0xB08
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0xB10
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0xB14
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0xB18
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0xB20
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0xB24
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0xB28
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0xB30
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0xB34
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0xB38
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0xB40
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0xB44
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0xB48
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0xB50
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0xB54
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0xB58
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0xB60
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0xB64
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0xB68
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0xB70
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0xB74
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#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0xB78
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#define EMC_PMACRO_IB_VREF_DQ_0 0xBE0
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#define EMC_PMACRO_IB_VREF_DQ_1 0xBE4
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#define EMC_PMACRO_IB_VREF_DQS_0 0xBF0
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#define EMC_PMACRO_IB_VREF_DQS_1 0xBF4
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#define EMC_PMACRO_DDLL_LONG_CMD_0 0xC00
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#define EMC_PMACRO_DDLL_LONG_CMD_1 0xC04
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#define EMC_PMACRO_DDLL_LONG_CMD_2 0xC08
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#define EMC_PMACRO_DDLL_LONG_CMD_3 0xC0C
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#define EMC_PMACRO_DDLL_LONG_CMD_4 0xC10
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#define EMC_PMACRO_DDLL_SHORT_CMD_0 0xC20
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#define EMC_PMACRO_DDLL_SHORT_CMD_1 0xC24
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#define EMC_PMACRO_DDLL_SHORT_CMD_2 0xC28
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#define EMC_PMACRO_CFG_PM_GLOBAL_0 0xC30
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#define EMC_PMACRO_VTTGEN_CTRL_0 0xC34
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#define EMC_PMACRO_VTTGEN_CTRL_1 0xC38
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#define EMC_PMACRO_BG_BIAS_CTRL_0 0xC3C
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#define EMC_PMACRO_PAD_CFG_CTRL 0xC40
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#define EMC_PMACRO_ZCTRL 0xC44
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#define EMC_PMACRO_CMD_PAD_RX_CTRL 0xC50
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#define EMC_PMACRO_DATA_PAD_RX_CTRL 0xC54
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#define EMC_PMACRO_CMD_RX_TERM_MODE 0xC58
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#define EMC_PMACRO_DATA_RX_TERM_MODE 0xC5C
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#define EMC_PMACRO_CMD_PAD_TX_CTRL 0xC60
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#define EMC_PMACRO_DATA_PAD_TX_CTRL 0xC64
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#define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xC68
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#define EMC_PMACRO_AUTOCAL_CFG_COMMON 0xC78
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#define EMC_PMACRO_VTTGEN_CTRL_2 0xCF0
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#define EMC_PMACRO_IB_RXRT 0xCF4
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#define EMC_PMACRO_TRAINING_CTRL_0 0xCF8
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#define CH0_TRAINING_E_WRPTR (1 << 3)
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#define EMC_PMACRO_TRAINING_CTRL_1 0xCFC
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#define EMC_TRAINING_CMD 0xE00
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#define EMC_TRAINING_CTRL 0xE04
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#define EMC_TRAINING_STATUS 0xE08
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#define EMC_TRAINING_QUSE_CORS_CTRL 0xE0C
|
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#define EMC_TRAINING_QUSE_FINE_CTRL 0xE10
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#define EMC_TRAINING_QUSE_CTRL_MISC 0xE14
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#define EMC_TRAINING_WRITE_FINE_CTRL 0xE18
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#define EMC_TRAINING_WRITE_CTRL_MISC 0xE1C
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#define EMC_TRAINING_WRITE_VREF_CTRL 0xE20
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#define EMC_TRAINING_READ_FINE_CTRL 0xE24
|
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#define EMC_TRAINING_READ_CTRL_MISC 0xE28
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#define EMC_TRAINING_READ_VREF_CTRL 0xE2C
|
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#define EMC_TRAINING_CA_FINE_CTRL 0xE30
|
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#define EMC_TRAINING_CA_CTRL_MISC 0xE34
|
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#define EMC_TRAINING_CA_CTRL_MISC1 0xE38
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#define EMC_TRAINING_CA_VREF_CTRL 0xE3C
|
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#define EMC_TRAINING_SETTLE 0xE44
|
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#define EMC_TRAINING_MPC 0xE5C
|
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#define EMC_TRAINING_PATRAM_CTRL 0xE60
|
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#define EMC_TRAINING_PATRAM_DQ 0xE64
|
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#define EMC_TRAINING_PATRAM_DMI 0xE68
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#define EMC_TRAINING_VREF_SETTLE 0xE6C
|
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#define EMC_TRAINING_OPT_CA_VREF 0xEC0
|
|
#define EMC_TRAINING_OPT_DQ_OB_VREF 0xEC4
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|
#define EMC_TRAINING_QUSE_VREF_CTRL 0xED0
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#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 0xED4
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#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 0xED8
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|
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/* Per channel registers offsets. Should be used with EMC_BASE */
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#define EMC0_MRW10 0x34B4
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#define EMC0_MRW11 0x34B8
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#define EMC0_MRW12 0x34BC
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#define EMC0_MRW13 0x34C0
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#define EMC0_DATA_BRLSHFT_0 0x3588
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#define EMC0_DATA_BRLSHFT_1 0x358C
|
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#define EMC0_CMD_BRLSHFT_0 0x359C
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#define EMC0_QUSE_BRLSHFT_0 0x35AC
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#define EMC0_QUSE_BRLSHFT_2 0x35BC
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#define EMC0_TRAINING_RW_OFFSET_IB_BYTE0 0x3E98
|
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#define EMC0_TRAINING_RW_OFFSET_IB_BYTE1 0x3E9C
|
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#define EMC0_TRAINING_RW_OFFSET_IB_BYTE2 0x3EA0
|
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#define EMC0_TRAINING_RW_OFFSET_IB_BYTE3 0x3EA4
|
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#define EMC0_TRAINING_RW_OFFSET_IB_MISC 0x3EA8
|
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#define EMC0_TRAINING_RW_OFFSET_OB_BYTE0 0x3EAC
|
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#define EMC0_TRAINING_RW_OFFSET_OB_BYTE1 0x3EB0
|
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#define EMC0_TRAINING_RW_OFFSET_OB_BYTE2 0x3EB4
|
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#define EMC0_TRAINING_RW_OFFSET_OB_BYTE3 0x3EB8
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#define EMC0_TRAINING_RW_OFFSET_OB_MISC 0x3EBC
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#define EMC0_TRAINING_OPT_DQS_IB_VREF_RANK0 0x3ED4
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#define EMC0_TRAINING_OPT_DQS_IB_VREF_RANK1 0x3ED8
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#define EMC1_MRW10 0x44B4
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#define EMC1_MRW11 0x44B8
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#define EMC1_MRW12 0x44BC
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#define EMC1_MRW13 0x44C0
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#define EMC1_DATA_BRLSHFT_0 0x4588
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#define EMC1_DATA_BRLSHFT_1 0x458C
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#define EMC1_CMD_BRLSHFT_1 0x45A0
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#define EMC1_QUSE_BRLSHFT_1 0x45B8
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#define EMC1_QUSE_BRLSHFT_3 0x45C4
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#define EMC1_TRAINING_RW_OFFSET_IB_BYTE0 0x4E98
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#define EMC1_TRAINING_RW_OFFSET_IB_BYTE1 0x4E9C
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#define EMC1_TRAINING_RW_OFFSET_IB_BYTE2 0x4EA0
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#define EMC1_TRAINING_RW_OFFSET_IB_BYTE3 0x4EA4
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#define EMC1_TRAINING_RW_OFFSET_IB_MISC 0x4EA8
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#define EMC1_TRAINING_RW_OFFSET_OB_BYTE0 0x4EAC
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#define EMC1_TRAINING_RW_OFFSET_OB_BYTE1 0x4EB0
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#define EMC1_TRAINING_RW_OFFSET_OB_BYTE2 0x4EB4
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#define EMC1_TRAINING_RW_OFFSET_OB_BYTE3 0x4EB8
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#define EMC1_TRAINING_RW_OFFSET_OB_MISC 0x4EBC
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#define EMC1_TRAINING_OPT_DQS_IB_VREF_RANK0 0x4ED4
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#define EMC1_TRAINING_OPT_DQS_IB_VREF_RANK1 0x4ED8
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE0_SHIFT 0
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE1_SHIFT 16
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE2_SHIFT 0
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE3_SHIFT 16
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE4_SHIFT 0
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE5_SHIFT 16
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE6_SHIFT 0
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#define EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE7_SHIFT 16
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#endif |