mirror of
https://github.com/CTCaer/hekate
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185526d134
BDK will allow developers to use the full collection of drivers, with limited editing, if any, for making payloads for Nintendo Switch. Using a single source for everything will also help decoupling Switch specific code and easily port it to other Tegra X1/X1+ platforms. And maybe even to lower targets. Everything is now centrilized into bdk folder. Every module or project can utilize it by simply including it. This is just the start and it will continue to improve.
173 lines
5.3 KiB
C
173 lines
5.3 KiB
C
/*
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* USB driver for Tegra X1
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*
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* Copyright (c) 2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _USB_T210_H_
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#define _USB_T210_H_
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#include "../utils/types.h"
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/* General USB registers */
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#define USB1_IF_USB_SUSP_CTRL 0x400
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#define SUSP_CTRL_USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
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#define SUSP_CTRL_USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
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#define SUSP_CTRL_USB_PHY_CLK_VALID (1 << 7)
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#define SUSP_CTRL_UTMIP_RESET (1 << 11)
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#define SUSP_CTRL_UTMIP_PHY_ENB (1 << 12)
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#define SUSP_CTRL_UTMIP_UTMIP_SUSPL1_SET (1 << 25)
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#define USB1_IF_USB_PHY_VBUS_SENSORS 0x404
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#define USB1_UTMIP_XCVR_CFG0 0x808
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#define USB1_UTMIP_BIAS_CFG0 0x80C
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#define USB1_UTMIP_HSRX_CFG0 0x810
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#define USB1_UTMIP_HSRX_CFG1 0x814
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#define USB1_UTMIP_TX_CFG0 0x820
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#define USB1_UTMIP_MISC_CFG1 0x828
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#define USB1_UTMIP_DEBOUNCE_CFG0 0x82C
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#define USB1_UTMIP_SPARE_CFG0 0x834
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#define USB1_UTMIP_XCVR_CFG1 0x838
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#define USB1_UTMIP_BIAS_CFG1 0x83C
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#define USB1_UTMIP_BIAS_CFG2 0x850
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#define USB1_UTMIP_XCVR_CFG2 0x854
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#define USB1_UTMIP_XCVR_CFG3 0x858
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/* USB Queue Head Descriptor */
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#define USB2_QH_USB2D_QH_EP_BASE (USB_BASE + 0x1000)
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#define USB_QHD_EP_CAP_IOS_ENABLE (1 << 15)
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#define USB_QHD_EP_CAP_MAX_PKT_LEN_MASK 0x7FF
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#define USB_QHD_EP_CAP_ZERO_LEN_TERM_DIS (1 << 29)
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#define USB_QHD_EP_CAP_MULTI_NON_ISO (0 << 30)
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#define USB_QHD_EP_CAP_MULTI_1 (1 << 30)
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#define USB_QHD_EP_CAP_MULTI_2 (2 << 30)
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#define USB_QHD_EP_CAP_MULTI_3 (3 << 30)
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#define USB_QHD_TOKEN_XFER_ERROR (1 << 3)
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#define USB_QHD_TOKEN_BUFFER_ERROR (1 << 5)
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#define USB_QHD_TOKEN_HALTED (1 << 6)
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#define USB_QHD_TOKEN_ACTIVE (1 << 7)
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#define USB_QHD_TOKEN_MULT_OVERR_MASK (2 << 10)
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#define USB_QHD_TOKEN_IRQ_ON_COMPLETE (1 << 15)
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#define USB_QHD_TOKEN_TOTAL_BYTES_SHIFT 16
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/* USB_OTG/USB_1 controllers register bits */
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#define USB2D_PORTSC1_SUSP (1 << 7)
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#define USB2D_USBCMD_RUN (1 << 0)
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#define USB2D_USBCMD_RESET (1 << 1)
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#define USB2D_USBCMD_ITC_MASK (0xFF << 16)
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#define USB2D_USBSTS_UI (1 << 0)
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#define USB2D_USBSTS_UEI (1 << 1)
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#define USB2D_USBSTS_PCI (1 << 2)
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#define USB2D_USBSTS_FRI (1 << 3)
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#define USB2D_USBSTS_SEI (1 << 4)
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#define USB2D_USBSTS_AAI (1 << 5)
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#define USB2D_USBSTS_URI (1 << 6)
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#define USB2D_USBSTS_SRI (1 << 7)
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#define USB2D_USBSTS_SLI (1 << 8)
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#define USB2D_USBMODE_CM_MASK (3 << 0)
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#define USB2D_USBMODE_CM_IDLE 0
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#define USB2D_USBMODE_CM_RSVD 1
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#define USB2D_USBMODE_CM_DEVICE 2
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#define USB2D_USBMODE_CM_HOST 3
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#define USB2D_ENDPT_STATUS_RX_OFFSET (1 << 0)
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#define USB2D_ENDPT_STATUS_TX_OFFSET (1 << 16)
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#define USB2D_ENDPTCTRL_RX_EP_STALL (1 << 0)
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#define USB2D_ENDPTCTRL_RX_EP_TYPE_CTRL (0 << 2)
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#define USB2D_ENDPTCTRL_RX_EP_TYPE_ISO (1 << 2)
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#define USB2D_ENDPTCTRL_RX_EP_TYPE_BULK (2 << 2)
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#define USB2D_ENDPTCTRL_RX_EP_TYPE_INTR (3 << 2)
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#define USB2D_ENDPTCTRL_RX_EP_TYPE_MASK (3 << 2)
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#define USB2D_ENDPTCTRL_RX_EP_INHIBIT (1 << 5)
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#define USB2D_ENDPTCTRL_RX_EP_RESET (1 << 6)
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#define USB2D_ENDPTCTRL_RX_EP_ENABLE (1 << 7)
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#define USB2D_ENDPTCTRL_TX_EP_STALL (1 << 16)
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#define USB2D_ENDPTCTRL_TX_EP_TYPE_CTRL (0 << 18)
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#define USB2D_ENDPTCTRL_TX_EP_TYPE_ISO (1 << 18)
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#define USB2D_ENDPTCTRL_TX_EP_TYPE_BULK (2 << 18)
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#define USB2D_ENDPTCTRL_TX_EP_TYPE_INTR (3 << 18)
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#define USB2D_ENDPTCTRL_TX_EP_TYPE_MASK (3 << 18)
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#define USB2D_ENDPTCTRL_TX_EP_INHIBIT (1 << 21)
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#define USB2D_ENDPTCTRL_TX_EP_RESET (1 << 22)
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#define USB2D_ENDPTCTRL_TX_EP_ENABLE (1 << 23)
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#define USB2D_HOSTPC1_DEVLC_ASUS (1 << 17)
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#define USB2D_HOSTPC1_DEVLC_PHCD (1 << 22)
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#define USB2D_HOSTPC1_DEVLC_PSPD_MASK (3 << 25)
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#define USB2D_OTGSC_USB_ID_PULLUP (1 << 5)
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#define USB2D_OTGSC_USB_IRQ_STS_MASK (0x7F << 16)
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/* USB_OTG/USB_1 controllers registers */
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typedef struct _t210_usb2d_t
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{
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vu32 id;
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vu32 unk0;
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vu32 hw_host;
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vu32 hw_device;
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vu32 hw_txbuf;
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vu32 hw_rxbuf;
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vu32 unk1[26];
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vu32 gptimer0ld;
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vu32 gptimer0ctrl;
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vu32 gptimer1ld;
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vu32 gptimer1ctrl;
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vu32 unk2[28];
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vu16 caplength;
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vu16 hciversion;
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vu32 hcsparams;
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vu32 hccparams;
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vu32 unk3[5];
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vu32 dciversion;
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vu32 dccparams;
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vu32 extsts;
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vu32 usbextintr;
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vu32 usbcmd;
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vu32 usbsts;
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vu32 usbintr;
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vu32 frindex;
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vu32 unk4;
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vu32 periodiclistbase;
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vu32 asynclistaddr;
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vu32 asyncttsts;
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vu32 burstsize;
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vu32 txfilltuning;
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vu32 unk6;
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vu32 icusb_ctrl;
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vu32 ulpi_viewport;
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vu32 rsvd0[4];
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vu32 portsc1;
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vu32 rsvd1[15];
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vu32 hostpc1_devlc;
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vu32 rsvd2[15];
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vu32 otgsc;
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vu32 usbmode;
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vu32 unk10;
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vu32 endptnak;
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vu32 endptnak_enable;
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vu32 endptsetupstat;
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vu32 endptprime;
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vu32 endptflush;
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vu32 endptstatus;
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vu32 endptcomplete;
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vu32 endptctrl[16];
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} t210_usb2d_t;
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#endif
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