mirror of
https://github.com/CTCaer/hekate
synced 2024-07-03 15:03:29 +00:00
185526d134
BDK will allow developers to use the full collection of drivers, with limited editing, if any, for making payloads for Nintendo Switch. Using a single source for everything will also help decoupling Switch specific code and easily port it to other Tegra X1/X1+ platforms. And maybe even to lower targets. Everything is now centrilized into bdk folder. Every module or project can utilize it by simply including it. This is just the start and it will continue to improve.
109 lines
2.7 KiB
C
109 lines
2.7 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _SDMMC_T210_H_
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#define _SDMMC_T210_H_
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#include "../utils/types.h"
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#define TEGRA_MMC_VNDR_TUN_CTRL0_TAP_VAL_UPDATED_BY_HW 0x20000
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#define TEGRA_MMC_DLLCAL_CFG_EN_CALIBRATE 0x80000000
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#define TEGRA_MMC_DLLCAL_CFG_STATUS_DLL_ACTIVE 0x80000000
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#define TEGRA_MMC_SDMEMCOMPPADCTRL_PAD_E_INPUT_PWRD 0x80000000
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#define TEGRA_MMC_SDMEMCOMPPADCTRL_COMP_VREF_SEL_MASK 0xFFFFFFF0
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#define TEGRA_MMC_AUTOCALCFG_AUTO_CAL_ENABLE 0x20000000
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#define TEGRA_MMC_AUTOCALCFG_AUTO_CAL_START 0x80000000
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#define TEGRA_MMC_AUTOCALSTS_AUTO_CAL_ACTIVE 0x80000000
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typedef struct _t210_sdmmc_t
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{
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vu32 sysad;
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vu16 blksize;
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vu16 blkcnt;
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vu32 argument;
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vu16 trnmod;
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vu16 cmdreg;
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vu32 rspreg0;
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vu32 rspreg1;
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vu32 rspreg2;
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vu32 rspreg3;
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vu32 bdata;
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vu32 prnsts;
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vu8 hostctl;
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vu8 pwrcon;
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vu8 blkgap;
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vu8 wakcon;
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vu16 clkcon;
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vu8 timeoutcon;
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vu8 swrst;
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vu16 norintsts;
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vu16 errintsts;
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vu16 norintstsen; // Enable irq status.
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vu16 errintstsen; // Enable irq status.
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vu16 norintsigen; // Enable irq signal to LIC/GIC.
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vu16 errintsigen; // Enable irq signal to LIC/GIC.
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vu16 acmd12errsts;
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vu16 hostctl2;
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vu32 capareg;
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vu32 capareg_1;
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vu32 maxcurr;
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vu8 rsvd0[4]; // 4C-4F reserved for more max current.
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vu16 setacmd12err;
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vu16 setinterr;
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vu8 admaerr;
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vu8 rsvd1[3]; // 55-57 reserved.
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vu32 admaaddr;
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vu32 admaaddr_hi;
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vu8 rsvd2[156]; // 60-FB reserved.
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vu16 slotintsts;
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vu16 hcver;
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vu32 venclkctl;
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vu32 vensysswctl;
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vu32 venerrintsts;
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vu32 vencapover;
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vu32 venbootctl;
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vu32 venbootacktout;
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vu32 venbootdattout;
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vu32 vendebouncecnt;
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vu32 venmiscctl;
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vu32 maxcurrover;
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vu32 maxcurrover_hi;
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vu32 unk0[32]; // 0x12C
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vu32 veniotrimctl;
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vu32 vendllcalcfg;
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vu32 vendllctl0;
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vu32 vendllctl1;
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vu32 vendllcalcfgsts;
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vu32 ventunctl0;
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vu32 ventunctl1;
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vu32 ventunsts0;
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vu32 ventunsts1;
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vu32 venclkgatehystcnt;
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vu32 venpresetval0;
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vu32 venpresetval1;
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vu32 venpresetval2;
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vu32 sdmemcmppadctl;
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vu32 autocalcfg;
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vu32 autocalintval;
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vu32 autocalsts;
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vu32 iospare;
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vu32 mcciffifoctl;
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vu32 timeoutwcoal;
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} t210_sdmmc_t;
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#endif
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