mirror of
https://github.com/CTCaer/hekate
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185526d134
BDK will allow developers to use the full collection of drivers, with limited editing, if any, for making payloads for Nintendo Switch. Using a single source for everything will also help decoupling Switch specific code and easily port it to other Tegra X1/X1+ platforms. And maybe even to lower targets. Everything is now centrilized into bdk folder. Every module or project can utilize it by simply including it. This is just the start and it will continue to improve.
287 lines
9.4 KiB
C
287 lines
9.4 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _T210_H_
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#define _T210_H_
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#include "../utils/types.h"
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#define BOOTROM_BASE 0x100000
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#define IRAM_BASE 0x40000000
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#define HOST1X_BASE 0x50000000
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#define BPMP_CACHE_BASE 0x50040000
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#define DISPLAY_A_BASE 0x54200000
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#define DSI_BASE 0x54300000
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#define VIC_BASE 0x54340000
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#define TSEC_BASE 0x54500000
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#define SOR1_BASE 0x54580000
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#define ICTLR_BASE 0x60004000
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#define TMR_BASE 0x60005000
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#define CLOCK_BASE 0x60006000
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#define FLOW_CTLR_BASE 0x60007000
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#define AHBDMA_BASE 0x60008000
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#define SYSREG_BASE 0x6000C000
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#define SB_BASE (SYSREG_BASE + 0x200)
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#define GPIO_BASE 0x6000D000
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#define GPIO_1_BASE (GPIO_BASE)
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#define GPIO_2_BASE (GPIO_BASE + 0x100)
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#define GPIO_3_BASE (GPIO_BASE + 0x200)
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#define GPIO_4_BASE (GPIO_BASE + 0x300)
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#define GPIO_5_BASE (GPIO_BASE + 0x400)
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#define GPIO_6_BASE (GPIO_BASE + 0x500)
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#define GPIO_7_BASE (GPIO_BASE + 0x600)
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#define GPIO_8_BASE (GPIO_BASE + 0x700)
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#define EXCP_VEC_BASE 0x6000F000
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#define IPATCH_BASE 0x6001DC00
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#define APBDMA_BASE 0x60020000
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#define APB_MISC_BASE 0x70000000
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#define PINMUX_AUX_BASE 0x70003000
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#define UART_BASE 0x70006000
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#define PWM_BASE 0x7000A000
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#define RTC_BASE 0x7000E000
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#define PMC_BASE 0x7000E400
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#define SYSCTR0_BASE 0x700F0000
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#define FUSE_BASE 0x7000F800
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#define KFUSE_BASE 0x7000FC00
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#define SE_BASE 0x70012000
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#define MC_BASE 0x70019000
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#define EMC_BASE 0x7001B000
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#define EMC0_BASE 0x7001E000
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#define EMC1_BASE 0x7001F000
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#define MIPI_CAL_BASE 0x700E3000
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#define CL_DVFS_BASE 0x70110000
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#define I2S_BASE 0x702D1000
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#define ADMA_BASE 0x702E2000
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#define TZRAM_BASE 0x7C010000
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#define USB_BASE 0x7D000000
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#define USB_OTG_BASE USB_BASE
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#define USB1_BASE 0x7D004000
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#define _REG(base, off) *(vu32 *)((base) + (off))
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#define HOST1X(off) _REG(HOST1X_BASE, off)
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#define BPMP_CACHE_CTRL(off) _REG(BPMP_CACHE_BASE, off)
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#define DISPLAY_A(off) _REG(DISPLAY_A_BASE, off)
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#define DSI(off) _REG(DSI_BASE, off)
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#define VIC(off) _REG(VIC_BASE, off)
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#define TSEC(off) _REG(TSEC_BASE, off)
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#define SOR1(off) _REG(SOR1_BASE, off)
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#define ICTLR(cidx, off) _REG(ICTLR_BASE + (0x100 * cidx), off)
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#define TMR(off) _REG(TMR_BASE, off)
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#define CLOCK(off) _REG(CLOCK_BASE, off)
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#define FLOW_CTLR(off) _REG(FLOW_CTLR_BASE, off)
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#define SYSREG(off) _REG(SYSREG_BASE, off)
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#define AHB_GIZMO(off) _REG(SYSREG_BASE, off)
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#define SB(off) _REG(SB_BASE, off)
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#define GPIO(off) _REG(GPIO_BASE, off)
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#define GPIO_1(off) _REG(GPIO_1_BASE, off)
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#define GPIO_2(off) _REG(GPIO_2_BASE, off)
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#define GPIO_3(off) _REG(GPIO_3_BASE, off)
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#define GPIO_4(off) _REG(GPIO_4_BASE, off)
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#define GPIO_5(off) _REG(GPIO_5_BASE, off)
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#define GPIO_6(off) _REG(GPIO_6_BASE, off)
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#define GPIO_7(off) _REG(GPIO_7_BASE, off)
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#define GPIO_8(off) _REG(GPIO_8_BASE, off)
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#define EXCP_VEC(off) _REG(EXCP_VEC_BASE, off)
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#define APB_MISC(off) _REG(APB_MISC_BASE, off)
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#define PINMUX_AUX(off) _REG(PINMUX_AUX_BASE, off)
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#define PWM(off) _REG(PWM_BASE, off)
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#define RTC(off) _REG(RTC_BASE, off)
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#define PMC(off) _REG(PMC_BASE, off)
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#define SYSCTR0(off) _REG(SYSCTR0_BASE, off)
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#define FUSE(off) _REG(FUSE_BASE, off)
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#define KFUSE(off) _REG(KFUSE_BASE, off)
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#define SE(off) _REG(SE_BASE, off)
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#define MC(off) _REG(MC_BASE, off)
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#define EMC(off) _REG(EMC_BASE, off)
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#define EMC_CH0(off) _REG(EMC0_BASE, off)
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#define EMC_CH1(off) _REG(EMC1_BASE, off)
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#define MIPI_CAL(off) _REG(MIPI_CAL_BASE, off)
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#define CL_DVFS(off) _REG(CL_DVFS_BASE, off)
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#define I2S(off) _REG(I2S_BASE, off)
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#define ADMA(off) _REG(ADMA_BASE, off)
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#define USB(off) _REG(USB_BASE, off)
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#define USB1(off) _REG(USB1_BASE, off)
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#define TEST_REG(off) _REG(0x0, off)
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/* HOST1X registers. */
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#define HOST1X_CH0_SYNC_BASE 0x2100
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#define HOST1X_CH0_SYNC_SYNCPT_9 (HOST1X_CH0_SYNC_BASE + 0xFA4)
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#define HOST1X_CH0_SYNC_SYNCPT_160 (HOST1X_CH0_SYNC_BASE + 0x1200)
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/*! EVP registers. */
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#define EVP_CPU_RESET_VECTOR 0x100
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#define EVP_COP_RESET_VECTOR 0x200
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#define EVP_COP_UNDEF_VECTOR 0x204
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#define EVP_COP_SWI_VECTOR 0x208
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#define EVP_COP_PREFETCH_ABORT_VECTOR 0x20C
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#define EVP_COP_DATA_ABORT_VECTOR 0x210
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#define EVP_COP_RSVD_VECTOR 0x214
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#define EVP_COP_IRQ_VECTOR 0x218
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#define EVP_COP_FIQ_VECTOR 0x21C
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#define EVP_COP_IRQ_STS 0x220
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/*! Primary Interrupt Controller registers. */
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#define PRI_ICTLR_FIR 0x14
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#define PRI_ICTLR_FIR_SET 0x18
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#define PRI_ICTLR_FIR_CLR 0x1C
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#define PRI_ICTLR_CPU_IER 0x20
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#define PRI_ICTLR_CPU_IER_SET 0x24
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#define PRI_ICTLR_CPU_IER_CLR 0x28
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#define PRI_ICTLR_CPU_IEP_CLASS 0x2C
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#define PRI_ICTLR_COP_IER 0x30
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#define PRI_ICTLR_COP_IER_SET 0x34
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#define PRI_ICTLR_COP_IER_CLR 0x38
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#define PRI_ICTLR_COP_IEP_CLASS 0x3C
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/*! AHB Gizmo registers. */
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#define AHB_ARBITRATION_PRIORITY_CTRL 0x8
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#define ARBITRATION_PRIORITY_CTRL_ENB_FAST_REARBITRATE (1 << 6)
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#define AHB_GIZMO_AHB_MEM 0x10
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#define AHB_MEM_ENB_FAST_REARBITRATE (1 << 2)
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#define AHB_GIZMO_USB 0x20
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#define AHB_GIZMO_USB_IMMEDIATE (1 << 18)
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#define AHB_AHB_MEM_PREFETCH_CFG1 0xF0
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#define MEM_PREFETCH_ENABLE (1 << 31)
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#define MEM_PREFETCH_AHB_MST_USB 6
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/*! Misc registers. */
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#define APB_MISC_PP_STRAPPING_OPT_A 0x08
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#define APB_MISC_PP_PINMUX_GLOBAL 0x40
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#define APB_MISC_GP_HIDREV 0x804
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#define APB_MISC_GP_AUD_MCLK_CFGPADCTRL 0x8F4
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#define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34
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#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98
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#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL 0xA9C
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#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL 0xAB4
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#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL 0xABC
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#define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64
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#define APB_MISC_GP_WIFI_RST_CFGPADCTRL 0xB68
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/*! System registers. */
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#define AHB_ARBITRATION_XBAR_CTRL 0xE0
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#define AHB_AHB_SPARE_REG 0x110
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/*! Secure boot registers. */
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#define SB_CSR 0x0
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#define SB_CSR_NS_RST_VEC_WR_DIS (1 << 1)
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#define SB_CSR_PIROM_DISABLE (1 << 4)
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#define SB_AA64_RESET_LOW 0x30
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#define SB_AA64_RST_AARCH64_MODE_EN (1 << 0)
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#define SB_AA64_RESET_HIGH 0x34
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/*! SOR registers. */
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#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB 0x1E8
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#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB 0x21C
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#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB 0x208
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#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB 0x20C
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/*! RTC registers. */
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#define APBDEV_RTC_SECONDS 0x8
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#define APBDEV_RTC_SHADOW_SECONDS 0xC
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#define APBDEV_RTC_MILLI_SECONDS 0x10
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/*! SYSCTR0 registers. */
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#define SYSCTR0_CNTFID0 0x20
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#define SYSCTR0_CNTCR 0x00
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#define SYSCTR0_COUNTERID0 0xFE0
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#define SYSCTR0_COUNTERID1 0xFE4
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#define SYSCTR0_COUNTERID2 0xFE8
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#define SYSCTR0_COUNTERID3 0xFEC
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#define SYSCTR0_COUNTERID4 0xFD0
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#define SYSCTR0_COUNTERID5 0xFD4
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#define SYSCTR0_COUNTERID6 0xFD8
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#define SYSCTR0_COUNTERID7 0xFDC
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#define SYSCTR0_COUNTERID8 0xFF0
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#define SYSCTR0_COUNTERID9 0xFF4
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#define SYSCTR0_COUNTERID10 0xFF8
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#define SYSCTR0_COUNTERID11 0xFFC
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/*! TMR registers. */
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#define TIMERUS_CNTR_1US (0x10 + 0x0)
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#define TIMERUS_USEC_CFG (0x10 + 0x4)
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#define TIMER_TMR8_TMR_PTV 0x78
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#define TIMER_TMR9_TMR_PTV 0x80
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#define TIMER_EN (1 << 31)
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#define TIMER_PER_EN (1 << 30)
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#define TIMER_TMR8_TMR_PCR 0x7C
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#define TIMER_TMR9_TMR_PCR 0x8C
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#define TIMER_INTR_CLR (1 << 30)
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#define TIMER_WDT4_CONFIG (0x100 + 0x80)
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#define TIMER_SRC(TMR) (TMR & 0xF)
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#define TIMER_PER(PER) ((PER & 0xFF) << 4)
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#define TIMER_SYSRESET_EN (1 << 14)
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#define TIMER_PMCRESET_EN (1 << 15)
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#define TIMER_WDT4_COMMAND (0x108 + 0x80)
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#define TIMER_START_CNT (1 << 0)
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#define TIMER_CNT_DISABLE (1 << 1)
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#define TIMER_WDT4_UNLOCK_PATTERN (0x10C + 0x80)
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#define TIMER_MAGIC_PTRN 0xC45A
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/*! I2S registers. */
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#define I2S1_CG 0x88
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#define I2S1_CTRL 0xA0
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#define I2S2_CG 0x188
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#define I2S2_CTRL 0x1A0
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#define I2S3_CG 0x288
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#define I2S3_CTRL 0x2A0
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#define I2S4_CG 0x388
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#define I2S4_CTRL 0x3A0
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#define I2S5_CG 0x488
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#define I2S5_CTRL 0x4A0
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#define I2S_CG_SLCG_ENABLE (1 << 0)
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#define I2S_CTRL_MASTER_EN (1 << 10)
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/*! PWM registers. */
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#define PWM_CONTROLLER_PWM_CSR_0 0x00
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#define PWM_CONTROLLER_PWM_CSR_1 0x10
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#define PWM_CSR_EN (1 << 31)
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/*! Special registers. */
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#define EMC_SCRATCH0 0x324
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#define EMC_HEKA_UPD (1 << 30)
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#define EMC_SEPT_RUN (1 << 31)
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/*! Flow controller registers. */
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#define FLOW_CTLR_HALT_COP_EVENTS 0x4
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#define HALT_COP_GIC_IRQ (1 << 9)
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#define HALT_COP_LIC_IRQ (1 << 11)
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#define HALT_COP_SEC (1 << 23)
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#define HALT_COP_MSEC (1 << 24)
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#define HALT_COP_USEC (1 << 25)
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#define HALT_COP_JTAG (1 << 28)
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#define HALT_COP_WAIT_EVENT (1 << 30)
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#define HALT_COP_STOP_UNTIL_IRQ (1 << 31)
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#define HALT_COP_MAX_CNT 0xFF
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#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0
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#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14
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#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C
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#define FLOW_CTLR_HALT_CPU3_EVENTS 0x24
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#define FLOW_CTLR_CPU0_CSR 0x8
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#define FLOW_CTLR_CPU1_CSR 0x18
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#define FLOW_CTLR_CPU2_CSR 0x20
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#define FLOW_CTLR_CPU3_CSR 0x28
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#define FLOW_CTLR_RAM_REPAIR 0x40
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#define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98
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/*! USB controller registers. */
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#define USB1_UTMIP_BAT_CHRG_CFG0 0x830
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#define BAT_CHRG_CFG0_OP_SRC_EN (1 << 3)
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#define BAT_CHRG_CFG0_PWRDOWN_CHRG (1 << 0)
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#endif
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