mirror of
https://github.com/CTCaer/hekate
synced 2024-07-06 00:13:29 +00:00
185526d134
BDK will allow developers to use the full collection of drivers, with limited editing, if any, for making payloads for Nintendo Switch. Using a single source for everything will also help decoupling Switch specific code and easily port it to other Tegra X1/X1+ platforms. And maybe even to lower targets. Everything is now centrilized into bdk folder. Every module or project can utilize it by simply including it. This is just the start and it will continue to improve.
222 lines
5.4 KiB
C
222 lines
5.4 KiB
C
/*
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* BPMP-Lite IRQ driver for Tegra X1
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*
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* Copyright (c) 2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef IRQ_H
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#define IRQ_H
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#include "../utils/types.h"
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#define IRQ_MAX_HANDLERS 16
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/* Primary interrupt controller ids */
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#define IRQ_TMR1 0
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#define IRQ_TMR2 1
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#define IRQ_RTC 2
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#define IRQ_CEC 3
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#define IRQ_SHR_SEM_INBOX_FULL 4
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#define IRQ_SHR_SEM_INBOX_EMPTY 5
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#define IRQ_SHR_SEM_OUTBOX_FULL 6
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#define IRQ_SHR_SEM_OUTBOX_EMPTY 7
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#define IRQ_NVJPEG 8
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#define IRQ_NVDEC 9
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#define IRQ_QUAD_SPI 10
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#define IRQ_DPAUX_INT1 11
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#define IRQ_SATA_RX_STAT 13
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#define IRQ_SDMMC1 14
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#define IRQ_SDMMC2 15
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#define IRQ_VGPIO_INT 16
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#define IRQ_VII2C_INT 17
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#define IRQ_SDMMC3 19
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#define IRQ_USB 20
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#define IRQ_USB2 21
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#define IRQ_SATA_CTL 23
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#define IRQ_PMC_INT 24
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#define IRQ_FC_INT 25
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#define IRQ_APB_DMA_CPU 26
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#define IRQ_ARB_SEM_GNT_COP 28
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#define IRQ_ARB_SEM_GNT_CPU 29
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#define IRQ_SDMMC4 31
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/* Secondary interrupt controller ids */
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#define IRQ_GPIO1 32
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#define IRQ_GPIO2 33
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#define IRQ_GPIO3 34
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#define IRQ_GPIO4 35
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#define IRQ_UARTA 36
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#define IRQ_UARTB 37
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#define IRQ_I2C 38
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#define IRQ_USB3_HOST_INT 39
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#define IRQ_USB3_HOST_SMI 40
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#define IRQ_TMR3 41
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#define IRQ_TMR4 42
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#define IRQ_USB3_HOST_PME 43
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#define IRQ_USB3_DEV_HOST 44
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#define IRQ_ACTMON 45
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#define IRQ_UARTC 46
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#define IRQ_THERMAL 48
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#define IRQ_XUSB_PADCTL 49
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#define IRQ_TSEC 50
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#define IRQ_EDP 51
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#define IRQ_I2C5 53
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#define IRQ_GPIO5 55
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#define IRQ_USB3_DEV_SMI 56
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#define IRQ_USB3_DEV_PME 57
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#define IRQ_SE 58
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#define IRQ_SPI1 59
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#define IRQ_APB_DMA_COP 60
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#define IRQ_CLDVFS 62
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#define IRQ_I2C6 63
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/* Tertiary interrupt controller ids */
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#define IRQ_HOST1X_SYNCPT_COP 64
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#define IRQ_HOST1X_SYNCPT_CPU 65
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#define IRQ_HOST1X_GEN_COP 66
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#define IRQ_HOST1X_GEN_CPU 67
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#define IRQ_NVENC 68
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#define IRQ_VI 69
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#define IRQ_ISPB 70
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#define IRQ_ISP 71
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#define IRQ_VIC 72
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#define IRQ_DISPLAY 73
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#define IRQ_DISPLAYB 74
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#define IRQ_SOR1 75
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#define IRQ_SOR 76
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#define IRQ_MC 77
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#define IRQ_EMC 78
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#define IRQ_TSECB 80
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#define IRQ_HDA 81
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#define IRQ_SPI2 82
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#define IRQ_SPI3 83
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#define IRQ_I2C2 84
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#define IRQ_PMU_EXT 86
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#define IRQ_GPIO6 87
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#define IRQ_GPIO7 89
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#define IRQ_UARTD 90
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#define IRQ_I2C3 92
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#define IRQ_SPI4 93
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/* Quaternary interrupt controller ids */
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#define IRQ_DTV 96
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#define IRQ_PCIE_INT 98
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#define IRQ_PCIE_MSI 99
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#define IRQ_AVP_CACHE 101
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#define IRQ_APE_INT1 102
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#define IRQ_APE_INT0 103
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#define IRQ_APB_DMA_CH0 104
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#define IRQ_APB_DMA_CH1 105
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#define IRQ_APB_DMA_CH2 106
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#define IRQ_APB_DMA_CH3 107
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#define IRQ_APB_DMA_CH4 108
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#define IRQ_APB_DMA_CH5 109
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#define IRQ_APB_DMA_CH6 110
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#define IRQ_APB_DMA_CH7 111
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#define IRQ_APB_DMA_CH8 112
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#define IRQ_APB_DMA_CH9 113
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#define IRQ_APB_DMA_CH10 114
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#define IRQ_APB_DMA_CH11 115
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#define IRQ_APB_DMA_CH12 116
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#define IRQ_APB_DMA_CH13 117
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#define IRQ_APB_DMA_CH14 118
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#define IRQ_APB_DMA_CH15 119
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#define IRQ_I2C4 120
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#define IRQ_TMR5 121
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#define IRQ_WDT_CPU 123
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#define IRQ_WDT_AVP 124
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#define IRQ_GPIO8 125
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#define IRQ_CAR 126
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/* Quinary interrupt controller ids */
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#define IRQ_APB_DMA_CH16 128
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#define IRQ_APB_DMA_CH17 129
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#define IRQ_APB_DMA_CH18 130
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#define IRQ_APB_DMA_CH19 131
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#define IRQ_APB_DMA_CH20 132
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#define IRQ_APB_DMA_CH21 133
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#define IRQ_APB_DMA_CH22 134
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#define IRQ_APB_DMA_CH23 135
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#define IRQ_APB_DMA_CH24 136
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#define IRQ_APB_DMA_CH25 137
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#define IRQ_APB_DMA_CH26 138
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#define IRQ_APB_DMA_CH27 139
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#define IRQ_APB_DMA_CH28 140
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#define IRQ_APB_DMA_CH29 141
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#define IRQ_APB_DMA_CH30 142
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#define IRQ_APB_DMA_CH31 143
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#define IRQ_CPU0_PMU_INTR 144
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#define IRQ_CPU1_PMU_INTR 145
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#define IRQ_CPU2_PMU_INTR 146
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#define IRQ_CPU3_PMU_INTR 147
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#define IRQ_SDMMC1_SYS 148
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#define IRQ_SDMMC2_SYS 149
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#define IRQ_SDMMC3_SYS 150
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#define IRQ_SDMMC4_SYS 151
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#define IRQ_TMR6 152
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#define IRQ_TMR7 153
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#define IRQ_TMR8 154
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#define IRQ_TMR9 155
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#define IRQ_TMR0 156
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#define IRQ_GPU_STALL 157
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#define IRQ_GPU_NONSTALL 158
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#define IRQ_DPAUX 159
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/* Senary interrupt controller ids */
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#define IRQ_MPCORE_AXIERRIRQ 160
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#define IRQ_MPCORE_INTERRIRQ 161
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#define IRQ_EVENT_GPIO_A 162
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#define IRQ_EVENT_GPIO_B 163
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#define IRQ_EVENT_GPIO_C 164
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#define IRQ_FLOW_RSM_CPU 168
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#define IRQ_FLOW_RSM_COP 169
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#define IRQ_TMR_SHARED 170
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#define IRQ_MPCORE_CTIIRQ0 171
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#define IRQ_MPCORE_CTIIRQ1 172
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#define IRQ_MPCORE_CTIIRQ2 173
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#define IRQ_MPCORE_CTIIRQ3 174
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#define IRQ_MSELECT_ERROR 175
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#define IRQ_TMR10 176
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#define IRQ_TMR11 177
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#define IRQ_TMR12 178
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#define IRQ_TMR13 179
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typedef int (*irq_handler_t)(u32 irq, void *data);
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typedef enum _irq_status_t
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{
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IRQ_NONE = 0,
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IRQ_HANDLED = 1,
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IRQ_ERROR = 2,
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IRQ_ENABLED = 0,
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IRQ_NO_SLOTS_AVAILABLE = 1,
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IRQ_ALREADY_REGISTERED = 2
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} irq_status_t;
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typedef enum _irq_flags_t
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{
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IRQ_FLAG_NONE = 0,
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IRQ_FLAG_ONE_OFF = (1 << 0),
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IRQ_FLAG_REPLACEABLE = (1 << 1)
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} irq_flags_t;
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void irq_end();
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void irq_free(u32 irq);
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void irq_wait_event();
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void irq_disable_wait_event();
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irq_status_t irq_request(u32 irq, irq_handler_t handler, void *data, irq_flags_t flags);
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#endif |