mirror of
https://github.com/CTCaer/hekate
synced 2024-07-06 00:13:29 +00:00
185526d134
BDK will allow developers to use the full collection of drivers, with limited editing, if any, for making payloads for Nintendo Switch. Using a single source for everything will also help decoupling Switch specific code and easily port it to other Tegra X1/X1+ platforms. And maybe even to lower targets. Everything is now centrilized into bdk folder. Every module or project can utilize it by simply including it. This is just the start and it will continue to improve.
168 lines
4.4 KiB
C
168 lines
4.4 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "gpio.h"
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#include "t210.h"
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#define GPIO_BANK_IDX(port) (port >> 2)
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#define GPIO_CNF_OFFSET(port) (0x00 + ((port >> 2) << 8) + ((port % 4) << 2))
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#define GPIO_OE_OFFSET(port) (0x10 + ((port >> 2) << 8) + ((port % 4) << 2))
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#define GPIO_OUT_OFFSET(port) (0x20 + ((port >> 2) << 8) + ((port % 4) << 2))
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#define GPIO_IN_OFFSET(port) (0x30 + ((port >> 2) << 8) + ((port % 4) << 2))
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#define GPIO_INT_STA_OFFSET(port) (0x40 + ((port >> 2) << 8) + ((port % 4) << 2))
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#define GPIO_INT_ENB_OFFSET(port) (0x50 + ((port >> 2) << 8) + ((port % 4) << 2))
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#define GPIO_INT_LVL_OFFSET(port) (0x60 + ((port >> 2) << 8) + ((port % 4) << 2))
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#define GPIO_INT_CLR_OFFSET(port) (0x70 + ((port >> 2) << 8) + ((port % 4) << 2))
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#define GPIO_CNF_MASKED_OFFSET(port) (0x80 + ((port >> 2) << 8) + ((port % 4) << 2))
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#define GPIO_OE_MASKED_OFFSET(port) (0x90 + ((port >> 2) << 8) + ((port % 4) << 2))
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#define GPIO_OUT_MASKED_OFFSET(port) (0xA0 + ((port >> 2) << 8) + ((port % 4) << 2))
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#define GPIO_INT_STA_MASKED_OFFSET(port) (0xC0 + ((port >> 2) << 8) + ((port % 4) << 2))
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#define GPIO_INT_ENB_MASKED_OFFSET(port) (0xD0 + ((port >> 2) << 8) + ((port % 4) << 2))
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#define GPIO_INT_LVL_MASKED_OFFSET(port) (0xE0 + ((port >> 2) << 8) + ((port % 4) << 2))
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#define GPIO_IRQ_BANK1 32
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#define GPIO_IRQ_BANK2 33
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#define GPIO_IRQ_BANK3 34
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#define GPIO_IRQ_BANK4 35
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#define GPIO_IRQ_BANK5 55
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#define GPIO_IRQ_BANK6 87
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#define GPIO_IRQ_BANK7 89
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#define GPIO_IRQ_BANK8 125
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static u8 gpio_bank_irq_ids[8] = {
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GPIO_IRQ_BANK1, GPIO_IRQ_BANK2, GPIO_IRQ_BANK3, GPIO_IRQ_BANK4,
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GPIO_IRQ_BANK5, GPIO_IRQ_BANK6, GPIO_IRQ_BANK7, GPIO_IRQ_BANK8
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};
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void gpio_config(u32 port, u32 pins, int mode)
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{
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u32 offset = GPIO_CNF_OFFSET(port);
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if (mode)
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GPIO(offset) |= pins;
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else
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GPIO(offset) &= ~pins;
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(void)GPIO(offset); // Commit the write.
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}
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void gpio_output_enable(u32 port, u32 pins, int enable)
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{
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u32 port_offset = GPIO_OE_OFFSET(port);
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if (enable)
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GPIO(port_offset) |= pins;
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else
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GPIO(port_offset) &= ~pins;
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(void)GPIO(port_offset); // Commit the write.
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}
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void gpio_write(u32 port, u32 pins, int high)
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{
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u32 port_offset = GPIO_OUT_OFFSET(port);
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if (high)
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GPIO(port_offset) |= pins;
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else
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GPIO(port_offset) &= ~pins;
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(void)GPIO(port_offset); // Commit the write.
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}
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int gpio_read(u32 port, u32 pins)
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{
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u32 port_offset = GPIO_IN_OFFSET(port);
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return (GPIO(port_offset) & pins) ? 1 : 0;
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}
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static void _gpio_interrupt_clear(u32 port, u32 pins)
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{
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u32 port_offset = GPIO_INT_CLR_OFFSET(port);
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GPIO(port_offset) |= pins;
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(void)GPIO(port_offset); // Commit the write.
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}
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int gpio_interrupt_status(u32 port, u32 pins)
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{
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u32 port_offset = GPIO_INT_STA_OFFSET(port);
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u32 enabled = GPIO(GPIO_INT_ENB_OFFSET(port)) & pins;
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int status = ((GPIO(port_offset) & pins) && enabled) ? 1 : 0;
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// Clear the interrupt status.
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if (status)
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_gpio_interrupt_clear(port, pins);
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return status;
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}
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void gpio_interrupt_enable(u32 port, u32 pins, int enable)
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{
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u32 port_offset = GPIO_INT_ENB_OFFSET(port);
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// Clear any possible stray interrupt.
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_gpio_interrupt_clear(port, pins);
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if (enable)
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GPIO(port_offset) |= pins;
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else
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GPIO(port_offset) &= ~pins;
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(void)GPIO(port_offset); // Commit the write.
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}
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void gpio_interrupt_level(u32 port, u32 pins, int high, int edge, int delta)
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{
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u32 port_offset = GPIO_INT_LVL_OFFSET(port);
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u32 val = GPIO(port_offset);
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if (high)
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val |= pins;
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else
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val &= ~pins;
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if (edge)
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val |= pins << 8;
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else
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val &= ~(pins << 8);
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if (delta)
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val |= pins << 16;
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else
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val &= ~(pins << 16);
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GPIO(port_offset) = val;
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(void)GPIO(port_offset); // Commit the write.
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// Clear any possible stray interrupt.
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_gpio_interrupt_clear(port, pins);
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}
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u32 gpio_get_bank_irq_id(u32 port)
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{
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u32 bank_idx = GPIO_BANK_IDX(port);
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return gpio_bank_irq_ids[bank_idx];
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} |