mirror of
https://github.com/CTCaer/hekate
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185526d134
BDK will allow developers to use the full collection of drivers, with limited editing, if any, for making payloads for Nintendo Switch. Using a single source for everything will also help decoupling Switch specific code and easily port it to other Tegra X1/X1+ platforms. And maybe even to lower targets. Everything is now centrilized into bdk folder. Every module or project can utilize it by simply including it. This is just the start and it will continue to improve.
309 lines
9.7 KiB
C
309 lines
9.7 KiB
C
/*
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* BPMP-Lite Cache/MMU and Frequency driver for Tegra X1
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*
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* Copyright (c) 2019-2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "bpmp.h"
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#include "clock.h"
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#include "t210.h"
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#include "../../common/memory_map.h"
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#include "../utils/util.h"
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#define BPMP_MMU_CACHE_LINE_SIZE 0x20
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#define BPMP_CACHE_CONFIG 0x0
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#define CFG_ENABLE_CACHE (1 << 0)
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#define CFG_ENABLE_SKEW_ASSOC (1 << 1)
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#define CFG_DISABLE_RANDOM_ALLOC (1 << 2)
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#define CFG_FORCE_WRITE_THROUGH (1 << 3)
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#define CFG_NEVER_ALLOCATE (1 << 6)
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#define CFG_ENABLE_INTERRUPT (1 << 7)
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#define CFG_MMU_TAG_MODE(x) (x << 8)
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#define TAG_MODE_PARALLEL 0
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#define TAG_MODE_TAG_FIRST 1
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#define TAG_MODE_MMU_FIRST 2
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#define CFG_DISABLE_WRITE_BUFFER (1 << 10)
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#define CFG_DISABLE_READ_BUFFER (1 << 11)
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#define CFG_ENABLE_HANG_DETECT (1 << 12)
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#define CFG_FULL_LINE_DIRTY (1 << 13)
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#define CFG_TAG_CHK_ABRT_ON_ERR (1 << 14)
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#define CFG_TAG_CHK_CLR_ERR (1 << 15)
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#define CFG_DISABLE_SAMELINE (1 << 16)
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#define CFG_OBS_BUS_EN (1 << 31)
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#define BPMP_CACHE_LOCK 0x4
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#define LOCK_LINE(x) (1 << x)
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#define BPMP_CACHE_SIZE 0xC
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#define BPMP_CACHE_LFSR 0x10
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#define BPMP_CACHE_TAG_STATUS 0x14
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#define TAG_STATUS_TAG_CHECK_ERROR (1 << 0)
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#define TAG_STATUS_CONFLICT_ADDR_MASK 0xFFFFFFE0
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#define BPMP_CACHE_CLKEN_OVERRIDE 0x18
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#define CLKEN_OVERRIDE_WR_MCCIF_CLKEN (1 << 0)
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#define CLKEN_OVERRIDE_RD_MCCIF_CLKEN (1 << 1)
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#define BPMP_CACHE_MAINT_ADDR 0x20
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#define BPMP_CACHE_MAINT_DATA 0x24
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#define BPMP_CACHE_MAINT_REQ 0x28
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#define MAINT_REQ_WAY_BITMAP(x) ((x) << 8)
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#define BPMP_CACHE_INT_MASK 0x40
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#define BPMP_CACHE_INT_CLEAR 0x44
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#define BPMP_CACHE_INT_RAW_EVENT 0x48
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#define BPMP_CACHE_INT_STATUS 0x4C
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#define INT_MAINT_DONE (1 << 0)
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#define INT_MAINT_ERROR (1 << 1)
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#define BPMP_CACHE_RB_CFG 0x80
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#define BPMP_CACHE_WB_CFG 0x84
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#define BPMP_CACHE_MMU_FALLBACK_ENTRY 0xA0
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#define BPMP_CACHE_MMU_SHADOW_COPY_MASK 0xA4
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#define BPMP_CACHE_MMU_CFG 0xAC
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#define MMU_CFG_BLOCK_MAIN_ENTRY_WR (1 << 0)
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#define MMU_CFG_SEQ_EN (1 << 1)
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#define MMU_CFG_TLB_EN (1 << 2)
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#define MMU_CFG_SEG_CHECK_ALL_ENTRIES (1 << 3)
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#define MMU_CFG_ABORT_STORE_LAST (1 << 4)
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#define MMU_CFG_CLR_ABORT (1 << 5)
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#define BPMP_CACHE_MMU_CMD 0xB0
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#define MMU_CMD_NOP 0
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#define MMU_CMD_INIT 1
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#define MMU_CMD_COPY_SHADOW 2
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#define BPMP_CACHE_MMU_ABORT_STAT 0xB4
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#define ABORT_STAT_UNIT_MASK 0x7
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#define ABORT_STAT_UNIT_NONE 0
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#define ABORT_STAT_UNIT_CACHE 1
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#define ABORT_STAT_UNIT_SEQ 2
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#define ABORT_STAT_UNIT_TLB 3
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#define ABORT_STAT_UNIT_SEG 4
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#define ABORT_STAT_UNIT_FALLBACK 5
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#define ABORT_STAT_OVERLAP (1 << 3)
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#define ABORT_STAT_ENTRY (0x1F << 4)
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#define ABORT_STAT_TYPE_MASK (3 << 16)
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#define ABORT_STAT_TYPE_EXE (0 << 16)
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#define ABORT_STAT_TYPE_RD (1 << 16)
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#define ABORT_STAT_TYPE_WR (2 << 16)
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#define ABORT_STAT_SIZE (3 << 18)
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#define ABORT_STAT_SEQ (1 << 20)
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#define ABORT_STAT_PROT (1 << 21)
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#define BPMP_CACHE_MMU_ABORT_ADDR 0xB8
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#define BPMP_CACHE_MMU_ACTIVE_ENTRIES 0xBC
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#define BPMP_MMU_SHADOW_ENTRY_BASE (BPMP_CACHE_BASE + 0x400)
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#define BPMP_MMU_MAIN_ENTRY_BASE (BPMP_CACHE_BASE + 0x800)
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#define MMU_EN_CACHED (1 << 0)
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#define MMU_EN_EXEC (1 << 1)
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#define MMU_EN_READ (1 << 2)
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#define MMU_EN_WRITE (1 << 3)
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bpmp_mmu_entry_t mmu_entries[] =
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{
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{ DRAM_START, 0xFFFFFFFF, MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC | MMU_EN_CACHED, true },
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{ IRAM_BASE, 0x4003FFFF, MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC | MMU_EN_CACHED, true }
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};
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void bpmp_mmu_maintenance(u32 op, bool force)
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{
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if (!force && !(BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) & CFG_ENABLE_CACHE))
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return;
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BPMP_CACHE_CTRL(BPMP_CACHE_INT_CLEAR) = INT_MAINT_DONE;
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// This is a blocking operation.
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BPMP_CACHE_CTRL(BPMP_CACHE_MAINT_REQ) = MAINT_REQ_WAY_BITMAP(0xF) | op;
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while(!(BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT) & INT_MAINT_DONE))
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;
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BPMP_CACHE_CTRL(BPMP_CACHE_INT_CLEAR) = BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT);
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}
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void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply)
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{
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if (idx > 31)
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return;
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volatile bpmp_mmu_entry_t *mmu_entry = (bpmp_mmu_entry_t *)(BPMP_MMU_SHADOW_ENTRY_BASE + sizeof(bpmp_mmu_entry_t) * idx);
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if (entry->enable)
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{
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mmu_entry->start_addr = ALIGN(entry->start_addr, BPMP_MMU_CACHE_LINE_SIZE);
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mmu_entry->end_addr = ALIGN_DOWN(entry->end_addr, BPMP_MMU_CACHE_LINE_SIZE);
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mmu_entry->attr = entry->attr;
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_SHADOW_COPY_MASK) |= (1 << idx);
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if (apply)
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_COPY_SHADOW;
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}
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}
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void bpmp_mmu_enable()
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{
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if (BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) & CFG_ENABLE_CACHE)
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return;
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// Init BPMP MMU.
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_INIT;
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_FALLBACK_ENTRY) = MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC; // RWX for non-defined regions.
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CFG) = MMU_CFG_SEQ_EN | MMU_CFG_TLB_EN | MMU_CFG_ABORT_STORE_LAST;
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// Init BPMP MMU entries.
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_SHADOW_COPY_MASK) = 0;
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for (u32 idx = 0; idx < (sizeof(mmu_entries) / sizeof(bpmp_mmu_entry_t)); idx++)
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bpmp_mmu_set_entry(idx, &mmu_entries[idx], false);
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_COPY_SHADOW;
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// Invalidate cache.
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY, true);
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// Enable cache.
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BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) = CFG_ENABLE_CACHE | CFG_FORCE_WRITE_THROUGH |
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CFG_MMU_TAG_MODE(TAG_MODE_PARALLEL) | CFG_TAG_CHK_ABRT_ON_ERR;
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// HW bug. Invalidate cache again.
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY, false);
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}
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void bpmp_mmu_disable()
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{
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if (!(BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) & CFG_ENABLE_CACHE))
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return;
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// Clean and invalidate cache.
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false);
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// Disable cache.
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BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) = 0;
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}
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// APB clock affects RTC, PWM, MEMFETCH, APE, USB, SOR PWM,
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// I2C host, DC/DSI/DISP. UART gives extra stress.
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// 92: 100% success ratio. 93-94: 595-602MHz has 99% success ratio. 95: 608MHz less.
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const u8 pll_divn[] = {
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0, // BPMP_CLK_NORMAL: 408MHz 0% - 136MHz APB.
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85, // BPMP_CLK_HIGH_BOOST: 544MHz 33% - 136MHz APB.
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90, // BPMP_CLK_SUPER_BOOST: 576MHz 41% - 144MHz APB.
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92 // BPMP_CLK_HYPER_BOOST: 589MHz 44% - 147MHz APB.
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// Do not use for public releases!
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//95 // BPMP_CLK_DEV_BOOST: 608MHz 49% - 152MHz APB.
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};
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bpmp_freq_t bpmp_clock_set = BPMP_CLK_NORMAL;
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void bpmp_clk_rate_get()
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{
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bool clk_src_is_pllp = ((CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) >> 4) & 7) == 3;
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if (clk_src_is_pllp)
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bpmp_clock_set = BPMP_CLK_NORMAL;
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else
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{
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bpmp_clock_set = BPMP_CLK_HIGH_BOOST;
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u8 pll_divn_curr = (CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) >> 10) & 0xFF;
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for (u32 i = 1; i < sizeof(pll_divn); i++)
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{
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if (pll_divn[i] == pll_divn_curr)
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{
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bpmp_clock_set = i;
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break;
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}
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}
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}
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}
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void bpmp_clk_rate_set(bpmp_freq_t fid)
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{
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if (fid > (BPMP_CLK_MAX - 1))
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fid = BPMP_CLK_MAX - 1;
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if (bpmp_clock_set == fid)
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return;
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if (fid)
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{
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if (bpmp_clock_set)
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{
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// Restore to PLLP source during PLLC4 configuration.
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // PLLP_OUT.
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msleep(1); // Wait a bit for clock source change.
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}
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// Configure and enable PLLC.
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clock_enable_pllc(pll_divn[fid]);
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// Set SCLK / HCLK / PCLK.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 3; // PCLK = HCLK / (3 + 1). HCLK == SCLK.
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003310; // PLLC_OUT1 for active and CLKM for idle.
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}
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else
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{
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003330; // PLLP_OUT for active and CLKM for idle.
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msleep(1); // Wait a bit for clock source change.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // PCLK = HCLK / (2 + 1). HCLK == SCLK.
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// Disable PLLC to save power.
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clock_disable_pllc();
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}
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bpmp_clock_set = fid;
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}
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// The following functions halt BPMP to reduce power while sleeping.
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// They are not as accurate as RTC at big values but they guarantee time+ delay.
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void bpmp_usleep(u32 us)
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{
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u32 delay;
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// Each iteration takes 1us.
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while (us)
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{
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delay = (us > HALT_COP_MAX_CNT) ? HALT_COP_MAX_CNT : us;
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us -= delay;
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FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_USEC | delay;
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}
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}
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void bpmp_msleep(u32 ms)
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{
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u32 delay;
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// Iteration time is variable. ~200 - 1000us.
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while (ms)
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{
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delay = (ms > HALT_COP_MAX_CNT) ? HALT_COP_MAX_CNT : ms;
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ms -= delay;
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FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_MSEC | delay;
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}
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}
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void bpmp_halt()
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{
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FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_JTAG;
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}
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