mirror of
https://github.com/CTCaer/hekate
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185526d134
BDK will allow developers to use the full collection of drivers, with limited editing, if any, for making payloads for Nintendo Switch. Using a single source for everything will also help decoupling Switch specific code and easily port it to other Tegra X1/X1+ platforms. And maybe even to lower targets. Everything is now centrilized into bdk folder. Every module or project can utilize it by simply including it. This is just the start and it will continue to improve.
178 lines
7.1 KiB
C
178 lines
7.1 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "max7762x.h"
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#include "max77620.h"
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#include "../soc/i2c.h"
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#include "../utils/util.h"
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#define REGULATOR_SD 0
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#define REGULATOR_LDO 1
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typedef struct _max77620_regulator_t
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{
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u8 type;
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const char *name;
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u8 reg_sd;
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u32 mv_step;
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u32 mv_min;
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u32 mv_default;
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u32 mv_max;
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u8 volt_addr;
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u8 cfg_addr;
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u8 volt_mask;
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u8 enable_mask;
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u8 enable_shift;
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u8 status_mask;
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u8 fps_addr;
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u8 fps_src;
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u8 pd_period;
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u8 pu_period;
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} max77620_regulator_t;
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static const max77620_regulator_t _pmic_regulators[] = {
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{ REGULATOR_SD, "sd0", 0x16, 12500, 600000, 625000, 1400000, MAX77620_REG_SD0, MAX77620_REG_SD0_CFG, MAX77620_SD0_VOLT_MASK, MAX77620_SD_POWER_MODE_MASK, MAX77620_SD_POWER_MODE_SHIFT, 0x80, MAX77620_REG_FPS_SD0, 1, 7, 1 },
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{ REGULATOR_SD, "sd1", 0x17, 12500, 600000, 1125000, 1125000, MAX77620_REG_SD1, MAX77620_REG_SD1_CFG, MAX77620_SD1_VOLT_MASK, MAX77620_SD_POWER_MODE_MASK, MAX77620_SD_POWER_MODE_SHIFT, 0x40, MAX77620_REG_FPS_SD1, 0, 1, 5 },
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{ REGULATOR_SD, "sd2", 0x18, 12500, 600000, 1325000, 1350000, MAX77620_REG_SD2, MAX77620_REG_SD2_CFG, MAX77620_SDX_VOLT_MASK, MAX77620_SD_POWER_MODE_MASK, MAX77620_SD_POWER_MODE_SHIFT, 0x20, MAX77620_REG_FPS_SD2, 1, 5, 2 },
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{ REGULATOR_SD, "sd3", 0x19, 12500, 600000, 1800000, 1800000, MAX77620_REG_SD3, MAX77620_REG_SD3_CFG, MAX77620_SDX_VOLT_MASK, MAX77620_SD_POWER_MODE_MASK, MAX77620_SD_POWER_MODE_SHIFT, 0x10, MAX77620_REG_FPS_SD3, 0, 3, 3 },
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{ REGULATOR_LDO, "ldo0", 0x00, 25000, 800000, 1200000, 1200000, MAX77620_REG_LDO0_CFG, MAX77620_REG_LDO0_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO0, 3, 7, 0 },
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{ REGULATOR_LDO, "ldo1", 0x00, 25000, 800000, 1050000, 1050000, MAX77620_REG_LDO1_CFG, MAX77620_REG_LDO1_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO1, 3, 7, 0 },
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{ REGULATOR_LDO, "ldo2", 0x00, 50000, 800000, 1800000, 3300000, MAX77620_REG_LDO2_CFG, MAX77620_REG_LDO2_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO2, 3, 7, 0 },
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{ REGULATOR_LDO, "ldo3", 0x00, 50000, 800000, 3100000, 3100000, MAX77620_REG_LDO3_CFG, MAX77620_REG_LDO3_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO3, 3, 7, 0 },
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{ REGULATOR_LDO, "ldo4", 0x00, 12500, 800000, 850000, 850000, MAX77620_REG_LDO4_CFG, MAX77620_REG_LDO4_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO4, 0, 7, 1 },
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{ REGULATOR_LDO, "ldo5", 0x00, 50000, 800000, 1800000, 1800000, MAX77620_REG_LDO5_CFG, MAX77620_REG_LDO5_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO5, 3, 7, 0 },
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{ REGULATOR_LDO, "ldo6", 0x00, 50000, 800000, 2900000, 2900000, MAX77620_REG_LDO6_CFG, MAX77620_REG_LDO6_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO6, 3, 7, 0 },
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{ REGULATOR_LDO, "ldo7", 0x00, 50000, 800000, 1050000, 1050000, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO7, 1, 4, 3 },
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{ REGULATOR_LDO, "ldo8", 0x00, 50000, 800000, 1050000, 1050000, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO8, 3, 7, 0 }
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};
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static void _max77620_try_set_reg(u8 reg, u8 val)
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{
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u8 tmp;
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do
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{
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, reg, val);
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tmp = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, reg);
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} while (val != tmp);
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}
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int max77620_regulator_get_status(u32 id)
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{
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if (id > REGULATOR_MAX)
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return 0;
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const max77620_regulator_t *reg = &_pmic_regulators[id];
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if (reg->type == REGULATOR_SD)
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return (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_STATSD) & reg->status_mask) ? 0 : 1;
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return (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, reg->cfg_addr) & 8) ? 1 : 0;
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}
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int max77620_regulator_config_fps(u32 id)
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{
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if (id > REGULATOR_MAX)
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return 0;
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const max77620_regulator_t *reg = &_pmic_regulators[id];
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_max77620_try_set_reg(reg->fps_addr,
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(reg->fps_src << MAX77620_FPS_SRC_SHIFT) | (reg->pu_period << MAX77620_FPS_PU_PERIOD_SHIFT) | (reg->pd_period));
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return 1;
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}
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int max77620_regulator_set_voltage(u32 id, u32 mv)
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{
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if (id > REGULATOR_MAX)
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return 0;
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const max77620_regulator_t *reg = &_pmic_regulators[id];
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if (mv < reg->mv_min || mv > reg->mv_max)
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return 0;
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u32 mult = (mv + reg->mv_step - 1 - reg->mv_min) / reg->mv_step;
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u8 val = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, reg->volt_addr);
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val = (val & ~reg->volt_mask) | (mult & reg->volt_mask);
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_max77620_try_set_reg(reg->volt_addr, val);
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usleep(1000);
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return 1;
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}
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int max77620_regulator_enable(u32 id, int enable)
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{
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if (id > REGULATOR_MAX)
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return 0;
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const max77620_regulator_t *reg = &_pmic_regulators[id];
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u32 addr = reg->type == REGULATOR_SD ? reg->cfg_addr : reg->volt_addr;
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u8 val = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, addr);
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if (enable)
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val = (val & ~reg->enable_mask) | ((MAX77620_POWER_MODE_NORMAL << reg->enable_shift) & reg->enable_mask);
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else
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val &= ~reg->enable_mask;
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_max77620_try_set_reg(addr, val);
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usleep(1000);
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return 1;
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}
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// LDO only.
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int max77620_regulator_set_volt_and_flags(u32 id, u32 mv, u8 flags)
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{
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if (id > REGULATOR_MAX)
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return 0;
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const max77620_regulator_t *reg = &_pmic_regulators[id];
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if (mv < reg->mv_min || mv > reg->mv_max)
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return 0;
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u32 mult = (mv + reg->mv_step - 1 - reg->mv_min) / reg->mv_step;
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u8 val = ((flags << reg->enable_shift) & ~reg->volt_mask) | (mult & reg->volt_mask);
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_max77620_try_set_reg(reg->volt_addr, val);
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usleep(1000);
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return 1;
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}
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void max77620_config_default()
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{
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for (u32 i = 1; i <= REGULATOR_MAX; i++)
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{
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i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CID4);
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max77620_regulator_config_fps(i);
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max77620_regulator_set_voltage(i, _pmic_regulators[i].mv_default);
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if (_pmic_regulators[i].fps_src != MAX77620_FPS_SRC_NONE)
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max77620_regulator_enable(i, 1);
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}
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_max77620_try_set_reg(MAX77620_REG_SD_CFG2, 4);
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}
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void max77620_low_battery_monitor_config(bool enable)
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{
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_max77620_try_set_reg(MAX77620_REG_CNFGGLBL1,
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MAX77620_CNFGGLBL1_LBDAC_EN | (enable ? MAX77620_CNFGGLBL1_MPPLD : 0) |
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MAX77620_CNFGGLBL1_LBHYST_200 | MAX77620_CNFGGLBL1_LBDAC_2800);
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}
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