mirror of
https://github.com/CTCaer/hekate
synced 2024-07-03 15:03:29 +00:00
185526d134
BDK will allow developers to use the full collection of drivers, with limited editing, if any, for making payloads for Nintendo Switch. Using a single source for everything will also help decoupling Switch specific code and easily port it to other Tegra X1/X1+ platforms. And maybe even to lower targets. Everything is now centrilized into bdk folder. Every module or project can utilize it by simply including it. This is just the start and it will continue to improve.
172 lines
3.9 KiB
C
172 lines
3.9 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018 balika011
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include "smmu.h"
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#include "../soc/ccplex.h"
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#include "../soc/t210.h"
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#include "../mem/mc_t210.h"
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#include "../utils/util.h"
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#include "../utils/aarch64_util.h"
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bool smmu_used = false;
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u8 *_pageheap = (u8 *)SMMU_HEAP_ADDR;
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//Enabling SMMU requires a TZ secure write: MC(MC_SMMU_CONFIG) = 1;
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u8 smmu_payload[] __attribute__((aligned(16))) = {
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0x41, 0x01, 0x00, 0x58, // 0x00: LDR X1, =0x70019010
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0x20, 0x00, 0x80, 0xD2, // 0x04: MOV X0, #0x1
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0x20, 0x00, 0x00, 0xB9, // 0x08: STR W0, [X1]
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0x1F, 0x71, 0x08, 0xD5, // 0x0C: IC IALLUIS
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0x9F, 0x3B, 0x03, 0xD5, // 0x10: DSB ISH
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0xFE, 0xFF, 0xFF, 0x17, // 0x14: B loop
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0x00, 0x00, 0x80, 0xD2, // 0x18: MOV X0, #0x0
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0x20, 0x00, 0x00, 0xB9, // 0x1C: STR W0, [X1]
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0x80, 0x00, 0x00, 0x58, // 0x20: LDR X0, =0x4002B000
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0x00, 0x00, 0x1F, 0xD6, // 0x28: BR X0
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0x10, 0x90, 0x01, 0x70, // 0x28: MC_SMMU_CONFIG
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0x00, 0x00, 0x00, 0x00, // 0x2C:
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0x00, 0x00, 0x00, 0x00, // 0x30: secmon address
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0x00, 0x00, 0x00, 0x00 // 0x34:
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};
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void *page_alloc(u32 num)
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{
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u8 *res = _pageheap;
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_pageheap += 0x1000 * num;
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memset(res, 0, 0x1000 * num);
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return res;
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}
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u32 *smmu_alloc_pdir()
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{
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u32 *pdir = (u32 *)page_alloc(1);
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for (int pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
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pdir[pdn] = _PDE_VACANT(pdn);
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return pdir;
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}
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void smmu_flush_regs()
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{
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(void)MC(MC_SMMU_PTB_DATA);
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}
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void smmu_flush_all()
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{
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MC(MC_SMMU_PTC_FLUSH) = 0;
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smmu_flush_regs();
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MC(MC_SMMU_TLB_FLUSH) = 0;
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smmu_flush_regs();
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}
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void smmu_init(u32 secmon_base)
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{
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MC(MC_SMMU_PTB_ASID) = 0;
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MC(MC_SMMU_PTB_DATA) = 0;
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MC(MC_SMMU_TLB_CONFIG) = 0x30000030;
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MC(MC_SMMU_PTC_CONFIG) = 0x28000F3F;
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MC(MC_SMMU_PTC_FLUSH) = 0;
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MC(MC_SMMU_TLB_FLUSH) = 0;
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// Set the secmon address
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*(u32 *)(smmu_payload + 0x30) = secmon_base;
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}
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void smmu_enable()
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{
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if (smmu_used)
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return;
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ccplex_boot_cpu0((u32)smmu_payload);
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smmu_used = true;
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msleep(150);
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smmu_flush_all();
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}
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bool smmu_is_used()
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{
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return smmu_used;
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}
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void smmu_exit()
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{
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*(u32 *)(smmu_payload + 0x14) = _NOP();
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}
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u32 *smmu_init_domain4(u32 dev_base, u32 asid)
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{
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u32 *pdir = smmu_alloc_pdir();
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MC(MC_SMMU_PTB_ASID) = asid;
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MC(MC_SMMU_PTB_DATA) = SMMU_MK_PDIR((u32)pdir, _PDIR_ATTR);
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smmu_flush_regs();
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MC(dev_base) = 0x80000000 | (asid << 24) | (asid << 16) | (asid << 8) | (asid);
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smmu_flush_regs();
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return pdir;
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}
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u32 *smmu_get_pte(u32 *pdir, u32 iova)
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{
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u32 ptn = SMMU_ADDR_TO_PFN(iova);
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u32 pdn = SMMU_ADDR_TO_PDN(iova);
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u32 *ptbl;
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if (pdir[pdn] != _PDE_VACANT(pdn))
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ptbl = (u32 *)((pdir[pdn] & SMMU_PFN_MASK) << SMMU_PDIR_SHIFT);
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else
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{
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ptbl = (u32 *)page_alloc(1);
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u32 addr = SMMU_PDN_TO_ADDR(pdn);
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for (int pn = 0; pn < SMMU_PTBL_COUNT; pn++, addr += SMMU_PAGE_SIZE)
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ptbl[pn] = _PTE_VACANT(addr);
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pdir[pdn] = SMMU_MK_PDE((u32)ptbl, _PDE_ATTR | _PDE_NEXT);
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smmu_flush_all();
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}
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return &ptbl[ptn % SMMU_PTBL_COUNT];
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}
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void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr)
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{
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for (int i = 0; i < cnt; i++)
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{
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u32 *pte = smmu_get_pte(pdir, addr);
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*pte = SMMU_ADDR_TO_PFN(page) | attr;
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addr += 0x1000;
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page += 0x1000;
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}
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smmu_flush_all();
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}
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u32 *smmu_init_for_tsec()
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{
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return smmu_init_domain4(MC_SMMU_TSEC_ASID, 1);
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}
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void smmu_deinit_for_tsec()
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{
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MC(MC_SMMU_PTB_ASID) = 1;
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MC(MC_SMMU_PTB_DATA) = 0;
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MC(MC_SMMU_TSEC_ASID) = 0;
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smmu_flush_regs();
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}
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